JPH10312455A - Access method to memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an access method to memory for outputting interlace only with one memory. SOLUTION: If the memory is DRAM, data of the next screen is successively written in an address of a read line by performing a read modify written in interlace reading of data of a written one screen. The initial data is written by successive address in an order of lines A to H and read out in the order of the lines 1→3→5→7→2→4→6→8 in the interlace reading of A→C→E→G→B→D→F→H. In this case, the data of the next screen is inputted in the order of 1=A→2=C→3=E→4=G→5=B→6=D→7=F→8=H in the read modify writing and the interlace reading is performed in the order of A→E→B→F→C→G→D→H. Then, the data of one screen after the next screen is inputted in the order of 1=A→2=E→3=B→4=F→5=C→6=G→7=D→8=H and the interlace reading is performed in the order of A→B→C→D→E→F→G→H.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory for storing image data using a DRAM or the like.

2. Description of the Related Art In an image pickup apparatus using a progressive CCD, CCD data for one screen (one page) is once written into a memory, and interlaced reading for reading out the written one screen data by one line is performed. I do it. In this case, writing and reading must be performed simultaneously for real-time processing. For this purpose, a memory for two screens of CCD data is provided and one of them is alternately used for writing and the other is alternately used for reading. ing. Alternatively, a dedicated memory in which one port of a two-port memory is dedicated to writing and the other port is dedicated to reading is used.

[0003]

As a memory as described above,. DRA in a system with two screens of memory
M are typically used; As the dedicated memory, there is a video memory. However, in this case, two DRAMs must be provided, and in the other case, a dedicated memory called a video memory must be provided, which is disadvantageous in terms of cost and power consumption. Therefore, the present invention provides a memory access method for interlaced output, in which only one standard DRAM is required.

[0004]

SUMMARY OF THE INVENTION For this purpose, the present invention relates to a method of accessing a memory which enables writing immediately after reading to the same address, such as a read-modify-write function of a DRAM. 1 I wrote
In interlaced reading of screen data, data of the next screen is sequentially written to the read line address. That is, in the case of a DRAM, read-modify-write is performed at the time of interlaced reading of written one-screen data, so that data of the next screen is sequentially written to the read line address. Access method. This is executed by devising the order of specifying row addresses at the time of interlace reading.

In other words, when image data for one screen from the progressive CCD enters the memory, the one-screen data is
If it is the first time, first line → third line → fifth line ...
... Interlaced reading is performed in the order of the second line → the fourth line → the sixth line. At this time, in the present invention, for example, in the case of a DRAM, the read-modify-write function is used to sequentially write the image data of the next screen sent from the CCD to the read line. That is, the next data is written to the address at the same time as the reading. Therefore, when one screen data of the next screen is completely written into the memory, the first screen data of the previous screen is written.
The first line of the next screen enters the address of the line, the second line of the next screen enters the address of the third line of the previous screen, and the third line of the next screen enters the address of the fifth line of the previous screen.
Lines are entered in this order. Therefore, when the next screen data is interlaced, the address of the first line of the previous screen → the address of the fifth line of the previous screen... The address of the third line of the previous screen → the address of the previous screen The data is read out in the order of the address of the seventh line. The same procedure may be followed for data subsequent to the next screen. In this case, assuming 2 ⁿ as the number of lines, the operation of the physical address returns to the original state after n times of screen processing. For example, if n = 9 (512 lines), the process returns to the first normal addressing order every nine screen processes.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of timing for a read-modify-write operation of a DRAM used as a memory for image data. For the RAS signal and the CAS signal, both the output control signal OE and the write control signal WE are activated during one cycle of the CAS signal at the timing of the page mode. That is, data is first read by activating output control signal OE, and following the end of the reading, write control signal WE is activated to write data to the same address. The writing of image data and the interlaced reading thereof using this are schematically shown in FIG.
It is shown assuming the case of 8 lines on the screen.

First, as shown in FIG. 2A, the first one-screen data is written in a continuous address in the order of rows A to H. Then, when interlaced reading is performed, addresses are specified in the order of A row → C row → E row → G row → B row → D row → F row → H row, and accordingly, the first line → third line Data is read in the order of line → fifth line → seventh line → second line → fourth line → sixth line → eighth line. At the time of this interlaced reading, the read / write as shown in FIG.
A modify write is executed, and data of the next screen sent from the CCD is sequentially written. Then, Figure 2
As shown in (b), the data of the next screen is the first line = A
Line → 2nd line = C line → 3rd line = E line → 4th line = G line → 5th line = B line → 6th line = D line → 7th line = F line → 8th line = H line It will be in the order of.

Subsequently, when interlaced reading of the next screen data shown in FIG. 2B is performed, row A → row E → row B →
By specifying addresses in the order of F line → C line → G line → D line → H line, interlaced reading can be executed as in the previous screen. When the read-modify-write operation is performed at the time of interlaced reading of the next screen, the data of the next screen is changed from the first line = A line to the second line = E line to the third line as shown in FIG. Line = B line → 4th line = F line → 5th line = C line → 6th line = G line → 7th line = D line → 8th line = H line.

Further, when performing interlaced reading of the screen data successively in FIG. 2 (c), row A → row B → row C →
The addresses are specified in the order of D row → E row → F row → G row → H row, and as a result, the state returns to the continuous address state of FIG. Thereafter, the writing patterns of the three patterns of FIGS. 2A, 2B, and 2C are repeated.

As described above, in the case of 8 lines (= 2 ³ ), the write address of each line is continuous for the first screen, every other row for the second screen, every third row for the third screen, and then returns to the continuous state. , Which is a repetition of three writing patterns in all. In other words, if the screen data has 2 ⁿ lines, the write address form of n patterns may be repeated in all. Even in a memory without a read-modify-write function, the same effect can be obtained by performing read and write to the same address.

[0011]

According to the present invention, it is possible to use only one memory while maintaining the processing performance of simultaneous reading and writing, which contributes to cost reduction and lower power consumption of the apparatus.

[Brief description of the drawings]

FIG. 1 is a signal waveform diagram showing the timing of a control signal for performing read-modify-write of a DRAM.

FIG. 2 is a schematic diagram of a DRAM for explaining a memory access method according to the present invention.

Claims (2)

[Claims] In a memory access method in which writing to the same address can be performed immediately after reading, the written address is
An access method characterized by sequentially writing data of a next screen to an address of a read line at the time of interlaced reading of screen data. 2. A method for accessing a DRAM, comprising the steps of:
An access method characterized by sequentially writing data of the next screen to an address of a read line by performing a modify write.