CN101897119A - 具有多个装置的系统中的时钟再生和时序方法以及具有可变数据对准的存储器控制器 - Google Patents
具有多个装置的系统中的时钟再生和时序方法以及具有可变数据对准的存储器控制器 Download PDFInfo
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- CN101897119A CN101897119A CN2008801205016A CN200880120501A CN101897119A CN 101897119 A CN101897119 A CN 101897119A CN 2008801205016 A CN2008801205016 A CN 2008801205016A CN 200880120501 A CN200880120501 A CN 200880120501A CN 101897119 A CN101897119 A CN 101897119A
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- clock signal
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1093—Input synchronization
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06506—Wire or wire-like electrical connections between devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dram (AREA)
- Manipulation Of Pulses (AREA)
- Memory System (AREA)
Abstract
Description
Claims (64)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110397274.5A CN102623039B (zh) | 2007-12-14 | 2008-12-04 | 具有多个装置的系统中的时钟再生和时序方法以及具有可变数据对准的存储器控制器 |
Applications Claiming Priority (11)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US1378407P | 2007-12-14 | 2007-12-14 | |
US61/013784 | 2007-12-14 | ||
US1990708P | 2008-01-09 | 2008-01-09 | |
US61/019907 | 2008-01-09 | ||
US3960508P | 2008-03-26 | 2008-03-26 | |
US61/039605 | 2008-03-26 | ||
US12/168,091 US8781053B2 (en) | 2007-12-14 | 2008-07-04 | Clock reproducing and timing method in a system having a plurality of devices |
US12/168091 | 2008-07-04 | ||
US12/325074 | 2008-11-28 | ||
US12/325,074 US8467486B2 (en) | 2007-12-14 | 2008-11-28 | Memory controller with flexible data alignment to clock |
PCT/CA2008/002108 WO2009076748A1 (en) | 2007-12-14 | 2008-12-04 | Clock reproducing and timing method in a system having a plurality of devices and memory controller with flexible data alignment |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110397274.5A Division CN102623039B (zh) | 2007-12-14 | 2008-12-04 | 具有多个装置的系统中的时钟再生和时序方法以及具有可变数据对准的存储器控制器 |
Publications (2)
Publication Number | Publication Date |
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CN101897119A true CN101897119A (zh) | 2010-11-24 |
CN101897119B CN101897119B (zh) | 2014-04-30 |
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Family Applications (2)
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CN201110397274.5A Expired - Fee Related CN102623039B (zh) | 2007-12-14 | 2008-12-04 | 具有多个装置的系统中的时钟再生和时序方法以及具有可变数据对准的存储器控制器 |
CN200880120501.6A Expired - Fee Related CN101897119B (zh) | 2007-12-14 | 2008-12-04 | 具有多个装置的系统中的时钟再生和时序方法以及具有可变数据对准的存储器控制器 |
Family Applications Before (1)
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CN201110397274.5A Expired - Fee Related CN102623039B (zh) | 2007-12-14 | 2008-12-04 | 具有多个装置的系统中的时钟再生和时序方法以及具有可变数据对准的存储器控制器 |
Country Status (7)
Country | Link |
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US (3) | US8467486B2 (zh) |
EP (1) | EP2220766A4 (zh) |
JP (3) | JP5523333B2 (zh) |
KR (2) | KR101647849B1 (zh) |
CN (2) | CN102623039B (zh) |
TW (1) | TWI519077B (zh) |
WO (1) | WO2009076748A1 (zh) |
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CN104063340A (zh) * | 2013-03-14 | 2014-09-24 | 奥特拉有限公司 | 用于dqs自动门控的电路和方法 |
CN104506179A (zh) * | 2014-12-25 | 2015-04-08 | 中国电子科技集团公司第二十九研究所 | 多通道时钟分配及信号同步和分配电路及其选控方法 |
CN105027444A (zh) * | 2013-03-15 | 2015-11-04 | 英特尔公司 | 集成时钟差分缓冲 |
CN105190585A (zh) * | 2013-03-15 | 2015-12-23 | 高通股份有限公司 | 基于操作速度的数据总线反相(dbi)编码 |
CN107005231A (zh) * | 2014-12-25 | 2017-08-01 | 英特尔公司 | 用于在高性能互连中定中心的方法、设备、系统 |
CN108646984A (zh) * | 2018-05-16 | 2018-10-12 | 华为技术有限公司 | 一种dqs位置调整方法和装置 |
CN108986860A (zh) * | 2017-06-01 | 2018-12-11 | 三星电子株式会社 | 非易失性存储器 |
CN113496736A (zh) * | 2020-03-19 | 2021-10-12 | 铠侠股份有限公司 | 半导体集成电路、存储器控制器以及存储器系统 |
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US8467486B2 (en) * | 2007-12-14 | 2013-06-18 | Mosaid Technologies Incorporated | Memory controller with flexible data alignment to clock |
US8781053B2 (en) * | 2007-12-14 | 2014-07-15 | Conversant Intellectual Property Management Incorporated | Clock reproducing and timing method in a system having a plurality of devices |
US7957173B2 (en) | 2008-10-14 | 2011-06-07 | Mosaid Technologies Incorporated | Composite memory having a bridging device for connecting discrete memory devices to a system |
US8134852B2 (en) | 2008-10-14 | 2012-03-13 | Mosaid Technologies Incorporated | Bridge device architecture for connecting discrete memory devices to a system |
US8549209B2 (en) | 2008-11-04 | 2013-10-01 | Mosaid Technologies Incorporated | Bridging device having a configurable virtual page size |
US8521980B2 (en) * | 2009-07-16 | 2013-08-27 | Mosaid Technologies Incorporated | Simultaneous read and write data transfer |
US9160349B2 (en) * | 2009-08-27 | 2015-10-13 | Micron Technology, Inc. | Die location compensation |
US8966208B2 (en) * | 2010-02-25 | 2015-02-24 | Conversant Ip Management Inc. | Semiconductor memory device with plural memory die and controller die |
US8825967B2 (en) | 2011-12-08 | 2014-09-02 | Conversant Intellectual Property Management Inc. | Independent write and read control in serially-connected devices |
US8710879B2 (en) * | 2012-07-06 | 2014-04-29 | Silicon Integrated System Corp. | Apparatus and method for multiplying frequency of a clock signal |
US9478502B2 (en) * | 2012-07-26 | 2016-10-25 | Micron Technology, Inc. | Device identification assignment and total device number detection |
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US9825755B2 (en) * | 2013-08-30 | 2017-11-21 | Qualcomm Incorporated | Configurable clock tree |
US9478268B2 (en) * | 2014-06-12 | 2016-10-25 | Qualcomm Incorporated | Distributed clock synchronization |
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US9698967B2 (en) | 2015-09-11 | 2017-07-04 | Apple Inc. | Dual path source synchronous interface |
US10019170B2 (en) | 2016-03-30 | 2018-07-10 | Micron Technology, Inc. | Controlling timing and edge transition of a delayed clock signal and data latching methods using such a delayed clock signal |
US10254782B2 (en) * | 2016-08-30 | 2019-04-09 | Micron Technology, Inc. | Apparatuses for reducing clock path power consumption in low power dynamic random access memory |
JP2019057344A (ja) | 2017-09-20 | 2019-04-11 | 東芝メモリ株式会社 | メモリシステム |
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US12046271B2 (en) * | 2022-08-31 | 2024-07-23 | Changxin Memory Technologies, Inc. | Clock system and memory |
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Also Published As
Publication number | Publication date |
---|---|
US20090154285A1 (en) | 2009-06-18 |
WO2009076748A1 (en) | 2009-06-25 |
TW201214975A (en) | 2012-04-01 |
JP5523333B2 (ja) | 2014-06-18 |
US20130243137A1 (en) | 2013-09-19 |
JP2011507358A (ja) | 2011-03-03 |
CN102623039A (zh) | 2012-08-01 |
JP2012060677A (ja) | 2012-03-22 |
JP2012085318A (ja) | 2012-04-26 |
CN101897119B (zh) | 2014-04-30 |
JP5562922B2 (ja) | 2014-07-30 |
TWI519077B (zh) | 2016-01-21 |
EP2220766A4 (en) | 2012-02-01 |
US8467486B2 (en) | 2013-06-18 |
KR101582020B1 (ko) | 2015-12-31 |
CN102623039B (zh) | 2015-08-19 |
KR101647849B1 (ko) | 2016-08-11 |
KR20140007468A (ko) | 2014-01-17 |
JP5432976B2 (ja) | 2014-03-05 |
US8837655B2 (en) | 2014-09-16 |
KR20100092930A (ko) | 2010-08-23 |
EP2220766A1 (en) | 2010-08-25 |
US20150082072A1 (en) | 2015-03-19 |
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