CN101853813A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN101853813A
CN101853813A CN200910165189A CN200910165189A CN101853813A CN 101853813 A CN101853813 A CN 101853813A CN 200910165189 A CN200910165189 A CN 200910165189A CN 200910165189 A CN200910165189 A CN 200910165189A CN 101853813 A CN101853813 A CN 101853813A
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gate stack
silicon
oxide layer
semiconductor device
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徐振斌
郑光茗
庄学理
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体装置及其制造方法。上述半导体装置的制造方法包括形成一栅极堆叠于一硅基底之上，形成虚置间隙子于该栅极堆叠的侧壁上，各向同性地蚀刻该硅基底以形成凹陷区于该栅极堆叠的一侧，形成一半导体材料于所述凹陷区之内，该半导体材料相异于该硅基底；移除所述虚置间隙子，形成多个栅极间隙子层，其具有氧化物-氮化物-氧化物配置于该栅极堆叠与该半导体材料上，以及蚀刻所述间隙子层以形成栅极间隙子于该栅极堆叠的侧壁上。本发明优点在于该应变界面可提升半导体装置的载流子迁移率；另一优点在于多层配置的间隙子以及最佳化的蚀刻步骤以克服间隙子残留问题；再一优点在于所述方法可相容于CMOS工艺流程且可容易地实行。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法，特别涉及间隙子于应变硅中的半导体装置及其制造方法。
背景技术
半导体集成电路(IC)工业已经历快速成长。集成电路材料与设计的技术进步已造就数个IC世代，相较于前一世代，各世代具有更小且更复杂的电路。然而，这些进步也增加了IC的工艺和制造的复杂度，并且为了实现这些技术进步，需要相似的研发于IC工艺和制造。在集成电路演化的方向上，功能性的密度(也即每芯片区域中内连线元件的数目)已逐渐地增加，随着几何尺寸(也即使用制造技术所能创造的最小元件(或线))降低。此微缩化一般所提供的益处为增加制造效率及降低相关的成本。此微缩化也造成相对地高功率散失值，可通过使用低高功率散失装置例如互补式金属-氧化物-半导体(CMOS)装置解决。
在半导体制造工艺中，间隙子可形成于一栅极堆叠的侧壁上。上述间隙子可通过以下的方法形成，包括沉积一适当的间隙子材料，及蚀刻该材料以形成所欲的间隙子轮廓。然而，传统的形成间隙子的方法会留下不想要的间隙子材料残留。
发明内容
为了解决现有技术存在的上述问题，本发明的实施例提供一种半导体装置的制造方法。上述方法包括：提供一硅基底具有一浅沟槽隔离物形成于其上；形成一栅极堆叠于该硅基底之上；形成虚置间隙子于该栅极堆叠的侧壁上；形成一凹陷区于该硅基底中，其中该凹陷区为夹置于该栅极堆叠与该浅沟槽隔离物之间；外延成长一半导体材料于该凹陷区之内，其中该半导体材料相异于该硅基底；移除该虚置间隙子；形成一第一氧化硅层于该栅极堆叠和该半导体材料之上；形成一氮化硅层于该第一氧化硅层之上；形成一第二氧化硅层于该氮化硅层之上；实施一第一干蚀刻工艺以移除一部分的该第二氧化硅层；实施一第二干蚀刻工艺以移除一部分的该氮化硅层；以及实施一第三干蚀刻工艺以移除一部分的该第一氧化硅层，借此形成栅极间隙子于该栅极堆叠的侧壁上，其中各栅极间隙子包括一残留部分的该第一氧化硅层、该氮化硅层、及该第二氧化硅层。
本发明的实施例另提供一种半导体装置的制造方法。上述方法包括：形成一栅极堆叠于一硅基底之上；形成虚置间隙子于该栅极堆叠的侧壁上；各向同性地蚀刻该硅基底以形成凹陷区于该栅极堆叠的一侧；形成一半导体材料于所述凹陷区之内，其中该半导体材料相异于该硅基底；移除所述虚置间隙子；形成多个栅极间隙子层，其具有氧化物-氮化物-氧化物配置于该栅极堆叠与该半导体材料上；以及蚀刻所述间隙子层以形成栅极间隙子于该栅极堆叠的侧壁上。
本发明的实施例又提供一半导体装置。上述半导体装置包括：一硅基底具有一硅区域、多个应变半导体材料区域、及一浅沟槽隔离物区域，其中所述应变半导体材料区域之一夹置于该硅区域和该浅沟槽隔离物区域之间，以及其中所述应变半导体材料区域包括一各向同性轮廓；以及一晶体管包括：一栅极堆叠于该硅区域上；多个间隙子形成于该栅极堆叠的侧壁上，其中各间隙子包括一氮化层夹置于一第一氧化层和一第二氧化层之间；以及轻掺杂源极/漏极(LDD)区各形成于该硅区域的一部分位于该间隙子下方以及形成于应变半导体材料区域的一部分。
综上所述，所揭示的方法和装置的优点为在一半导体装置的硅基底中形成多个凹陷区域，以及以应变半导体材料填入凹陷区域中，以创造出应变界面于该基地和半导体材料之间。上述所揭示的也包括间隙子具有多层的配置且通过实施最佳化的干蚀刻工艺形成。本发明优点之一在于该应变界面，其位于该凹陷区域中的半导体材料与该硅基底之间，可提升半导体装置的载流子迁移率。该载流子迁移率允许较大的沟道电流而无须增加栅极电压；另一优点在于多层配置的间隙子以及最佳化的蚀刻步骤以克服间隙子残留问题；再一优点在于所揭示的方法可相容于CMOS工艺流程且可容易地实行。
为使本发明能更明显易懂，下文特举实施例，并配合附图，作详细说明如下。
附图说明
图1为一制造流程图显示根据本发明揭示的各种型态形成间隙子的方法；以及
图2A-图2J为根据图1所揭示的方法，半导体元件于各制造阶段的剖面示意图。
上述附图中的附图标记说明如下：
100～制造方法；
110-190～步骤区块；
200～半导体元件；
202～基底；
204～绝缘结构；
206和208～有源区域；
210～栅极堆叠；
212～高介电常数介电层；
213～金属层；
214～有源材料层；
216～硬掩模层；
218～虚置间隙子；
220和222～凹陷区域；
230和232～半导体材料；
235～轻掺杂源极/漏极区域；
240～第一间隙子层；
250～第二间隙子层；
260～第三间隙子层；
265～结构；
275～间隙子；
310～蚀刻工艺；
315～选择性外延成长工艺；
320～第一蚀刻工艺；
330～第二蚀刻工艺；
340～第三蚀刻工艺。
具体实施方式
以下以各实施例详细说明并伴随着附图说明的范例，做为本发明的参考依据。在附图或说明书描述中，相似或相同的部分皆使用相同的附图标记。且在附图中，实施例的形状或是厚度可扩大，并以简化或是方便标示。再者，附图中各元件的部分将以分别描述说明，值得注意的是，图中未示出或描述的元件，为所属技术领域中普通技术人员所知的形式，另外，特定的实施例仅为揭示本发明使用的特定方式，其并非用以限定本发明。
图1为一制造流程图，其显示形成间隙子的方法100根据本发明揭示的各种型态。图2A-图2J为根据图1的方法100，半导体元件200于各制造阶段的剖面示意图。该半导体元件200可为一体集成电路，或其中的一部分，此集成电路包括存储器电路和/或逻辑电路例如P-沟道场效应晶体管(pFET)，N-沟道场效应晶体管(nFET)，金属-氧化物-半导体场效应晶体管(MOSFET)，或互补式金属-氧化物-半导体(CMOS)晶体管。应注意的是部分的半导体元件200的结构可通过CMOS工艺流程制造。有鉴于此，可了解的是，在图1的方法之前、当时、或之后可提供额外的工艺，以及许多其他的工艺仅会在此作简略的描述。
请参阅图1，制造方法100始于步骤区块110在其中一栅极堆叠形成于一硅基底之上，此硅基底具有一浅沟槽隔离物。请参阅图2A，其显示一半导体元件200处于制造过程的中间阶段。该半导体元件200可包括一基底202，例如一硅基底。该基底202可包括各种掺杂型态，根据公知的设计需求而定。该基底202也可包括其他的基本的半导体，例如锗和钻石。另择一地，该基底202可包括一化合物半导体和/或一合金半导体。在本实施例中，该基底202包括一硅材料。
该半导体元件200还可包括一绝缘结构204供基底中的有源区域206和208间绝缘。绝缘结构204包括一介电材料及可由氧化硅、氮化硅、氮氧化硅、氟掺杂硅酸盐(FSG)和/或公知的介电材料而形成。上述有源区域206和208可配置一N-型金属-氧化物-半导体晶体管装置(简称为NMOS)，或一P-型金属-氧化物-半导体晶体管装置(简称为PMOS)。
该半导体元件200可包括一栅极堆叠210形成于有源区域208之上。该栅极堆叠210可包括一界面层(未示出)形成于该基底202之上。该界面层可包括氧化硅(SiO2)或氮氧化硅(SiON)具有厚度约5到10埃
Figure B2009101651899D0000051
栅极堆叠210还可包括一高介电常数介电层212形成于该基底202之上。该高介电常数介电层212可包括氧化铪(HfOx)。另择一地，该高介电常数介电层212可选择性地包括其他高介电常数介电材料，例如LaO、AlO、ZrO、TiO、Ta2O5、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba，Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化硅、或其他适合的材料。该高介电常数介电层212可包含一厚度范围介于约10到40埃高介电常数介电层212可由原子层沉积法(ALD)或其他适合的技术形成。
栅极堆叠210还可包括一金属层213形成于高介电常数介电层212之上。该栅极堆叠210可包括任一金属材料适用于形成金属栅极或其一部分，包括低功函数层、衬垫层、界面层、晶种层、黏结层、阻挡层等。例如，该金属层可包括TiN、TaN、ZrN、HfN、VN、NbN、CrN、MoN、WN、TiAl、TiAlN、或其任意组合。该金属层213可通过ALD、物理气相沉积法(PVD或溅镀)、化气相沉积法(CVD)，或其他适合的技术形成。该栅极堆叠210还可包括一有源材料层214形成于该金属层213之上。该有源材料层214可为一金属层或者可包括Al、Cu、W、Ti、Ta、Cr、V、Nb、Zr、Hf、Mo、Ni、Co、或其任意组合。另择一地，该有源材料层214可通过各种沉积技术形成，例如PVD、CVD、ALD、电镀、或其他适合的技术。
该栅极堆叠210也可包括一硬掩模层216形成于该有源材料层214之上。该硬掩模层216可使用于图案化底下层，且可包括一介电材料例如氧化硅、氮化硅、氮氧化硅、或碳化硅。在本实施例中，该硬掩模层216包括氮化硅。虚置间隙子218也可形成于栅极堆叠210的任一侧上。该虚置间隙子218可包括介电材料例如氮化硅或氧化硅。在本实施例中，该虚置间隙子218包括氧化硅。该虚置间隙子218可被形成，通过沉积虚置间隙子层于该栅极堆叠210与硅基底202上，接着施以一干蚀刻工艺于该虚置间隙子层。
继续进行该方法100的步骤区块120在其中形成一凹陷区域于该基底中，其中该凹陷区域夹置于该栅极堆叠与该浅沟槽隔离物之间。请参阅图2B，可实施一蚀刻工艺310于该基底202以形成凹陷区域220和222。在本实施例中，该蚀刻工艺310可包括一蚀刻工艺其形成一等方向性的轮廓。该蚀刻工艺310可包括一干蚀刻工艺使用等离子体气体或一湿蚀刻工艺使用酸。例如，该蚀刻工艺310可使用HBr等离子体气体做为蚀刻剂。再者，在本实施例中，该蚀刻工艺310可调整一偏压于该等离子体气体以达到所望的轮廓于凹陷区域220和222中，其包括一等方向性的轮廓如本实施例的图2B所示。在其他的实施例中，可使用一湿蚀刻工艺，其包括HF酸做为蚀刻剂，以形成等方向性的轮廓于凹陷区域220和222中。在其他的实施例中，可实行结合干式及湿式的蚀刻工艺以形成等方向性的轮廓。如同先前所述，该浅沟槽隔离物(STI)204可包括介电材料而该基底202包括硅材料，STI 204的介电材料和基底202的硅材料之间可具有蚀刻选择率，使得蚀刻工艺310不会将STI 204蚀刻掉。因此，当该栅极204位于次邻于STI 204蚀，蚀刻工艺310可停止或中断于STI 204，使得STI 204形成该于凹陷区域222的边界。当后续地形成侧壁或栅极间隙子时，此可能导致发生残留物移除的问题，此后将进一步讨论。
继续进行方法100的步骤区块130在其中外延成长半导体材料于该凹陷区域中。请参阅图2C，可将半导体材料230和232相对地形成于凹陷区域220和222中，通过一选择性外延成长(SEG)工艺315或其他适合的外延技术工艺。该选择性外延成长工艺315可使用一特殊的CVD工艺。例如，该特殊的CVD工艺可实行于低的沉积速率或低的基底温度。另择一地，可使用ALD工艺做为选择性外延成长工艺315。半导体材料230和232可为相异于硅基底202的材料。通过完成此创造应变于半导体材料230和232与硅基底202，使得可提升有源区域208中的载流子迁移率，其可允许较大的沟道电流而不增加栅极电压。因此，该半导体材料230和232可被称为“应变”半导体材料，以及凹陷区域222中硅基底202与半导体材料232之间的界面可被称为“应变”界面。本实施例的先进之处在于因应变结构而提升载流子迁移率。额外地，该应变结构升起于该硅基底202上方。在一实施例中，该有源区域208可为一PMOS元件，以及该半导体材料230和232可包括硅锗(SiGe)。在另一实施例中，该有源区域208可为一NMOS元件，以及该半导体材料230和232可包括碳化硅(SiC)。然而，已观察到该SEG工艺315可能无法成长半导体材料232于介电材料例如STI 204上，当半导体材料232典型地使用SEG工艺315成长于一晶体面例如硅基底202。其结果为，形成于该凹陷区域222中的半导体材料232可具有一倾斜的表面，如图2C所示。
请参阅图2D，可通过蚀刻工艺移除该虚置间隙子218。在蚀刻完该虚置间隙子218之后，可形成轻掺杂源极/漏极(简称为LDD)区域235于硅基底202位于栅极堆叠210的一侧，通过本技术领域所公知的离子注入法或扩散工艺。在一实施例中，该有源区域208可为一PMOS元件，且P-型掺杂物例如硼可注入于该PMOS元件208中。在另一实施例中，该有源区域208可为一NMOS元件，且N-型掺杂物例如磷或砷可注入于该NMOS元件208中。如图2D所示，一部分的LDD区域235可形成于硅基底202，另一部分的LDD区域235可形成于半导体材料230和232相对于凹陷区域220和222中。
继续进行方法100的步骤区块140在其中形成第一氧化硅层于该栅极堆叠和该半导体材料之上。请参阅图2E，可通过CVD、ALD、或其他适当的技术，形成一间隙子层240于硅基底202和栅极堆叠210之上。该间隙子层240可包括一氧化物材料例如氧化硅。该间隙子层240可包含一厚度范围大抵介于30埃至200埃。
继续进行方法100的步骤区块150在其中形成一氮化硅层于该第一氧化硅层之上。请参阅图2F，可通过CVD、ALD、或其他适当的技术，形成一间隙子层250于间隙子层240之上。该间隙子层250可包括一氮化物材料例如氮化硅。该间隙子层250可包含一厚度范围大抵介于30埃至200埃。
继续进行方法100的步骤区块160在其中形成一第二氧化硅层于该氮化硅间隙层之上。请参阅图2G，可通过本技术领域所公知的技术，例如CVD或ALD，形成一间隙子层260于间隙子层250之上。该间隙子层260可包括一氧化物材料例如氧化硅。该间隙子层260可包含一厚度范围大抵介于100埃至1000埃。应注意的是，间隙子层260的厚度可分别地大于间隙子层240和250的厚度。有鉴于此，间隙子层260愈厚，可使其愈容易受控制且于后续的蚀刻工艺中最佳化该侧壁/栅极间隙子的临界维度(critical dimension)，将于以下内容中讨论。
继续进行方法100的步骤区块170在其中实施一第一干蚀刻工艺以移除一部分的第二氧化硅层。请参阅图2H，可实施蚀刻工艺320于间隙子层260。该蚀刻工艺320可为一干蚀刻工艺且可包含一碳氟基等离子体气体做为一蚀刻剂。该蚀刻工艺320可移除位于该栅极堆叠210上方的一部分的该间隙子层260。该蚀刻工艺320也可移除位于覆盖半导体材料230和232分别于凹陷区域220和222中的一部分的该间隙子层260。因此，在蚀刻工艺320之后，一残留部分的间隙子层260可构成位于栅极堆叠210侧壁上结构265。该结构265的厚度可通过控制蚀刻工艺320的蚀刻速率，并且以可通过控制间隙子层260的初始地沉积步骤(于步骤区块160中)。该结构265可用于保护位于其下方的间隙子层240和250的部分，以避免于之后的蚀刻工艺中被蚀刻。该结构265也可用于避免桥接效应。再者，由于在本实施例中，间隙子层260包括氧化物材料及间隙子层250包括氮化物材料，因此在间隙子层250和260之间可具有充分的蚀刻选择率。因此，间隙子层250可作用为蚀刻工艺320的蚀刻终止层。
继续进行方法100的步骤区块180在其中实施一第二干蚀刻工艺以移除一部分的氮化硅层。请参阅图2I，可实施蚀刻工艺330于间隙子层250。该蚀刻工艺330可为一干蚀刻工艺，移除掉未被结构265保护的间隙子层250的部分。因此，蚀刻工艺330可移除位于栅极堆叠210上方的间隙子层250的部分。该蚀刻工艺330也可移除位于覆盖半导体材料230和232分别于凹陷区域220和222中的一部分的该间隙子层250。在本实施例中，该蚀刻工艺330可为一干蚀刻工艺且可包含一氢-氟基等离子体气体做为一蚀刻剂。再者，由于在本实施例中，间隙子层240包括氧化物材料及间隙子层250包括氮化物材料，因此在间隙子层240和250之间可具有充分的蚀刻选择率。因此，间隙子层240可作用为蚀刻工艺330的蚀刻终止层。
继续进行方法100的步骤区块190在其中实施一第三干蚀刻工艺以移除一部分的第一氧化硅层，由此形成栅极间隙子于栅极堆叠的侧壁上。请参阅图2J，可实施蚀刻工艺340于间隙子层240。该蚀刻工艺340可为一干蚀刻工艺，移除掉未被结构265保护的间隙子层240的部分。因此，蚀刻工艺340可移除位于栅极堆叠210上方的间隙子层240的部分。该蚀刻工艺340也可移除位覆盖半导体材料230和232分别于凹陷区域220和222中的一部分的该间隙子层240。在本实施例中，该蚀刻工艺340可为一干蚀刻工艺且可包含一碳氟基等离子体气体做为一蚀刻剂。该蚀刻工艺340可实质地移除完位于凹陷区域222中的半导体材料232上的间隙子层240，使得在凹陷区域222中的半导体材料232的上面并无残留。在实施蚀刻工艺340之后，可形成间隙子275于栅极堆叠210的侧壁上。该间隙子275可包括一残留的部分的间隙子层250夹置于该结构265与残留的部分的间隙子层240之间。
由此可观察到，若侧壁间隙子已经形成，通过形成一主要的间隙子材料于该基底和该栅极堆叠上，并通过实施干蚀刻工艺于该间隙子材料，可导致间隙子残留的问题。以传统的方法，形成一主要间隙子材料层于基底上，仅以一部分的间隙子材料填入该凹陷区域中。该蚀刻工艺，实施用以形成间隙子且移除位于该凹陷区域中间隙子材料，并非有效率的，因此导致留下间隙子材料残留于该凹陷区域中的应变结构上。该材料残留对于后续的工艺具有不利的效果，例如一离子注入工艺以形成源极/漏极区以及一硅化工艺以形成硅结构于源极/漏极区域及其他有源区域上。相较之下，本实施例可通过数种蚀刻工艺完全地移除位于该凹陷区域222中半导体材料232上的各种间隙子层。因此，本实施例的一优点为不会有不想要的间隙子材料残留存在于半导体装置200中。
应注意的是，可通过额外的步骤继续进行方法100，以完成制造该半导体装置200。例如，通过离子注入法或扩散适当的N-型或P-型掺杂物，形成重掺杂源极/漏极区于该基底202中，于该栅极堆叠210的一侧。该重掺杂源极/漏极区可实质地对准于结构265的外侧侧边。通过硅化工艺形成硅化物结构于源极/漏极区域及多晶硅层上。一接触蚀刻终止层(CESL)可形成于该基底上。一层间介电(ILD)层可形成于CESL上。此外，多个接触与内连线可形成以建构半导体装置200的电性连接。
综上所述，在此所揭示的方法和装置的优点为在一半导体装置的硅基底中形成多个凹陷区域，以及以应变半导体材料填入所述凹陷区域中，以创造出应变界面于该基地和半导体材料之间。上述所揭示的也包括间隙子具有多层的配置且通过实施最佳化的干蚀刻工艺形成。通过这么做，本实施例提供多个优于公知技术的优点。本实施例的优点之一在于该应变界面，其位于该凹陷区域中的半导体材料与该硅基底之间，可提升半导体装置的载流子迁移率。该载流子迁移率允许较大的沟道电流而无须增加栅极电压。本实施例的另一优点在于多层配置的间隙子以及最佳化的蚀刻步骤以克服间隙子残留问题，其可能出现在公知技术中。本实施例的再一优点在于此处所揭示的方法可相容于CMOS工艺流程且可容易地实行。应注意的是，此处所揭示的各不同的实施例提供不同的优点，并且无特定的优点是必需被所有实施例所要求。
本发明虽以各种实施例揭示如上，然其并非用以限定本发明的范围，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可做些许的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (11)

1.一种半导体装置的制造方法，包括：
提供一硅基底具有一浅沟槽隔离物形成于其上；
形成一栅极堆叠于该硅基底之上；
形成虚置间隙子于该栅极堆叠的侧壁上；
形成一凹陷区于该硅基底中，其中该凹陷区为夹置于该栅极堆叠与该浅沟槽隔离物之间；
外延成长一半导体材料于该凹陷区之内，其中该半导体材料相异于该硅基底；
移除该虚置间隙子；
形成一第一氧化硅层于该栅极堆叠和该半导体材料之上；
形成一氮化硅层于该第一氧化硅层之上；
形成一第二氧化硅层于该氮化硅层之上；
实施一第一干蚀刻工艺以移除一部分的该第二氧化硅层；
实施一第二干蚀刻工艺以移除一部分的该氮化硅层；以及
实施一第三干蚀刻工艺以移除一部分的该第一氧化硅层，借此形成栅极间隙子于该栅极堆叠的侧壁上，其中各栅极间隙子包括一残留部分的该第一氧化硅层、该氮化硅层、及该第二氧化硅层。
2.如权利要求1所述的半导体装置的制造方法，其中形成该凹陷区的步骤包括通过一各向同性蚀刻工艺形成一凹陷区。
3.如权利要求2所述的半导体装置的制造方法，其中该各向同性蚀刻工艺包括一干蚀刻工艺，其利用一HBr等离子体气体；以及其中该干蚀刻工艺包括调整一偏压功率以定义出该凹陷区的一各向同性轮廓。
4.如权利要求1所述的半导体装置的制造方法，其中该第一和第三干蚀刻工艺各利用一碳氟等离子体气体；以及其中该第二干蚀刻工艺利用一碳氢-氟等离子体气体。
5.一种半导体装置的制造方法，包括：
形成一栅极堆叠于一硅基底之上；
形成虚置间隙子于该栅极堆叠的侧壁上；
各向同性地蚀刻该硅基底以形成凹陷区于该栅极堆叠的一侧；
形成一半导体材料于所述凹陷区之内，其中该半导体材料相异于该硅基底；
移除所述虚置间隙子；
形成多个栅极间隙子层，其具有氧化物-氮化物-氧化物配置于该栅极堆叠与该半导体材料上；以及
蚀刻所述间隙子层以形成栅极间隙子于该栅极堆叠的侧壁上。
6.如权利要求5所述的半导体装置的制造方法，其中各向同性地蚀刻该硅基底的步骤包括实施一干蚀刻工艺使用一氢-硼等离子体气体和调整该干蚀刻工艺的一偏压功率以定义出所述凹陷区的一各向同性轮廓。
7.如权利要求5所述的半导体装置的制造方法，其中形成多个栅极间隙子层的步骤包括：
形成一第一氧化层于该栅极堆叠和该半导体材料之上，其中该第一氧化层包含一厚度范围大抵介于30埃至200埃；
形成一氮化层于该第一氧化层之上，其中该氮化层包含一厚度范围大抵介于30埃至200埃；及
形成一第二氧化层于该氮化层之上，其中该第二氧化层包含一厚度范围大抵介于100埃至1000埃。
8.如权利要求7所述的半导体装置的制造方法，其中蚀刻所述间隙子层的步骤包括：
蚀刻该第二氧化层，以一第一干蚀刻工艺使用一碳氟等离子体气体；
蚀刻该氮化层，以一第二干蚀刻工艺使用一碳氢-氟等离子体气体；以及
蚀刻该第一氧化层，以一第三干蚀刻工艺使用一碳氟等离子体气体。
9.一半导体装置，包括：
一硅基底具有一硅区域、多个应变半导体材料区域、及一浅沟槽隔离物区域，其中所述多个应变半导体材料区域之一夹置于该硅区域和该浅沟槽隔离物区域之间，以及其中所述多个应变半导体材料区域包括一各向同性轮廓；以及
一晶体管，包括：
一栅极堆叠于该硅区域上；
多个间隙子形成于该栅极堆叠的侧壁上，其中各间隙子包括一氮化层夹置于一第一氧化层和一第二氧化层之间；以及
轻掺杂源极/漏极区各形成于该硅区域的一部分位于该间隙子下方以及形成于应变半导体材料区域的一部分。
10.如权利要求9所述的半导体装置，其中该应变半导体材料区域包括硅锗或碳化硅。
11.如权利要求9所述的半导体装置，其中所述多个应变半导体材料区域之一被该浅沟槽隔离物区域截断使得所述多个应变半导体材料区域之一具有一斜的表面。
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CN102569408A (zh) * 2012-02-28 2012-07-11 上海华力微电子有限公司 一种高擦写速度的sonos单元晶体管及其制造方法
CN109786380A (zh) * 2017-11-10 2019-05-21 联华电子股份有限公司 半导体存储装置的外延接触结构的制作方法
CN109786380B (zh) * 2017-11-10 2020-11-10 联华电子股份有限公司 半导体存储装置的外延接触结构的制作方法
CN112542446A (zh) * 2019-09-23 2021-03-23 南亚科技股份有限公司 具有气隙的半导体元件结构及其制备方法
CN112542446B (zh) * 2019-09-23 2024-03-08 南亚科技股份有限公司 具有气隙的半导体元件结构及其制备方法

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