CN101719485A - 芯片结构、衬底结构、芯片封装结构及其工艺 - Google Patents

芯片结构、衬底结构、芯片封装结构及其工艺 Download PDF

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CN101719485A
CN101719485A CN200910126850A CN200910126850A CN101719485A CN 101719485 A CN101719485 A CN 101719485A CN 200910126850 A CN200910126850 A CN 200910126850A CN 200910126850 A CN200910126850 A CN 200910126850A CN 101719485 A CN101719485 A CN 101719485A
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chip
substrate
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沈启智
陈仁川
张惠珊
潘彦良
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种芯片封装结构及工艺，其结构包括一衬底、一芯片、一焊锡层以及至少一结线凸块。衬底具有至少一接垫，而芯片具有一主动面，该主动面配置有至少一焊垫。此外，结线凸块配置于芯片的焊垫上或衬底的接垫上，并与该焊锡层相接合而固定芯片于衬底上。结线凸块的材质为金银合金，其中银含量为15％以下。

Description

芯片结构、衬底结构、芯片封装结构及其工艺
技术领域
本发明是有关于一种半导体封装结构，且特别是有关于一种芯片结构、衬底结构、芯片封装结构及其工艺。
背景技术
在现今高度整合的时代，半导体工业是技术成熟度高的产业，也因应市场的需求，朝向多元化的市场发展各式各样的芯片封装结构，例如光电相关产品、发光元件或感光元件(影像传感器)等，均可以半导体工艺来制作，以有效地降低成本。
图1是已知一种芯片封装结构的剖面示意图。请参考图1，在芯片100的主动面102上制作多个凸块110以及凸块底金属层108(Under BumpMetallurgy，UBM)。将制作完成的芯片100翻覆之后，以芯片100的主动面102上的凸块110与衬底120的接垫122电性连接，以构成一芯片封装结构130。其中，凸块110例如是印刷的焊料凸块、电镀的导电凸块。此外，凸块110亦可以是利用打线结球工艺所形成的金凸块。
已知的金凸块为含量99％的金与含量1％的钯所组成的结线凸块(studbump)。当结线凸块110与衬底120的接垫122由焊锡相连接时，除了金锡共晶结合之外，更会在接合处产生介金属化合物(IMC)及空孔(void)等缺陷。此缺陷容易造成裂缝，进而影响结线凸块110与接垫122接合的强度及使用寿命。此外，在长时间操作之后，结线凸块110中的金元素扩散到焊锡中，将会造成结线凸块110的金流失或造成结线凸块110的成份改变。有鉴于此，已知的结线凸块的可靠度仍有进一步改善的必要性。
发明内容
本发明提供一种芯片结构、衬底结构、芯片封装结构及其工艺，用以改善已知的缺陷，以提高结线凸块的可靠度。
本发明提出一种芯片结构，其包括一芯片以及至少一结线凸块。芯片具有一主动面，该主动面配置有至少一焊垫。结线凸块配置于芯片的焊垫上，该结线凸块的材质为金银合金，其中银含量为15％以下。
本发明提出一种衬底结构，其包括一衬底以及至少一结线凸块。衬底具有至少一接垫。结线凸块配置于衬底的接垫上，该结线凸块的材质为金银合金，其中银含量为15％以下。
本发明提出一种芯片封装结构，其包括一衬底、一芯片以及至少一结线凸块。衬底具有至少一接垫，而芯片具有一主动面，该主动面配置有至少一焊垫。结线凸块配置于衬底的接垫上或芯片的焊垫上，结线凸块的材质为金银合金，其中银含量为15％以下。
在本发明的一实施例中，衬底为印刷电路板，而芯片为倒装芯片。
在本发明的一实施例中，芯片封装结构还包括一焊锡层，其配置于衬底的接垫上。在另一实施例中，焊锡层配置于芯片的焊垫上。
本发明提出一种芯片封装工艺。首先，提供一衬底以及一芯片，衬底具有至少一接垫，而芯片具有至少一焊垫。接着，形成至少一结线凸块于芯片的焊垫上，使衬底与芯片由结线凸块与相接合，结线凸块的材质为金银合金，其中银含量为15％以下。
本发明提出另一种芯片封装工艺。首先，提供一衬底以及一芯片，衬底具有至少一接垫，而芯片具有至少一焊垫。接着，形成至少一结线凸块于衬底的接垫上，使衬底与芯片藉由结线凸块与相接合。结线凸块的材质为金银合金，其中银含量为5％-15％。
在本发明的一实施例中，上述形成结线凸块的方法包括进行打线结球工艺。
本发明因采用银含量为5％～15％的金银合金作为结线凸块，因此在焊接时，由于焊锡层含有扩散银的成分存在，故能抑制介金属化合物的成长，并能减缓金流失的速度。
附图说明
为让本发明的上述特征和优点能更明显易懂，下文特举较佳实施例，并配合附图，作详细说明如下，其中：
图1是已知一种芯片封装结构的剖面示意图。
图2A-图2C是本发明第一实施例的芯片封装结构及其工艺的示意图。
图3A-图3C是本发明第二实施例的芯片封装结构及其工艺的示意图。
图4是本发明另一实施例的芯片结构的示意图。
图5是本发明另一实施例的衬底结构的示意图。
具体实施方式
图2A-图2C是本发明第一实施例的芯片封装结构及其工艺的示意图。请先参考图2A的芯片结构200，其包括一芯片210以及多个结线凸块220。芯片210的主动面212上具有多个焊垫214，其材质例如是铝，用以作为电子信号输入/输出的接口。芯片210可以是球格阵列封装(BGA)用的芯片，例如是感光元件、发光元件或处理器等半导体元件。结线凸块220是由打线机所用的金线结成凸块状的金球，而金球被压制于焊垫214上之后再切断金线即可。利用打线结球工艺所形成的金凸块能加快工艺的时程、提高产能，因此能有效降低工艺的成本。
接着进行倒装接合工艺，请参考图2B，将芯片210翻转并以撷取器(图未示)吸附芯片210的背面之后，芯片210由结线凸块220与衬底230电性接合，以形成图2C所示的芯片封装结构250。衬底230例如是印刷电路板，其具有多个接垫232，而接垫232的材质例如是铜。在进行倒装接合工艺之前，可先在衬底230的接垫232上以印刷的方式形成一焊锡层240，其材质可以是锡膏、无铅焊接剂等，用以接合芯片210上的结线凸块220，以使芯片210能固定于衬底230上。在本实施例中，固定芯片210于衬底230上的方法例如是热压接合，以使金凸块与焊锡产生金锡共晶接合，进而提高接合的强度。此外，请参考图4，在另一实施例中，焊锡层除了形成在衬底230的接垫232上以外，也可形成在每一个结线凸块220上，例如以结线凸块220沾附焊锡的方式而形成所需的焊锡层240a，如此，不需制作网版，以节省成本。另外，固定芯片于衬底上的方法也可利用超声波震动接合，此方法不需先形成焊锡层240于衬底230的接垫232上或形成焊锡层240a于结线凸块220上，而简化工艺。
值得注意的是，为了避免结线凸块220的金元素扩散到焊锡层240中或与焊锡层240焊接时产生介金属化合物，本发明的结线凸块220的材质采用金银合金，其中银含量为15％以下。更详尽地说，银会扩散至焊锡层240中，使其纯锡成分改变，并形成一混合层，该混合层的成分包含0.5-3.5％银、金及锡的合金。在焊接时，由于焊锡层240含有扩散银的成分存在，故能抑制介金属化合物的成长，并能减缓金流失的速度。
在本实施例中，芯片封装结构250的结线凸块220使用强度较高的金线(含15％以下的银)，相对于已知的金线(含99％的金)，具有较佳的打线结合强度、截线(bond-off)性能以及均一性高的凸块高度，因此能减少工艺上的重工率，以提高产能及良率。此外，银的成本较低，并能有效抑制介金属化合物的成长，相对提高结线凸块的可靠度。
图3A-图3C是本发明第二实施例的芯片封装结构及其工艺的示意图。请先参考图3A的衬底结构300，其包括一衬底310以及多个结线凸块320。衬底310例如是印刷电路板，其具有多个接垫312，而接垫312的材质例如是铜。结线凸块320是由打线机所用的金线结成凸块状的金球，而金球被压制于接垫上之后再切断金线即可成型。在衬底310上形成结线凸块320可避免打线机对芯片施力过大而损坏芯片内部的集成电路，以降低风险。此外，在衬底310上制作结线凸块320的成本低且良率高，能有效地降低重工率，进而提高产能。
接着进行倒装接合工艺，请参考图3B，将芯片330翻转并以撷取器吸附芯片的背面之后，芯片330由焊锡层340与衬底310上的结线凸块320进行电性接合，以形成图3C所示的芯片封装结构350。焊锡层340例如以印刷的方式形成于芯片330的焊垫332上，其材质可以是锡膏、无铅焊接剂等，用以接合衬底310上的结线凸块320，以使芯片330能固定于衬底310上。在本实施例中，固定芯片330于衬底310上的方法例如是热压接合，以使金凸块与焊锡产生金锡共晶接合，进而提高接合的强度。此外，请参考图5，在另一实施例中，焊锡层除了形成在芯片330的焊垫332上以外，也可形成在每一个结线凸块320上，例如以结线凸块320沾附焊锡的方式而形成所需的焊锡层340a，如此，不需制作网版，以节省成本。另外，固定芯片于衬底上的方法也可利用超声波震动接合，此方法不需先形成焊锡层340于芯片330的焊垫332上或形成焊锡层340a于结线凸块320上，而简化工艺。
值得注意的是，本发明的结线凸块的材质为金银合金，其中银含量为15％以下，而银会扩散至焊锡层中，使其纯锡成分改变，因而形成含0.5-3.5％银的合金。在焊接时，由于焊锡层含有扩散银的成分存在，故能抑制介金属化合物的成长，并能减缓金流失的速度。
综上所述，本发明提出的芯片结构、衬底结构、芯片封装结构及其工艺，均采用银含量为15％以下的金银合金作为结线凸块，能减缓结线凸块的金元素扩散到焊锡层中或与焊锡层焊接时产生介金属化合物。相对于已知的金线(含99％的金)，本发明的结线凸块具有较佳的打线结合强度、截线(bond-off)性能以及均一性高的凸块高度，因此能减少工艺上的重工率，以提高产能及良率。
虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视权利要求所界定的为准。

Claims (15)

1.一种芯片结构，包括：
一芯片，具有一主动面，该主动面配置有至少一焊垫；以及
至少一结线凸块，配置于该芯片的该焊垫上，该结线凸块的材质为金银合金，其中银含量为15％以下。
2.如权利要求1所述的芯片结构，还包括一焊锡层，配置于该结线凸块上。
3.一种衬底结构，包括：
一衬底，具有至少一接垫；以及
至少一结线凸块，配置于该衬底的该接垫上，该结线凸块的材质为金银合金，其中银含量为15％以下。
4.如权利要求3所述的衬底结构，还包括一焊锡层，配置于该结线凸块上。
5.一种芯片封装结构，包括：
一衬底，具有至少一接垫；
一芯片，具有一主动面，该主动面配置有至少一焊垫；以及
至少一结线凸块，配置于该衬底的该接垫上或该芯片的该焊垫上，该结线凸块的材质为金银合金，其中银含量为15％以下。
6.如权利要求5所述的芯片封装结构，其中该结线凸块配置于该衬底的该接垫上，且该芯片封装结构还包括一焊锡层，配置于该结线凸块与该芯片的该焊垫之间。
7.如权利要求5所述的芯片封装结构，其中该结线凸块配置于该芯片的该焊垫上，且该芯片封装结构还包括一焊锡层，配置于该结线凸块与该衬底的该接垫之间。
8.一种芯片封装工艺，包括：
提供一衬底以及一芯片，该衬底具有至少一接垫，而该芯片具有至少一焊垫；
形成至少一结线凸块于该芯片的该焊垫上；
使该衬底与该芯片藉由该结线凸块相接合而固定，该结线凸块的材质为金银合金，其中银含量为15％以下。
9.如权利要求8所述的芯片封装工艺，其中形成该结线凸块的方法包括进行打线结球工艺。
10.如权利要求8所述的芯片封装工艺，还包括形成一焊锡层于该衬底的该接垫上，以在接合该衬底与该芯片时，使该结线凸块与该焊锡层相接合。
11.如权利要求8所述的芯片封装工艺，还包括沾附一焊锡层于该结线凸块上，以在接合该衬底与该芯片时，使该焊锡层与该衬底的该接垫相接合。
12.一种芯片封装工艺，包括：
提供一衬底以及一芯片，该衬底具有至少一接垫，而该芯片具有至少一焊垫；
形成至少一结线凸块于该衬底的该接垫上；
使该衬底与该芯片由该结线凸块相接合而固定，该结线凸块的材质为金银合金，其中银含量为15％以下。
13.如权利要求12所述的芯片封装工艺，其中形成该结线凸块的方法包括进行打线结球工艺。
14.如权利要求12所述的芯片封装工艺，还包括形成一焊锡层于该芯片的该焊垫上，以在接合该衬底与该芯片时，使该结线凸块与该焊锡层相接合。
15.如权利要求12所述的芯片封装工艺，还包括沾附一焊锡层于该结线凸块上，以在接合该衬底与该芯片时，使该焊锡层与该芯片的该焊垫相接合。
CN200910126850A 2007-11-19 2009-03-20 芯片结构、衬底结构、芯片封装结构及其工艺 Pending CN101719485A (zh)

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