CN101714538B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN101714538B
CN101714538B CN2009101791235A CN200910179123A CN101714538B CN 101714538 B CN101714538 B CN 101714538B CN 2009101791235 A CN2009101791235 A CN 2009101791235A CN 200910179123 A CN200910179123 A CN 200910179123A CN 101714538 B CN101714538 B CN 101714538B
Authority
CN
China
Prior art keywords
electrode
semiconductor substrate
semiconductor device
manufacture method
surface electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2009101791235A
Other languages
English (en)
Other versions
CN101714538A (zh
Inventor
及川贵弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
System Solutions Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Sanyo Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2008258242A external-priority patent/JP2010092894A/ja
Priority claimed from JP2008258243A external-priority patent/JP2010092895A/ja
Application filed by Sanyo Electric Co Ltd, Sanyo Semiconductor Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN101714538A publication Critical patent/CN101714538A/zh
Application granted granted Critical
Publication of CN101714538B publication Critical patent/CN101714538B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605—Shape
    • H01L2224/06051—Bonding areas having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供一种半导体器件及其制造方法，其目的为抑制半导体器件在使用时因为热所导致的翘曲，以提升半导体器件的可靠性。本发明的半导体器件是在构成纵型MOS晶体管的半导体衬底(10)的表面上，形成有与源极区域连接的源极电极连接部(18)。在源极电极连接部(18)形成有通过镀覆法所形成的表面电极(23)。在表面电极(23)连接有凸块电极(31)，而表面电极(23)由露出凸块电极(31)的保护膜(26)所覆盖。另一方面，在半导体衬底(10)的背面上，形成有与漏极区域连接的背面电极(30)。表面电极(23)与背面电极(30)由具有相同线膨胀系数的金属所构成，较佳为铜所构成。此外，表面电极(23)与背面电极(30)较佳为具有相同厚度，或大略相同厚度。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件及其制造方法，尤有关于一种在半导体衬底的两面具有电极的半导体器件及其制造方法。
背景技术
功率晶体管(power transistor)广泛使用作为电力供给用的开关组件。以功率晶体管的一种而言，已知有在与半导体衬底的表面垂直方向流通源极-漏极电流的纵型MOS(Metal Oxide Semiconductor，金属氧化物半导体)晶体管。
参照图式说明纵型MOS晶体管。图13(A)为从表面侧观看纵型MOS晶体管时的平面图，图13(B)为沿着图13(A)的Y-Y线的剖面图。
在半导体衬底100的表面上，形成有与在该表面所形成的未图示的源极区域及栅极连接，且作为表面电极的源极电极101及栅极电极104。在此源极电极101及栅极电极104上，形成有用以媒介源极电极101及栅极电极104与未图示的电路衬底(例如印刷衬底)电性连接的凸块电极(bump)102、105。再者，所述源极电极101及栅极电极104以露出凸块电极102、105的方式由保护膜103所覆盖。
另一方面，在半导体衬底100的背面上，形成有与半导体衬底100的漏极区域连接，且作为背面电极的漏极电极106。
关于此种纵型MOS晶体管记载于专利文献1。
[专利文献1]日本特开2008-66694号公报
发明内容
(发明所欲解决的问题)
然而，形成有所述纵型MOS晶体管的半导体衬底100，会有在使用状态中产生翘曲之虞。此是由于表面电极与背面电极的线膨胀系数不同时，在半导体衬底100与表面电极的界面所产生的应力、及半导体衬底100与背面电极的界面所产生的应力不同所致。由于此半导体衬底100的翘曲，会有保护膜103或凸块电极102、105剥离，甚至表面电极或背面电极剥离之虞。此种半导体衬底100的翘曲，会由于周围环境的温度变化而产生变化，因此保护膜103等会因为温度反复变化而易于产生剥离。
此外，市场上也有提升所述纵型MOS晶体管的电流驱动能力的要求。为了提升电流驱动能力，依据本发明人的检讨，将表面电极的垂直方向的膜厚增大的作法很有效。如图13(A)所示，此是由于凸块电极102、105形成于广布于半导体衬底100表面的表面电极的一部份上，且相对于半导体衬底100朝水平方向流通于表面电极的电流成分较多之故。此外，将所述背面电极侧的垂直方向的膜厚增大也同样有效。
由此种理由，要将表面电极及背面电极的垂直方向的膜厚增大时，以表面电极及背面电极的制法而言，以使用镀覆法来形成为较适当。
具体而言，首先，在半导体衬底100的表面上，形成在表面电极的形成区域具有开口部的光刻胶(resist)层，且通过使用该光刻胶层作为镀覆形成用掩膜的镀覆法，在开口部内形成表面电极。此外，在半导体衬底100的背面侧，于其整面形成背面电极。
然而，在纵型MOS晶体管的制程中，将半导体衬底100薄化时，由于与背面电极106的形成步骤或热处理步骤的关系，会有产生半导体衬底100的翘曲，并因此产生光刻胶层的剥离等的不良情形。若产生此种光刻胶层的形成不良，当然就会招致表面电极的形成不良。
因此，本发明的目的为通过镀覆法将表面电极形成为较厚，而提升晶体管的电流驱动能力，并且防止因为半导体衬底100的翘曲所导致光刻胶层的形成不良。
(解决问题的手段)
本发明的主要特征如下。本发明的半导体器件的特征为包括：半导体衬底；第1电极，形成于所述半导体衬底的表面上；第2电极，形成于所述半导体衬底的背面上；及保护膜，以覆盖所述第1电极的侧面的方式形成，且于表面上具有开口部；在所述保护膜的表面上形成所述开口部时，同时将所述半导体衬底的表面上的沿着切割线的区域的所述保护膜去除；第1电极及第2电极由具有相同线膨胀系数的金属所构成。
此外，本发明的半导体器件，在所述构成中，第1电极包含铜或银。
此外，本发明的半导体器件，在所述构成中，半导体衬底具备具有漏极、栅极、源极的纵型晶体管，第1电极与漏极、栅极、源极任一者电性连接。
此外，本发明的半导体器件，在所述构成中，半导体衬底具备具有漏极、栅极、源极的纵型晶体管，第1电极与栅极及源极电性连接，第2电极与漏极电性连接。
本发明的半导体器件的制造方法有鉴于所述问题而研创者，其特征为包括：通过使用具有形成在半导体衬底表面上的开口部的光刻胶层作为掩膜的镀覆法，将第1电极形成于开口部内的步骤；将形成有第1电极的半导体衬底的背面薄化的步骤；及在经薄化的半导体衬底的背面上形成第2电极的步骤。
此外，本发明的半导体器件的制造方法，在所述步骤中，半导体衬底具备具有漏极、栅极、源极的纵型晶体管，第1电极与漏极、栅极、源极任一者电性连接。
此外，本发明的半导体器件的制造方法，在所述步骤中，半导体衬底具备具有漏极、栅极、源极的纵型晶体管，第1电极与栅极及源极电性连接，第2电极与漏极电性连接。
此外，所述光刻胶层在70℃以上的温度下烘烤。
再者，包括：在将所述半导体衬底薄化之前，在所述第1电极侧形成保护膜，且将该保护膜进行烘烤的步骤。
此外，所述保护膜由有机树脂所构成，在150℃以上的温度下烘烤。
再者，所述第1电极包含铜或银。此外，所述镀覆法为电解镀覆法。
此外，本发明的半导体器件，在所述构成中，第1电极及第2电极由具有相同线膨胀系数的金属所构成。
此外，本发明的半导体器件，在所述构成中，第1电极及第2电极的厚度均为5μm以上20μm以内。
此外，本发明的半导体器件，在所述构成中，第1电极的厚度及第2电极的厚度相同。
再者，所述半导体衬底具备具有漏极、栅极、源极的纵型晶体管，所述第1电极与所述所述栅极及所述源极电性连接，所述第2电极与所述漏极电性连接。
再者，所述半导体衬底具备具有漏极、栅极、源极的纵型晶体管，所述第1电极与所述漏极、所述栅极及所述源极中的任一者电性连接。
(发明效果)
依据本发明，在使用半导体器件时，由于可抑制因为热所导致的翘曲，因此可提升半导体器件的可靠性。
依据本发明，在将半导体衬底薄化之前，通过镀覆法将第1电极(表面电极)形成为较厚，而谋求晶体管的大电流化，并且抑制因为进行镀覆步骤时对镀覆形成用光刻胶层进行的烘烤处理所导致的热而在半导体衬底产生翘曲。藉此，即可抑制因为半导体衬底的翘曲所导致光刻胶层的剥离等的不良情形。
附图说明
图1(A)及(B)为显示本发明实施形态的半导体器件的剖面图。
图2(A)及(B)为显示本发明实施形态的半导体器件的平面图。
图3为显示本发明实施形态的半导体器件及其制造方法的剖面图。
图4为显示本发明实施形态的半导体器件及其制造方法的剖面图。
图5为显示本发明实施形态的半导体器件及其制造方法的剖面图。
图6为显示本发明实施形态的半导体器件及其制造方法的剖面图。
图7为显示本发明实施形态的半导体器件及其制造方法的剖面图。
图8为显示本发明实施形态的半导体器件及其制造方法的剖面图。
图9为显示本发明实施形态的半导体器件及其制造方法的剖面图。
图10为显示本发明实施形态的半导体器件及其制造方法的剖面图。
图11为显示本发明实施形态的半导体器件及其制造方法的剖面图。
图12为显示本发明实施形态的半导体器件的平面图。
图13(A)及(B)为显示习知例半导体器件的剖面图。
主要组件符号说明
10、100  半导体衬底           11       N-型半导体层
12       P型半导体层          13       沟
14      栅极绝缘膜            15       栅极电极
16      层间绝缘膜            17       源极区域
18      源极电极连接部        19       覆层膜
20      障壁层                21、29   种晶层
22      光刻胶层              22A、26A  开口部
23、32、34  表面电极          24       镍镀覆层
25      金镀覆层              26、103  保护膜
27      钛层                  28       镍层
30      背面电极
31、33、35、102、105  凸块电极
101  源极电极              104  栅极电极
106  漏极电极              DL   切割线
具体实施方式
以下参照图式说明本发明实施形态的半导体器件。
本实施形态的半导体器件以在与半导体衬底的表面垂直的方向流通源极-漏极电流的纵型MOS晶体管的形态来说明。图1(A)为显示本实施形态的纵型MOS晶体管的构成剖面图，且图示沿着半导体衬底10的切割线(dicing line)DL所分割的2个纵型MOS晶体管。图1(B)为显示图1(A)中从源极电极连接部18至N-型半导体层的详细结构的部分放大图。
图1(A)与图2(A)及图2(B)所示纵型MOS晶体管的平面图中沿着X-X线的剖面对应。图2(A)显示从表面侧观看纵型MOS晶体管时的表面电极23、32等的配置，图2(B)显示从该背面侧观看时的背面电极30的配置。
如图所示，在N+型半导体衬底10的表面上，通过外延生长(epitaxial growth)形成有N-型半导体层11。在此N-型半导体层11的表面，形成有与形成在该表面的源极区域17连接的源极电极连接部18。源极电极连接部18例如由铝所构成，例如约以2μm至3μm形成。
此外，在N-型半导体层11的表面，形成有覆盖源极电极连接部18的端部，且具有露出该一部份的开口部的硅氮化膜等的覆层(passivation)膜19。通过此开口部所露出的源极电极连接部18的表面，通过由钛等所构成的障壁(barrier)层20所覆盖。再者，在障壁层20上叠层有由铜所构成的种晶(seed)层21。
再者，在此种晶层21上，通过镀覆法形成有由铜或银所构成的表面电极23。另外，所述表面电极23的厚度，例如为约5μm以上，较佳为10μm至20μm。此外，表面电极23的上面，由多层镀覆层，例如镍镀覆层24及金镀覆层25所覆盖。源极电极连接部18、表面电极23、镍镀覆层24及金镀覆层25，发挥作为源极电极功能。此外，与源极电极相同地，如图1(B)及图2(A)所示，具有与栅极电极15连接的未图示的栅极电极连接部，且在栅极电极连接部上隔着障壁层20、种晶层21形成有表面电极32。再者，所述表面电极32上面，例如由镍镀覆层24及金镀覆层25所覆盖。
再者，表面电极23、32的侧面、镍镀覆层24的侧面、及金镀覆层25是通过由有机树脂所构成的保护膜26所覆盖。在保护膜26中，设有露出金镀覆层25表面的开口部，而在通过该开口部所露出的金镀覆层25上，形成有媒介表面电极23、32与未图示的电路衬底(例如印刷衬底)电性连接的凸块电极31、33。
另一方面，在半导体衬底10的背面上，如图1(A)及图2(B)所示，形成有构成漏极区域的与半导体衬底10连接且通过镀覆法由铜或银所构成的背面电极30。即，此时，背面电极30发挥作为漏极电极功能。背面电极30延伸于纵型MOS晶体管的整体背面。
另外，所述背面电极30的厚度例如为约5μm以上，较佳为10μμm至20μm。在此，所述表面电极23、32与背面电极30，由具有相同线膨胀系数的金属所构成，各厚度也以彼此相同或大略相同为较佳。
藉此构成，在纵型MOS晶体管的使用状态中，由于表面电极23、32与背面电极30由相同材料所构成，故热膨胀量相等，或大略相等，因此半导体衬底10与表面电极23、32的界面所产生的应力、与半导体衬底10与背面电极30的界面所产生的应力相等，或大略相等。因此，像习知技术那样因为所述应力的差异而于半导体衬底10产生翘曲的情形可受到抑制。即，即使周围环境的温度变化反复时，也可抑制保护膜26或凸块电极31、33的剥离，或者表面电极23、32或背面电极30的剥离。结果，可提升半导体器件的可靠性。
再者，只要表面电极23、32与背面电极30各者厚度彼此相同或大略相同，即可更确实地使表面电极23、32与背面电极30的热膨胀量相等，因此可更确实地获得所述效果。
以下参照图1(B)说明纵型MOS晶体管的本体部分的详细构成。在N-型半导体层11的表面，形成有P型半导体层12。从P型半导体层12的表面至N-型半导体层11的一部份，形成有多条沟13，而在各沟13内，隔着硅氧化膜等栅极绝缘膜14而形成有多晶硅等栅极电极15。在P型半导体层12的表面且为沟13的两侧，形成有由N+层所构成的源极区域17。沟13的栅极电极15的上面，由在源极区域上具有开口部的层间绝缘膜16所覆盖。覆盖此层间绝缘膜，而形成有源极电极连接部18。源极电极连接部18经由层间绝缘膜16的开口部而与源极区域17连接。在此纵型MOS晶体管中，于沟13的侧壁的P型半导体层12的部分形成沟道区域，而N-型半导体层11及半导体衬底10则成为漏极区域。
在所述构成中，若对栅极电极15施加临限值以上的电压，则纵型MOS晶体管会导通。再者，源极-漏极电流依据施加于表面电极23与背面电极30的电压(源极-漏极间电压)而流通。
以下参照图3至图11说明所述纵型MOS晶体管制造方法。图3至图11中，图示中间夹着切割线DL而邻接的2个纵型MOS晶体管的形成区域。
首先，如图3所示，准备由N+型单晶硅所构成的半导体衬底10，在其表面，通过外延生长，形成N-型半导体层11。在此时点，半导体衬底10及N-型半导体层11的整体厚度例如为约500μm至约700μm。
在N-型半导体层11的表面，如图1(B)所示，形成有P型半导体层12，再者，形成有多条沟13、栅极绝缘膜14、栅极电极15、层间绝缘膜16、源极区域17。另外，在图3至图11的说明中，为了便于说明，省略P型半导体层12、多条沟13、栅极绝缘膜14、栅极电极15、层间绝缘膜16、源极区域17的图示。
之后，在N-型半导体层11的表面所形成的P型半导体层12上，形成例如由铝所构成的源极电极连接部18。同时，也形成栅极电极连接部。此等源极电极连接部18及栅极电极连接部，可通过溅镀法与光微影法(photolithographic method)来形成。之后，在N-型半导体层11上通过LPCVD(Low Pressure ChemicalVapor Deposition，低压化学气相沉积)法等形成由氮化硅膜等所构成的覆层膜19，且通过光微影法，使源极电极连接部18及栅极电极连接部的表面的一部份露出。
接着，如图4所示，覆盖源极电极连接部18、栅极电极连接部及覆层膜19而形成由钛等所构成的障壁层20。障壁层20发挥作为障壁铜自表面电极23、32扩散功能。在障壁层20上，为了后述的镀覆法，形成由铜所构成的种晶层21。
之后，如图5所示，在种晶层21上形成镀覆形成用的光刻胶层22。光刻胶层22以露出与图2(A)所示的表面电极23、32的形成区域对应的种晶层21区域的方式而具有开口部22A。此光刻胶层22使用作为后述的表面电极23、32的形成步骤，即镀覆步骤的镀覆形成用掩膜。
在光刻胶层22的形成步骤中，最初将光刻胶层22材料形成于种晶层21整面，通过例如光微影步骤，以形成开口部22A的方式进行图案化。之后，为了将光刻胶层22固化，在约70℃以上，较佳为约90℃至约130℃的温度下，对光刻胶层22进行热处理，即烘烤处理。
之后，如图6所示，通过将此光刻胶层22作为镀覆形成用掩膜的镀覆法，在开口部22A内的种晶层21上，形成由铜所构成的镀覆层，即表面电极23、32。由于此表面电极23、32通过镀覆法形成，因此可比溅镀法等其他方法更快形成。以形成表面电极23、32的镀覆法而言，虽也可使用电解镀覆步骤、无电解镀覆步骤的任一者，惟为了确实确保表面电极23、32的厚度，以使用电解镀覆步骤为较佳。表面电极23、32的厚度，约5μm以上，较佳为约10μm至约20μm。另外，表面电极23、32也可为由银所构成的镀覆层。
再者，在表面电极23、32上，可视需要形成多层镀覆层，例如镍镀覆层24及金镀覆层25。
如此，由于可将表面电极23、32相对于半导体衬底10在垂直方向形成为较厚，因此在表面电极23、32中，可增加相对于半导体衬底10在水平方向流通的电流成分。即，可提升纵型MOS晶体管的电流驱动能力。
之后，如图7所示，去除光刻胶层22。再者，通过蚀刻等，将障壁层20及种晶层21的不需要的区域，例如未与表面电极23、32重叠的区域去除。
接着，如图8所示，形成覆盖表面电极23、32的侧面、镍镀覆层24的侧面、及金镀覆层25，而由聚醯亚胺(polyimide)等有机树脂所构成的保护膜26。在保护膜26设有供露出金镀覆层25的一部份的开口部26A。对于此保护膜26形成开口部26A，可通过蚀刻法将开口部形成区域的保护膜予以去除，使用由例如感光性有机树脂所构成的保护膜时，只要通过显影处理形成开口部26A即可。
在此，为了固化所述保护膜26，在约150℃以上，较佳为约200以上的温度下，对保护膜26进行热处理，即烘烤处理。
另外，以在形成所述开口部26A的同时将沿着切割线D L的保护膜26的区域去除为较佳。此乃为了尽量避免在最后切割步骤中因为与切割刀(dicing blade)接触所导致保护膜26的剥离及损伤。
进一步而言，在本实施形态中，虽以与所述障壁层20、种晶层21、表面电极23、32、镍镀覆层24及金镀覆层25邻接的方式形成保护膜26，惟也可为隔着所期望的间隔形成，而不与各层邻接。
接着，如图9所示，对半导体衬底10的背面进行背研磨(back grind)，将半导体衬底10薄化。背研磨后的半导体衬底10的厚度例如约100μm至约200μm，较佳为约150μm。另外，将半导体衬底10薄化的步骤，不限定于所述研磨法，也可使用蚀刻法。
接着，如图10所示，在半导体衬底10的背面上整面，视需要形成钛层27、镍层28。另外，也可仅形成钛层27。再者，在此钛层27、镍层28上，或是钛层27上，形成由铜所构成的种晶层29。之后，在种晶层29上，通过镀覆法，形成由铜或银所构成的背面电极30。以此镀覆法而言，较佳为使用电解镀覆法，惟也可使用无电解镀覆法。
另外，背面电极30未必要通过镀覆法来形成，也可通过其他方法，例如溅镀或真空蒸镀等的PVD(PhysicalVapor Deopsition，物理气相沉积)法来形成。此时，不需形成种晶层29。
接着，如图11所示，在保护膜26的开口部26A内的金镀覆层25上，形成媒介表面电极23、32与未图示的电路衬底(例如印刷衬底)电性连接的凸块电极31、33。所述凸块电极31、33例如通过焊锡的回焊(reflow)而形成。之后，通过沿着切割线DL的切割，将半导体衬底10及叠层于该半导体衬底10的各层，分离为多个纵型MOS晶体管。
依据所述步骤，通过镀覆法，可将表面电极23、32形成为较厚，因此在表面电极23、32中，可增加相对于半导体衬底10在水平方向流通的电流成分。即，可提升纵型MOS晶体管的电流驱动能力。
此外，通过在所述半导体衬底10薄化之前进行表面电极23、32的形成步骤，可抑制因为通过镀覆法形成表面电极23、32的镀覆形成用光刻胶层22的烘烤处理时的热而于半导体衬底10产生翘曲。即，在将半导体衬底10薄化，且于形成较厚的背面电极30之后，若通过镀覆法形成表面电极23、32，则会由于作为该镀覆形成用掩膜所使用的光刻胶层22的烘烤处理，而因半导体衬底10与背面电极30的线膨胀系数的差异，导致半导体衬底10与背面电极30的热膨胀量产生差异，而使半导体衬底10产生翘曲。
此外，关于保护膜26的形成步骤，也在将所述半导体衬底10薄化并形成背面电极30之前进行。藉此，通过保护膜26的烘烤处理，而抑制由于半导体衬底10与背面电极30的线膨胀系数的差异所导致在半导体衬底10产生翘曲。
再者，此等表面电极23、32及保护膜26的形成步骤，在将半导体衬底10薄化的步骤之前，即在半导体衬底10较厚而机械性强度较大的状态下进行，因此可更确实防止半导体衬底10的翘曲。
此外，如图12的平面图所示，以所谓上漏极(updrain)构造而言，也可在半导体衬底10的表面上，形成与构成纵型MOS晶体管的漏极区域的半导体衬底10电性连接的作为漏极电极的表面电极34。再者，在所述表面电极34中，形成媒介与未图示的电路衬底(例如印刷衬底)作电性连接的凸块电极35。至于其他构成，与图1至图11所示的构成相同。
如上所说明，依据本发明，当在半导体衬底10表面侧的大部分区域形成厚膜的表面电极23、32、34，且于整面背面形成厚膜的背面电极30时，将形成于两面的电极的厚度作成大略相同，藉此可抑制半导体衬底10产生翘曲。再者，在半导体衬底10的表面侧形成膜厚的表面电极23、32、34、保护膜26之后，由于将半导体衬底的背面侧薄化，故不需在半导体衬底10的表面侧粘附玻璃衬底等支撑(support)板，而简化制程。
另外，在本实施形态中，将表面电极23、32、34与背面电极30的厚度作成相同或大略相同，这是由于表面电极23、32或表面电极23、32、34的合计面积与背面电极30的面积大略相同，因此通过将两电极的厚度作成相同或大略相同，而使各面的厚度一致，以抑制半导体衬底10的翘曲产生。然而，从将所述热膨胀量作成一致的观点而言，只要设定成使各面的体积相同或大略相同即可。
进一步而言，只要热膨胀量一致，则各面的电极材质也可不需相同，而能作各种设定。
另外，本发明并不限定于所述实施形态，在不脱离其主旨的范围内当然均可作各种变更。例如，实施形态虽以N沟道型纵型MOS晶体管为例进行说明，惟也可变更为P沟道型纵型MOS晶体管。

Claims (17)

1.一种半导体器件，其特征在于，具备：
半导体衬底；
第1电极，形成于所述半导体衬底的表面上；
第2电极，形成于所述半导体衬底的背面上；及
保护膜，以覆盖所述第1电极的侧面的方式形成，且于表面上具有开口部；
在所述保护膜的表面上形成所述开口部时，同时将所述半导体衬底的表面上的沿着切割线的区域的所述保护膜去除；
所述第1电极及第2电极由具有相同线膨胀系数的金属所构成。
2.根据权利要求1所述的半导体器件，其特征在于，所述第1电极及所述第2电极的厚度均为5μm以上20μm以内。
3.根据权利要求1所述的半导体器件，其特征在于，所述第1电极的厚度及所述第2电极的厚度相同。
4.根据权利要求1所述的半导体器件，其特征在于，所述第1电极包含铜或银。
5.根据权利要求1至4中任一项所述的半导体器件，其特征在于，所述半导体衬底具备具有漏极、栅极、源极的纵型晶体管，所述第1电极与所述漏极、所述栅极、所述源极中的任一者电性连接。
6.根据权利要求1至4中任一项所述的半导体器件，其特征在于，所述半导体衬底具备具有漏极、栅极、源极的纵型晶体管，所述第1电极与所述栅极及所述源极电性连接，所述第2电极与所述漏极电性连接。
7.一种半导体器件的制造方法，其特征在于，具备：
通过使用具有形成在半导体衬底表面上的开口部的光刻胶层作为掩膜的镀覆法，将第1电极形成于所述开口部内的步骤；
将形成有所述第1电极的半导体衬底的背面薄化的步骤；及
在经薄化的所述半导体衬底的背面上形成第2电极的步骤。
8.根据权利要求7所述的半导体器件的制造方法，其特征在于，所述光刻胶层在70℃以上的温度下烘烤。
9.根据权利要求7所述的半导体器件的制造方法，其特征在于，包括：在将所述半导体衬底薄化之前，在所述第1电极侧形成保护膜，且将该保护膜进行烘烤的步骤。
10.根据权利要求9所述的半导体器件的制造方法，其特征在于，所述保护膜由有机树脂所构成，在150℃以上的温度下烘烤。
11.根据权利要求7所述的半导体器件的制造方法，其特征在于，所述第1电极包含铜或银。
12.根据权利要求7所述的半导体器件的制造方法，其特征在于，所述镀覆法为电解镀覆法。
13.根据权利要求7所述的半导体器件的制造方法，其特征在于，所述第1电极及所述第2电极通过具有相同线膨胀系数的金属而形成。
14.根据权利要求13所述的半导体器件的制造方法，其特征在于，所述第1电极的厚度及所述第2电极的厚度均为5μm以上20μm以内。
15.根据权利要求13所述的半导体器件的制造方法，其特征在于，所述第1电极的厚度及所述第2电极的厚度相同。
16.根据权利要求7至15中任一项所述的半导体器件的制造方法，其特征在于，所述半导体衬底具备具有漏极、栅极、源极的纵型晶体管，所述第1电极与所述栅极及所述源极电性连接，所述第2电极与所述漏极电性连接。
17.根据权利要求7至15中任一项所述的半导体器件的制造方法，其特征在于，所述半导体衬底具备具有漏极、栅极、源极的纵型晶体管，所述第1电极与所述漏极、所述栅极及所述源极中的任一者电性连接。
CN2009101791235A 2008-10-03 2009-09-29 半导体器件及其制造方法 Active CN101714538B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2008-258243 2008-10-03
JP2008258242A JP2010092894A (ja) 2008-10-03 2008-10-03 半導体装置の製造方法
JP2008-258242 2008-10-03
JP2008258243A JP2010092895A (ja) 2008-10-03 2008-10-03 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
CN101714538A CN101714538A (zh) 2010-05-26
CN101714538B true CN101714538B (zh) 2013-04-17

Family

ID=41529535

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009101791235A Active CN101714538B (zh) 2008-10-03 2009-09-29 半导体器件及其制造方法

Country Status (3)

Country Link
US (1) US8907407B2 (zh)
CN (1) CN101714538B (zh)
TW (1) TW201015718A (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8759209B2 (en) * 2010-03-25 2014-06-24 Stats Chippac, Ltd. Semiconductor device and method of forming a dual UBM structure for lead free bump connections
JP5545000B2 (ja) * 2010-04-14 2014-07-09 富士電機株式会社 半導体装置の製造方法
CN102655125A (zh) * 2012-01-16 2012-09-05 中国科学院上海微系统与信息技术研究所 一种双面溅射金属层减小硅圆片翘曲的结构
US9478512B2 (en) * 2015-02-11 2016-10-25 Dawning Leading Technology Inc. Semiconductor packaging structure having stacked seed layers
DE102015104570B4 (de) * 2015-03-26 2019-07-11 Infineon Technologies Ag Leistungs-chip und chipanordnung
JP6588363B2 (ja) * 2016-03-09 2019-10-09 トヨタ自動車株式会社 スイッチング素子
JP6460016B2 (ja) * 2016-03-09 2019-01-30 トヨタ自動車株式会社 スイッチング素子
WO2018025839A1 (ja) 2016-08-02 2018-02-08 パナソニックＩｐマネジメント株式会社 半導体装置、半導体モジュール、および半導体パッケージ装置
DE102016122162B4 (de) 2016-11-17 2022-05-05 Infineon Technologies Ag Halbleitervorrichtung mit metallisierungsstrukturen auf gegenüberliegenden seiten eines halbleiterbereichs, halbleiterschaltanordnung und verfahren
CN114975302A (zh) 2016-12-27 2022-08-30 新唐科技日本株式会社 半导体装置
JP2019169579A (ja) 2018-03-23 2019-10-03 株式会社東芝 半導体装置及びその製造方法
JP7226186B2 (ja) * 2019-08-23 2023-02-21 三菱電機株式会社 半導体装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6888196B2 (en) * 2002-04-24 2005-05-03 Nec Electronics Corporation Vertical MOSFET reduced in cell size and method of producing the same
US6979861B2 (en) * 2002-05-30 2005-12-27 Apd Semiconductor, Inc. Power device having reduced reverse bias leakage current

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59232467A (ja) 1983-06-16 1984-12-27 Toshiba Corp ガ−ドリング付きシヨツトキ−バリヤ−ダイオ−ド
JPS61180472A (ja) * 1985-02-05 1986-08-13 Mitsubishi Electric Corp 半導体装置
JPS6263472A (ja) 1985-09-13 1987-03-20 Sharp Corp パワ−ｍｏｓ−ｆｅｔ
US5347149A (en) 1989-11-29 1994-09-13 Texas Instruments Incorporated Integrated circuit and method
JP2689047B2 (ja) 1991-07-24 1997-12-10 三菱電機株式会社 絶縁ゲート型バイポーラトランジスタとその製造方法
US5536964A (en) 1994-09-30 1996-07-16 Green; Evan D. H. Combined thin film pinhole and semiconductor photodetectors
KR0165398B1 (ko) * 1995-05-26 1998-12-15 윤종용 버티칼 트랜지스터의 제조방법
JPH09162395A (ja) 1995-12-11 1997-06-20 Nippon Telegr & Teleph Corp <Ntt> 絶縁ゲート型トランジスタ
JP4167313B2 (ja) 1997-03-18 2008-10-15 株式会社東芝 高耐圧電力用半導体装置
JP3929557B2 (ja) * 1997-07-30 2007-06-13 三菱電機株式会社 半導体装置およびその製造方法
US6081006A (en) 1998-08-13 2000-06-27 Cisco Systems, Inc. Reduced size field effect transistor
US6297155B1 (en) * 1999-05-03 2001-10-02 Motorola Inc. Method for forming a copper layer over a semiconductor wafer
JP3540691B2 (ja) 1999-10-20 2004-07-07 三洋電機株式会社 半導体装置とその製造方法
JP3860705B2 (ja) 2000-03-31 2006-12-20 新電元工業株式会社 半導体装置
JP2002016266A (ja) 2000-06-28 2002-01-18 Sankosha Corp 半導体素子とその製造方法
JP4528460B2 (ja) * 2000-06-30 2010-08-18 株式会社東芝 半導体素子
KR100569587B1 (ko) * 2000-06-30 2006-04-10 주식회사 하이닉스반도체 고유전체 캐패시터의 제조 방법
JP2002353452A (ja) 2001-05-25 2002-12-06 Toshiba Corp 電力用半導体素子
JP4122880B2 (ja) * 2002-07-24 2008-07-23 住友電気工業株式会社 縦型接合型電界効果トランジスタ
US7217950B2 (en) 2002-10-11 2007-05-15 Nissan Motor Co., Ltd. Insulated gate tunnel-injection device having heterojunction and method for manufacturing the same
JP3573149B2 (ja) 2002-10-16 2004-10-06 日産自動車株式会社 炭化珪素半導体装置
JP4232584B2 (ja) * 2002-10-15 2009-03-04 株式会社デンソー 半導体装置
JP4360077B2 (ja) 2002-10-16 2009-11-11 富士電機デバイステクノロジー株式会社 半導体素子の製造方法
US7132321B2 (en) 2002-10-24 2006-11-07 The United States Of America As Represented By The Secretary Of The Navy Vertical conducting power semiconductor devices implemented by deep etch
US7250650B2 (en) 2002-11-21 2007-07-31 Infineon Technologies Ag Field-effect transistor structure and associated semiconductor memory cell
WO2004066391A1 (ja) 2003-01-20 2004-08-05 Mitsubishi Denki Kabushiki Kaisha 半導体装置
DE10308275A1 (de) * 2003-02-26 2004-09-16 Advanced Micro Devices, Inc., Sunnyvale Strahlungsresistentes Halbleiterbauteil
US7217954B2 (en) * 2003-03-18 2007-05-15 Matsushita Electric Industrial Co., Ltd. Silicon carbide semiconductor device and method for fabricating the same
JP3906184B2 (ja) * 2003-06-11 2007-04-18 株式会社東芝 半導体装置およびその製造方法
DE10333556B4 (de) 2003-07-23 2006-07-06 Infineon Technologies Ag Halbleiterbauelement mit verbesserter Kommutierung
JP4525048B2 (ja) 2003-10-22 2010-08-18 富士電機システムズ株式会社 半導体装置の製造方法
US6955932B2 (en) * 2003-10-29 2005-10-18 International Business Machines Corporation Single and double-gate pseudo-FET devices for semiconductor materials evaluation
JP2006049341A (ja) * 2004-07-30 2006-02-16 Renesas Technology Corp 半導体装置およびその製造方法
JP2007150176A (ja) 2005-11-30 2007-06-14 Sharp Corp 半導体装置及びその製造方法
JP4817827B2 (ja) 2005-12-09 2011-11-16 株式会社東芝 半導体装置
JP2008066694A (ja) 2006-03-16 2008-03-21 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP5303839B2 (ja) * 2007-01-29 2013-10-02 富士電機株式会社 絶縁ゲート炭化珪素半導体装置とその製造方法
JP2008235788A (ja) * 2007-03-23 2008-10-02 Sanyo Electric Co Ltd 絶縁ゲート型半導体装置
US8008688B2 (en) * 2008-04-01 2011-08-30 Jds Uniphase Corporation Photodiode and method of fabrication
JP5477286B2 (ja) * 2008-04-15 2014-04-23 住友電気工業株式会社 半導体装置およびその製造方法
US7932583B2 (en) * 2008-05-13 2011-04-26 Infineon Technologies Austria Ag Reduced free-charge carrier lifetime device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6888196B2 (en) * 2002-04-24 2005-05-03 Nec Electronics Corporation Vertical MOSFET reduced in cell size and method of producing the same
US6979861B2 (en) * 2002-05-30 2005-12-27 Apd Semiconductor, Inc. Power device having reduced reverse bias leakage current

Also Published As

Publication number Publication date
US20100013008A1 (en) 2010-01-21
TW201015718A (en) 2010-04-16
US8907407B2 (en) 2014-12-09
CN101714538A (zh) 2010-05-26

Similar Documents

Publication Publication Date Title
CN101714538B (zh) 半导体器件及其制造方法
TWI263280B (en) Semiconductor device and fabrication method thereof
TW561622B (en) Schottky barrier diode and method of making same
TWI324800B (en) Method for manufacturing semiconductor device
JP2010092895A (ja) 半導体装置及びその製造方法
TW200531228A (en) Semiconductor device and method for producing the same
JP2004273614A (ja) 半導体装置およびその製造方法
CN103681238B (zh) 半导体装置及半导体装置的制造方法
JP2007019412A (ja) 半導体装置およびその製造方法
JP2008192986A (ja) 半導体装置とその製造方法
FR2730859A1 (fr) Procede a masquage reduit pour la fabrication de composants mos a grille
TW200412214A (en) Semiconductor device and method of manufacturing the same
JP4058619B2 (ja) 半導体ウエハ
TW200541116A (en) Chemical compound semiconductor device and manufacturing process therefor
TWI227509B (en) Semiconductor device and the manufacturing method thereof
JPS61104662A (ja) 半導体表面のシヨツトキ・バリア接合とその製造方法
CN103700670B (zh) 阵列基板及其制作方法、显示装置
TWI356499B (en) Method for fabricating pixel structure
US20020064729A1 (en) Selective electroplating method employing annular edge ring cathode electrode contact
KR100754262B1 (ko) 반도체 장치 및 그 제조 방법
TW561623B (en) IC type Schottky barrier diode and process therefor
TW200306641A (en) Semiconductor device and manufacturing method for the same
TW200917485A (en) Method for manufacturing pixel structure
JPS58124261A (ja) 半導体装置
CN106887468A (zh) 薄膜晶体管、阵列基板及其制造方法和显示面板

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant