CN101697344A - 一种降低芯片电源焊盘键合引线上电流的方法 - Google Patents

一种降低芯片电源焊盘键合引线上电流的方法 Download PDF

Info

Publication number
CN101697344A
CN101697344A CN200910197804A CN200910197804A CN101697344A CN 101697344 A CN101697344 A CN 101697344A CN 200910197804 A CN200910197804 A CN 200910197804A CN 200910197804 A CN200910197804 A CN 200910197804A CN 101697344 A CN101697344 A CN 101697344A
Authority
CN
China
Prior art keywords
chip
pad
power supply
power
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN200910197804A
Other languages
English (en)
Other versions
CN101697344B (zh
Inventor
何军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN2009101978044A priority Critical patent/CN101697344B/zh
Publication of CN101697344A publication Critical patent/CN101697344A/zh
Application granted granted Critical
Publication of CN101697344B publication Critical patent/CN101697344B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48092—Helix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Wire Bonding (AREA)

Abstract

本发明提供了一种降低芯片电源焊盘键合引线上电流的方法，所述芯片上设有多个电源焊盘以及多个置于所述芯片四角用于缓解芯片应力的虚拟焊盘，所述电源焊盘和所述虚拟焊盘皆连接电源总线，且通过键合引线与引线框架电连接。本发明降低了每根键合引线上的电流，因此减少了键合引线上的电感，降低了因电感引起的噪音，而且整个键合工艺较易实现，没有额外的占用芯片的面积。

Description

一种降低芯片电源焊盘键合引线上电流的方法
技术领域
本发明属于一种半导体工艺，尤其涉及一种降低芯片电源焊盘键合引线上电流的方法。
背景技术
硅片在通过电测试后，便开始进行单个芯片的装配和封装。传统工艺中，集成电路最终装配从硅片上分离出每个好的芯片并将芯片粘贴在金属引线框架或管壳上。对于引线框架装配，用细线将芯片表面的金属焊盘和提供芯片点通路的引线框架内端互连起来。
在现代越来越讲究快速的时代，数据处理趋向超高频，而越来越高的输出入(I/O)运作速率系统环境也相对发展，而使同步转换输出(simultaneousswitching output，SSO)成为一个重要的课题，这个问题也非常明显的体现在芯片的引线键合的过程中。
现有技术中，在输出入总线(I/O bus)上设计输出输入缓冲器时，会遇到由同步转换输出造成的信号变动噪声，尤其是在多个资料位同时由1切换到0或者由0切换到1时，也就是由高电位转为低电位，或者由低电位转为高电位时，电源需在极短时间内提供很大电流。这种瞬变的大电流使得电源焊垫键合引线的寄生电感效应不可忽略，造成电源和接地端发生准变动。该变动会造成与该电源相连的“静态”输出电平的不稳定，减少输出电平的有效范围甚至出现误码电平。在将芯片表面的键合电源焊盘和引线框架上或基座上的电极内端进行电连接之后，由于上述所提到的同步转换输出原理，在芯片上也会存在短时间内因电流较大而引起有效资料缺失的问题，因此如何降低电源焊垫的键合引线上的电流成为解决这一问题的关键。
为了降低键合引线上的电流，通常研发人员会在电源焊盘的一侧，再增加一个用于电连接的相同的电源焊盘，如图1所示，两个电源焊盘11、12分别通过键合引线15连接到引线框架上或基座上的电极内端14，这样每个键合引线15上的电流便只有原先的一半，另外，为了缓解芯片上的应力，平衡芯片的格局，都会在实际进行电连接的键合电源焊盘的一侧，放置多个虚拟焊盘13。这种方法虽然降低了引线上的电流，但是却额外的增加了一个键合电源焊盘11，占用了芯片上的面积。另一种方法是在键合电源焊盘和引线框架上或基座上的电极内端之间用两根键合引线相连，这样也能起到分流的作用，但是在引线框架上或基座上的电极内端上连两根键合引线容易实现，而在表面积很小的键合电源焊盘上连接两根键合引线，则比较困难，即使连好了，性能的稳定性也大大的降低了。因此，这种方法对工艺的要求很高，也不容易推广。
芯片封装时需固定在封装基板上。以塑料封装为例，由于以硅为主的芯片和以塑料为封装基板的热膨胀系数差异较大，温度变化会使芯片周边尤其是四角承受很大的形变应力。该应力会造成芯片四角薄膜剥离甚至垮裂。所以一般在芯片四角都有专门的角单元设计(corner cell design)用以缓解芯片边角所受的形变应力。常用的角单元设计包含宽电源总线金属45度转角以及添加虚拟焊盘。该虚拟焊盘不与任何电源总线连接，也不用键合引出，纯粹为了利用金属较好的伸缩性提高芯片边角抗形变应力的能力。也就是说，一般芯片有四个角单元，每个角单元至少有两个甚至六个这样的虚拟焊盘。本发明就是利用这些已有的虚拟焊盘，在不增加芯片面积的情况下减少电源焊盘键合引线的电流。
发明内容
为了解决现有技术中存在的连接电源焊盘和引线框架的键合引线上电流过大而引起同步转换输出的问题，本发明提供一种不增加芯片面积且能降低电源焊垫的键合引线上的电流的方法。
为了实现上述目的，本发明提出一种降低芯片电源焊盘键合引线上电流的方法，所述芯片上设有多个电源焊盘以及多个置于所述芯片四角用于缓解芯片应力的虚拟焊盘，所述电源焊盘和所述虚拟焊盘皆连接电源总线，且所述电源焊盘和所述虚拟焊盘通过键合引线与引线框架电连接。
可选的，所述电源焊盘和所述虚拟焊盘为矩形、八角形或圆形。
可选的，所述键合引线的直径范围为25μm至75μm。
可选的，所述电源焊盘和所述虚拟焊盘通过热压键合或超声键合电连接所述引线框架。
可选的，所述键合引线为铜线或者铝线。
本发明一种降低芯片电源焊盘键合引线上电流的方法的有益技术效果为：本发明通过将电源焊盘和虚拟焊盘均与引线框架相连，从而降低了每根键合引线上的电流，因此减少了电源焊盘键合引线上电感引起的噪声，而且整个键合工艺较易实现，没有额外的占用芯片的面积。
附图说明
图1是现有技术的芯片上连接方式的结构示意图；
图2是本发明一种降低芯片电源焊盘键合引线上电流的方法的流程示意图；
图3是本发明一种降低芯片电源焊盘键合引线上电流的方法的一实施例的结构示意图。
具体实施方式
以下结合附图和具体实施方式对本发明作进一步的详细说明。
首先，请参考图2，图2是本发明一种降低芯片电源焊盘键合引线上电流的方法的流程示意图，从图2可以看出，本发明包括以下步骤：步骤21：在所述芯片上设置多个电源焊盘，所述电源焊盘为矩形、八角形或圆形；步骤22：在所述芯片四角设置多个用于缓解芯片应力的虚拟焊盘，所述虚拟焊盘为矩形、八角形或圆形；步骤23：所述电源焊盘和所述虚拟焊盘皆连接电源总线，且所述电源焊盘和所述虚拟焊盘通过键合引线与引线框架电连接，所述键合引线的直径范围为25μm至75μm，所述电源焊盘和所述虚拟焊盘电连接所述引线框架的引线键合的方法为热压键合或超声键合，所述键合引线为铜线或者铝线，通过将电源焊盘和虚拟焊盘均与引线框架相连，从而可以最大限度的分流原先键合引线上的电流，即当电源焊盘角单元内有四个虚拟焊盘时，将四个虚拟焊盘全部通过键合引线和引线框架相连，从而每个引线框架上的电流便为原先电流的五分之一。图3是本发明一种降低芯片电源焊盘键合引线上电流的方法的一实施例的结构示意图，从图上可以清楚的看到，电源焊盘12和位于其一侧的虚拟焊盘13皆连接电源总线，且通过键合引线15和引线框架14电连接。通过将电源焊盘和虚拟焊盘均与引线框架相连，从而实现了分流，降低了键合引线上的电流，而且较易实现，由于利用的是角单元内已有的虚拟焊盘键合引出帮助分担大的电源电流，所以不需要额外增加芯片的面积，此外对于虚拟焊盘的作用减小芯片上的应力和平衡芯片的格局，也未产生任何影响。
虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明。本发明所述技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视权利要求书所界定者为准。

Claims (5)

1.一种降低芯片电源焊盘键合引线上电流的方法，所述芯片上设有多个所述电源焊盘以及多个置于所述芯片四角用于缓解芯片应力的虚拟焊盘，其特征在于：所述电源焊盘和所述虚拟焊盘皆连接电源总线，且所述电源焊盘和所述虚拟焊盘通过键合引线与引线框架电连接。
2.根据权利要求1所述的一种降低芯片电源焊盘键合引线上电流的方法，其特征在于所述电源焊盘和所述虚拟焊盘为矩形、八角形或圆形。
3.根据权利要求1所述的一种降低芯片电源焊盘键合引线上电流的方法，其特征在于所述键合引线的直径范围为25μm至75μm。
4.根据权利要求1所述的一种降低芯片电源焊盘键合引线上电流的方法，其特征在于所述电源焊盘和所述虚拟焊盘通过热压键合或超声键合电连接所述引线框架。
5.根据权利要求1所述的一种降低芯片电源焊盘键合引线上电流的方法，其特征在于所述键合引线为铜线或者铝线。
CN2009101978044A 2009-10-28 2009-10-28 一种降低芯片电源焊盘键合引线上电流的方法 Active CN101697344B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2009101978044A CN101697344B (zh) 2009-10-28 2009-10-28 一种降低芯片电源焊盘键合引线上电流的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2009101978044A CN101697344B (zh) 2009-10-28 2009-10-28 一种降低芯片电源焊盘键合引线上电流的方法

Publications (2)

Publication Number Publication Date
CN101697344A true CN101697344A (zh) 2010-04-21
CN101697344B CN101697344B (zh) 2012-10-31

Family

ID=42142441

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009101978044A Active CN101697344B (zh) 2009-10-28 2009-10-28 一种降低芯片电源焊盘键合引线上电流的方法

Country Status (1)

Country Link
CN (1) CN101697344B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035599A (zh) * 2011-09-28 2013-04-10 台湾积体电路制造股份有限公司 管芯中的金属焊盘结构
CN112770477A (zh) * 2019-10-21 2021-05-07 华为技术有限公司 一种电路板组件和电子设备

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0760838B2 (ja) * 1990-11-13 1995-06-28 株式会社東芝 半導体装置
KR0177744B1 (ko) * 1995-08-14 1999-03-20 김광호 전기적 특성이 향상된 반도체 장치
US6717270B1 (en) * 2003-04-09 2004-04-06 Motorola, Inc. Integrated circuit die I/O cells
JP2008112897A (ja) * 2006-10-31 2008-05-15 Matsushita Electric Ind Co Ltd 半導体集積回路及びその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035599A (zh) * 2011-09-28 2013-04-10 台湾积体电路制造股份有限公司 管芯中的金属焊盘结构
CN103035599B (zh) * 2011-09-28 2016-01-20 台湾积体电路制造股份有限公司 管芯中的金属焊盘结构
CN112770477A (zh) * 2019-10-21 2021-05-07 华为技术有限公司 一种电路板组件和电子设备
CN112770477B (zh) * 2019-10-21 2022-09-23 华为技术有限公司 一种电路板组件和电子设备

Also Published As

Publication number Publication date
CN101697344B (zh) 2012-10-31

Similar Documents

Publication Publication Date Title
US11961804B2 (en) Size and efficiency of dies
WO2007146307A2 (en) Stack die packages
CN103117263A (zh) 一种集成电路封装
TW567602B (en) Multi-chip module
KR101333387B1 (ko) 파워 및 접지 관통 비아를 갖는 패키지
JPH0689962A (ja) 半導体装置
CN101697344B (zh) 一种降低芯片电源焊盘键合引线上电流的方法
US7863716B2 (en) Method and apparatus of power ring positioning to minimize crosstalk
CN102222660B (zh) 双引线框架多芯片共同封装体及其制造方法
CN213184284U (zh) 一种集成封装的门极驱动电路
CN215600357U (zh) 一种高功率密度的sop8l封装引线框架
CN101404271B (zh) 音频功率放大器封装结构
CN209544315U (zh) 一种esop8双基岛封装框架
CN102332410A (zh) 一种芯片的封装方法及其封装结构
CN201000885Y (zh) 一种无引线集成电路芯片封装
CN115188746B (zh) 一种用于计算机微系统的电子封装结构
CN216354180U (zh) 集成电路封装结构
CN210723009U (zh) 带有转接板的qfn结构
CN109979892A (zh) Esop8双基岛封装框架
US20090278247A1 (en) Bonding pad sharing method applied to multi-chip module and apparatus thereof
CN203278755U (zh) 封装有多个音频功率放大电路晶片的芯片
CN210692525U (zh) 一种sot双芯片引线框架结构
US20180358275A1 (en) Face Down Dual Sided Chip Scale Memory Package
US20210358894A1 (en) Multi-Tier Processor/Memory Package
CN202871770U (zh) 一种紧凑型智能功率驱动模块

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING

Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI

Effective date: 20140514

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20140514

Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399

Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Address before: 201203 Shanghai Guo Shou Jing Road, Zhangjiang hi tech Park No. 818

Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai