CN101651141A - 半导体器件和制造半导体器件的方法 - Google Patents

半导体器件和制造半导体器件的方法 Download PDF

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CN101651141A
CN101651141A CN200910166067A CN200910166067A CN101651141A CN 101651141 A CN101651141 A CN 101651141A CN 200910166067 A CN200910166067 A CN 200910166067A CN 200910166067 A CN200910166067 A CN 200910166067A CN 101651141 A CN101651141 A CN 101651141A
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gate electrode
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川口宏
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Abstract

本发明涉及半导体器件和制造半导体器件的方法。该半导体器件包括：高耐压晶体管(128)；栅电极(110)，该栅电极形成在沟道区(170)上；第一导电类型源区(116a)和第一导电类型漏区(116b)，该第一导电类型源区(116a)形成在沟道区(170)的一侧，该第一导电类型漏区(116b)形成在沟道区(170)的另一侧；以及漂移区(172)，该漂移区(172)设置在源区(116a)和漏区(116b)之间并且具有超结结构，在该超结结构中，第一导电类型杂质扩散区和第二导电类型杂质扩散区沿着栅电极(110)的栅宽度方向以恒定宽度的规则间隔交替布置。从平面图看，栅电极具有梳状结构，该梳状结构包括覆盖漂移区(172)的第二导电类型杂质扩散区的梳齿。

Description

半导体器件和制造半导体器件的方法
技术领域
本发明涉及半导体器件和制造半导体器件的方法。
背景技术
传统地，已知存在具有超结结构的横向场效应晶体管(参见US7,023,050、US 7,202,526、US 7,105,387(称作“专利文件1至3”)和Proceedings of the 17International Symposium on power SemiconductorDevices & IC’s，May 23to 26，2005(2005年5月23日至26日在第17届功率半导体器件和集成电路国际研讨会会议论文集)上由S.Iwamoto、K.Takahashi、H.Kuribayashi、S.Wakimoto、k.Mochizuki和H.Nakazawa所著的名为“Above 500V class Superjunction MOSFETs fabricated bydeep trench etching and epitaxial growth”的文章(下文中，称作非专利文件1))。
图17是示出横向场效应晶体管结构的平面图。在图17中，示出了半导体器件10的半导体衬底22和栅电极24的表面结构。半导体器件10包括p型沟道区12、p型杂质扩散区14、n型源区16a、n型漏区16b以及设置在沟道区12和漏区16b之间的漂移区18。漂移区18具有超结结构，在该超结结构中，n型柱20a和p型柱20b沿着栅电极24的栅宽度方向以规则的间隔交替布置。
如上所述的超结结构使得n型柱20a和p型柱20b在预定电场中能够完全耗尽，由此具有超结结构的晶体管的电场与没有超结结构的晶体管的电场相比更缓和(mitigated)。因此，即使当衬底表面的杂质浓度设置得高时，也实现了高的耐压(withstanding voltage)特性。
本发明的发明者已经认识到如下问题。传统上，已经存在形成漂移区18的超结结构的制造步骤较复杂的问题。即，例如，如非专利文件1中所描述的，在具有一个导电类型的衬底中形成沟槽，并且通过外延生长形成具有相反导电类型的柱。
另外，当形成漂移区18时，必须考虑相对于栅电极24的对准误差。因此，如图17中箭头所示，需要增加栅电极24和漂移区18之间的余量，这造成了器件面积变大的问题。此外，对准误差会造成在耐压、操作过程中的电阻等方面的特性波动。
发明内容
根据本发明的一方面，提供了一种包括场效应晶体管的半导体器件，其包括：衬底；栅电极，所述栅电极形成在所述衬底的沟道区上；第一导电类型源区和第一导电类型漏区，所述第一导电类型源区和所述第一导电类型漏区在所述衬底表面的上方，且所述第一导电类型源区形成在所述沟道区的一侧，所述第一导电类型漏区形成在所述沟道区的另一侧；以及漂移区，所述漂移区设置在所述沟道区和所述漏区之间并且具有超结结构，在所述超结结构中，第一导电类型杂质扩散区和第二导电类型杂质扩散区沿着所述栅电极的栅宽度方向以恒定宽度的规则间隔交替布置，其中，从平面图来看，所述栅电极形成为梳状结构，所述梳状结构包括覆盖所述漂移区的所述第二导电类型杂质扩散区的梳齿。
根据本发明的另一方面，提供了一种制造半导体器件的方法。该方法包括形成场效应晶体管，所述形成所述场效应晶体管包括：在衬底的沟道区上形成梳状的栅电极，所述栅电极包括沿着栅长度方向在所述沟道区的至少一侧的梳齿，所述衬底具有在上形成有第二导电类型区域的表面；使用栅电极作为掩模，将第一导电类型杂质离子注入到所述衬底中，并且在所述栅电极的所述梳齿之间的区域中形成第一导电类型杂质扩散区，由此形成具有超结结构的漂移区，在所述超结结构中，所述第一导电类型杂质扩散区和第二导电类型杂质扩散区沿着所述栅电极的栅宽度方向以恒定宽度的规则间隔交替布置；以及将所述第一导电类型杂质离子注入到所述衬底的所述沟道区的两侧，由此沿着所述栅长度方向，在所述沟道区的一侧形成第一导电类型漏区并且在所述沟道区的另一侧形成第一导电类型源区。
根据上述结构，场效应晶体管包括梳状的栅电极，并且因此可以使用栅电极作为掩模以自对准方式形成漂移区。因此，栅电极和漂移区之间的距离可以由栅电极的形状来限定。与漂移区独立于栅电极形成的情况相比，不需要提供余量，否则在考虑到对准误差时要形成所述余量，由此可以防止器件面积不必要地增大。此外，没有造成对准误差，因此可以防止耐压、操作过程中的电阻等的特性波动。
应该注意的是，本发明的有效模式包括以上提及组件的任意组合，以及根据本发明表达方式的方法和器件之间的替换。
根据本发明，获得一种半导体器件，该半导体器件包括利用简单工序而具有高对准精度的横向场效应晶体管。
附图说明
结合附图，从对某些优选实施例的以下描述中，本发明的以上和其它目的、优点和特征将更清楚，在附图中：
图1是根据本发明的第一实施例的半导体器件结构的透视图；
图2是示出根据本发明的第一实施例的半导体器件的半导体衬底表面结构的平面图；
图3A和图3B是均示出根据本发明的第一实施例的半导体器件的制造工序的视图；
图4A和图4C是均示出根据本发明的第一实施例的半导体器件的制造工序的视图；
图5A和图5C是均示出根据本发明的第一实施例的半导体器件的制造工序的视图；
图6A和图6C是均示出根据本发明的第一实施例的半导体器件的制造工序的视图；
图7A和图7B是均示出根据本发明的第一实施例的半导体器件的制造工序的视图；
图8A和图8B是均示出根据本发明的第一实施例的半导体器件的制造工序的视图；
图9A和图9B是均示出根据本发明的第一实施例的半导体器件的制造工序的视图；
图10是根据本发明的第二实施例的半导体器件的平面图；
图11A和图11B是均示出根据本发明的第二实施例的半导体器件的制造工序的步骤剖视图；
图12A和图12B是均示出根据本发明的第二实施例的半导体器件的制造工序的步骤剖视图；
图13A和图13B是均示出根据本发明的第二实施例的半导体器件的制造工序的步骤剖视图；
图14A和图14B是均示出根据本发明的第二实施例的半导体器件的制造工序的步骤剖视图；
图15A和图15B是均示出根据本发明的第二实施例的半导体器件的制造工序的步骤剖视图；
图16是示出根据本发明的第二实施例的半导体器件的平面图；
图17是示出半导体器件结构的平面图，用于描述现有技术中的问题；
图18是示出根据本发明的另一个实施例的半导体器件的半导体衬底表面结构的示例的平面图。
具体实施方式
下文中，参照附图描述本发明的实施例。应该注意的是，在各个附图中，用相同的参考符号来表示相同的组件，并且适当省略了对其的描述。
(第一实施例)
图1是示出根据该实施例的半导体器件结构的透视图。图2是示出半导体器件的半导体衬底表面结构的平面图。
在该实施例中，半导体器件100包括作为横向场效应晶体管的高耐压晶体管128。半导体器件100包括半导体衬底(衬底)101、形成在半导体衬底101上的p阱102、在p阱102内形成在p型(第二导电类型)沟道区170上的栅电极110、以及在栅电极110的两侧都形成的侧壁114。
半导体器件100在半导体衬底101的表面上包括：n型(第一导电类型)源区116a，该n型源区116a形成在沟道区170的一侧；n型漏区116b，该n型漏区116b形成在沟道区170的另一侧；漂移区172，该漂移区172设置在沟道区170和漏区116b之间；n型扩展区174，该n型扩展区174设置在沟道区170和源区116a之间；以及n型扩展区176，该n型扩展区176设置在漂移区172和漏区116b之间。
这里，漂移区172具有超结结构，在该结结构中，n型杂质扩散区(柱)180和p型杂质扩散区(柱)182沿着栅电极110的栅宽度方向以恒定的规则间隔交替布置。如以下所描述的，通过将n型杂质注入到事先引入了p型杂质的区域(p型杂质扩散区106)中来形成n型杂质扩散180。在这种情况下，注入的n型杂质的浓度高于p型杂质扩散区106中p型杂质的浓度。同时，在如在漂移区172的情况下的超结结构中，期望的是，将空间电荷设置成在p型杂质扩散区和n型杂质扩散区中相等。通过以上提及的内容，确定栅电极110的梳齿的宽度和间隔。当栅电极110的梳齿宽度被设置成大于其梳齿之间的间隔时，可以令人满意地实现空间电荷的平衡。在该实施例中，从平面图看，栅电极110形成为梳状结构，该结构包括覆盖漂移区172的p型杂质扩散182的梳齿。在该实施例中，栅电极110的形状与漂移区172的p型杂质扩散区182和沟道区170重叠。在该实施例中，使用栅电极110的梳齿作为掩模，以自对准方式形成漂移区172的n型杂质扩散区180。
侧壁114在漂移区172的p型杂质扩散区182上填充栅电极110的梳齿之间的区域。在该实施例中，使用侧壁114作为掩模，以自对准方式形成源区116a和漏区116b。因此，通过侧壁114的宽度来限定沟道区170和源区116之间的间隔以及漂移区172和漏区116b之间的间隔。
应该注意的是，在该实施例中，以n型场效应晶体管(n-FET)作为示例来进行描述，其中，第一导电类型是n型而第二导电类型是p型。可选择地，也可以通过相同的结构来形成第一导电类型是p型而第二导电类型是n型的p型场效应晶体管(p-FET)。
另外，该实施例可以具有如下结构，在所述结构中，高耐压晶体管128可以具有，例如大致10V至20V的耐压。
接着，描述了根据该实施例的半导体器件100的制造工序。
图3A至图9B是均示出根据该实施例的半导体器件100的制造工序的视图。图3A、图4A、图5A、图6A、图7A、图8A和图9A是均示出半导体器件100的结构的平面图。图3B、图4B、图5B、图6B、图7B、图8B和图9B分别是沿着图3A至图9A中的a-a线截取的剖视图。图4C、图5C和图6C分别是沿着图4A至图6A中的b-b线截取的剖视图。
首先，在半导体衬底101的表面上形成器件隔离绝缘膜104。随后，在半导体衬底101的表面上的预定区域中形成p阱102。然后，通过将p型杂质离子注入(例如，在15keV和6E12cm-2的条件下)到要用作漂移区172的区域中，在半导体衬底101的p阱102内部形成p型杂质区106(图3A和图3B)。
此后，用于形成栅绝缘膜108的绝缘膜和用于形成栅电极110的导电膜以所述的次序层压在半导体衬底101上方的整个表面上。在该实施例中，例如，栅绝缘膜108可以由(例如)氧化硅膜、高电介质膜、或包括氧化硅膜和高电介质膜的层压膜来形成。在该实施例中，用于形成栅电极110的导电膜可以由，例如，多晶硅形成。随后，将导电膜和绝缘膜图案化为预定形状。结果，栅绝缘膜108和栅电极110形成在半导体衬底101之上(图4A、图4B和图4C)。
在该实施例中，从平面图看，将栅电极110形成为梳状，并且该梳状的梳齿被布置在要用作漂移区172的区域中。形成栅电极110的梳齿，使其在要用作漂移区172的区域的形成n型杂质扩散区180的部分中开口，并且覆盖形成p型杂质扩散区182的部分。从平面图看，栅绝缘膜108与栅电极110一起被图案化，以具有与栅电极110的形状相同的形状。
采用该结构，栅电极110和漂移区172之间的距离可以由栅电极110的形状来限定。不需要在栅电极24和漂移区18之间设置用图17中箭头表示的余量，其中，考虑到如在使用光致抗蚀剂的情况中的对准误差而形成所述余量，由此防止器件面积不必要地增大。
接着，通过使用栅电极110作为掩模，将n型杂质离子注入(例如，在10keV和1E13cm-2的条件下)到半导体衬底101中，来形成n型杂质扩散区112(图5A、图5B和图5C)。在这种情况下，注入的n型杂质离子的浓度会超过p型杂质扩散区106中的p型杂质离子的浓度。在该实施例中，从平面图看，将栅电极110形成为梳状，由此n型杂质离子被注入到栅电极110的梳齿之间的区域，如图5C中所示。结果，形成如图2中所示的超结结构。
接着，在半导体衬底101上方的整个表面上形成绝缘膜。这里，例如，可以通过化学气相沉积(CVD)沉积硅氧化物(SiO2)膜，或者通过层压由CVD沉积的硅氧化物膜和由CVD沉积的氮化硅(Si3N4)膜，来形成绝缘膜。沉积的绝缘膜的厚度被设置成栅电极110的梳齿之间间隔的至少一半。以此方式，栅电极110的梳齿之间的空间由绝缘膜填充。此后，通过各向异性蚀刻执行回蚀，以暴露栅电极110和半导体衬底101中形成有源区116a和漏区116b的部分，并且在栅电极110的两侧都形成侧壁114(图6A、图6B和图6C)。在这种情况下，栅电极110的梳齿之间的空间由绝缘膜填充，因此即使在执行了各向异性蚀刻之后也保留了绝缘膜。因此，在整个表面上方形成栅电极110，并且将栅电极110形成到其梳齿的顶部情况下，形成侧壁114，使得距离d等于距离d′。距离d表示从栅电极110的梳齿顶部到要形成漏区116b一侧的侧壁114的一端的距离。距离d′表示栅电极110的端部到要形成的源区116a一侧的侧壁114的另一端的距离。
采用该结构，栅电极110和漏区116b之间的距离可以由侧壁114来限定。不需要在栅电极24和漏区16b之间设置用图17中箭头表示的余量，其中，考虑到如在使用光致抗蚀剂的情况中的对准误差而形成所述余量，由此防止器件面积不必要地增大。
接下来，通过使用侧壁114作为掩模，将n型杂质离子注入(例如，在10keV和3E15cm-2的条件下)到半导体衬底101中，来形成源区116a和漏区116b(图7A和图7B)。在栅电极110由多晶硅形成的情况下，n型杂质离子也注入到栅电极110中。然后，注入的离子在半导体衬底内通过快速热退火(RTA)等被电激活，例如，在快速热退火中，执行1000℃的热处理30秒。
随后，在半导体衬底101上方的整个表面上形成诸如Ni或Co层的金属层，由此选择性地硅化(自对准硅化(salicide：self-alignedsilicidation))源区116a和漏区116b的表面，其表面被暴露于半导体衬底101之上。结果，在源区116a和漏区116b的表面上形成硅化物层120。同时，在栅电极110的表面上形成硅化物层118(图8A和图8B)。
此后，在半导体衬底101上方的整个表面上形成层间绝缘膜122。在层间绝缘膜122中形成接触孔，以暴露源区116a和漏区116b上形成的硅化物层120，和栅电极110上形成的硅化物层118。随后，用导电材料填充接触孔，由此形成接触124。另外，在层间绝缘膜122上形成层间绝缘膜(未示出)，并且在所形成的层间绝缘膜中形成布线凹槽。然后，用导电材料填充布线凹槽，由此形成布线126。通过以上提及的工序，完成半导体器件100(图9A和图9B)。
根据该实施例的半导体器件100，高耐压晶体管128包括梳状的栅电极110，由此可以使用栅电极110作为掩模以自对准方式来形成漂移区172。因此，栅电极110和漂移区172之间的距离可以由栅电极110的形状来限定。不需要设置当考虑到如在使用光致抗蚀剂的情况下的对准误差而形成的余量，由此可以防止器件面积不必要地增大。
另外，栅电极110具有梳状，因此侧壁114可以填充栅电极110的梳齿之间的区域，并且具有预定宽度的侧壁114可以形成在栅电极110的两侧。采用该结构，可以用侧壁114的宽度来限定栅电极110和漏区116b之间的距离。不需要设置当考虑到如在使用光致抗蚀剂的情况下的对准误差而形成的余量，由此可以防止器件面积不必要地增大。
例如，假设存在如下情况，其中，不采用如在该实施例中的结构，并且使用光致抗蚀剂等将漂移区172图案化。在这种情况下，考虑到对准误差，在设置相对于栅电极110的余量的同时，需要形成用于形成漂移区172的抗蚀剂膜。结果，栅电极110和漂移区172之间的距离不必要地增大，由此器件面积变大。根据该实施例的半导体器件100，可以避免这种问题。此外，没有造成对准误差，因此可以防止耐压、操作过程中的电阻等的特性波动。
(第二实施例)
除了第一实施例中描述的高耐压晶体管128之外，根据该实施例的半导体器件100进一步包括形成在其中的低耐压晶体管。下文中，描述了同时形成高耐压晶体管128和低耐压晶体管的工序。
图10和图16是均示出根据该实施例的半导体器件100的平面图。图11A至图15B是均示出根据该实施例的半导体器件100制造工序的视图。图11A至图12A均对应于沿着图10中的a-a线截取的剖视图。图12B至图15B均对应于沿着图16中的a-a线截取的剖视图。
半导体器件100设置有高耐压区200和低耐压区202，其中，高耐压晶体管128形成在高耐压区200中，低耐压晶体管142形成在低耐压区202中。
首先，在半导体衬底(未示出)的表面上形成器件隔离绝缘膜104。随后，还是在该实施例中，在半导体衬底表面上的预定区域中形成p阱102。与第一实施例类似地，在该实施例中，p阱102形成在半导体衬底101的表面上，但是从附图中省略了半导体衬底101。然后，在高耐压区200的半导体衬底上的p阱102内，通过将p型杂质离子注入(例如，在15keV和6E12cm-2的条件下)到要用作漂移区172的区域中，形成p型杂质扩散区106(图10和图11A)。
此后，在半导体衬底之上的p阱102的整个表面上形成栅绝缘膜108。这里，可以由，例如，通过氧化p阱102的表面得到的硅氧化物膜来形成栅绝缘膜108。随后，形成抗蚀剂膜130，抗蚀剂膜130选择性地覆盖高耐压区200并且在低耐压区202中开口(图11B)。然后，通过采用，例如，氟化氢(HF)的蚀刻，移除低耐压区202中暴露的栅绝缘膜108。随后，在低耐压区202中形成栅绝缘膜132，栅绝缘膜132的膜厚度小于栅绝缘膜108的厚度(图12A)。栅绝缘膜132可以由，例如，通过氧化p阱102的表面得到的硅氧化物膜形成。
此后，在p阱102上方的整个表面上形成用于形成栅电极110a和110b的导电膜。随后，将导电膜以及栅绝缘膜108和132图案化成预定形状。结果，分别在p阱102之上的高耐压区200和低耐压区202中形成栅电极110a和栅电极110b(图16和图12B)。这里，栅电极110a的结构与第一实施例中描述的栅电极110的结构相同。另外，将栅绝缘膜108与栅电极110a一起被图案化，以具有与栅电极110a相同的形状。类似地，将栅绝缘膜132与栅电极110b一起被图案化，以具有与栅电极110b相同的形状。
然后，形成抗蚀剂膜134，抗蚀剂膜134选择性地覆盖低耐压区202并且开口于高耐压区200。随后，使用栅电极110a作为掩模，将n型杂质离子注入(例如，在10keV和1E13cm-2的条件下)到p阱102中，由此在高耐压区200中形成n型杂质扩散区112(图13A)。这里，注入的n型杂质离子的浓度可以被设置成与第一实施例中相同的值。
此后，形成抗蚀剂膜136，抗蚀剂膜136选择性地覆盖高耐压区200并且开口于低耐压区202。随后，使用栅电极110b作为掩模，将n型杂质离子注入(例如，在20keV和1E14cm-2的条件下)到p阱102中，由此在高耐压区200中形成n型扩展区138(图13B)。
接着，在p阱102上方的整个表面上形成绝缘膜。这里，例如，可以通过化学气相沉积(CVD)沉积硅氧化物(SiO2)膜、或者通过层压由CVD沉积的硅氧化物膜和由CVD沉积的氮化硅(Si3N4)膜，形成绝缘膜。沉积的绝缘膜的膜厚度被设置为栅电极110a的梳齿之间间隔的至少一半。以此方式，栅电极110a的梳齿之间的间隔可以被绝缘膜填充。
此后，执行各向异性蚀刻来暴露栅电极110a和110b，以及半导体衬底的在高耐压区200中形成源区116a和漏区116b处以及在低耐压区202中形成源区140a和漏区140b处的部分。另外，在栅电极110a的两侧以及栅电极110b的两侧都形成侧壁114(图14A)。
接下来，使用侧壁114作为掩模，将n型杂质离子注入(例如，在10keV和3E15cm-2的条件下)注入到半导体衬底中，由此分别在高耐压区200中形成源区116a和漏区116b，并且在低耐压区202中形成源区140a和漏区140b(图14B)。然后，注入的离子在半导体衬底内通过快速热退火(RTA)等被电激活，例如，在快速热退火中，执行1000℃的热处理30秒。
随后，在半导体衬底上方的整个表面上形成诸如Ni或Co层的金属层，由此选择性地硅化(自对准硅化(salicide：self-alignedsilicidation))源区116a、漏区116b、源区140a、漏区140b以及栅电极110a和110b的表面，使其表面暴露于半导体衬底之上。结果，在源区116a、漏区116b、源区140a和漏区140b上形成硅化物层120。同时，在栅电极110a和110b的表面上形成硅化物层118(图15A)。
此后，在半导体衬底上方的整个表面上形成层间绝缘膜122。在层间绝缘膜122中形成接触孔，以暴露形成在源区116a、漏区116b、源区140a和漏区140b上的硅化物层120，以及形成在栅电极110a和110b上的硅化物层118。随后，用导电材料填充接触孔，由此形成接触件124。另外，在层间绝缘膜122上形成层间绝缘膜(未示出)，并且在所形成的层间绝缘膜中形成布线凹槽。然后，用导电材料填充布线凹槽，由此形成布线126。通过以上提及的工序，完成半导体器件100(图15B)。
同样，在该实施例中，也可以得到与第一实施例相同的效果。可以以简单的工序在相同的步骤中形成低耐压晶体管142和高耐压晶体管128。
在上文中，参照附图描述的本发明的实施例仅被当作本发明的示例。因此，本发明可以采用除了这些实施例的结构之外的各种结构。
在上述实施例中，示例了如下的情况，其中，在高耐压晶体管128的沟道区170和漏区116b之间形成漂移区172。然而，可以采用如下的结构，其中，在沟道区170和源区116a之间也设置漂移区172。可以以下面的方式形成具有以上提及的结构的高耐压晶体管128。即，栅电极110的梳齿也设置在源区116a侧，并且使用栅电极110作为掩模，形成n型杂质扩散区112。图18是示出具有上述结构的半导体器件110的半导体衬底的p阱102表面结构的平面图。采用该结构，即使在源和漏的使用功能调换的情况下，也可以实现高耐压晶体管128的高耐压特性。
在上述实施例中，示例了如下的情况，其中，p型杂质扩散区106选择性地只设置在要用作漂移区172的区域中，但是p阱102可以用作p型杂质扩散区106。具体地来讲，可以对沟道区170和漂移区172的p型杂质扩散区182进行设置，以使其具有相同的浓度分布。
明显的是，本发明不限于以上实施例，而是可以在不脱离本发明的范围和精神的情况下对其进行修改和变化。

Claims (10)

1.一种包括场效应晶体管的半导体器件，所述场效应晶体管包括：
衬底；
栅电极，所述栅电极形成在所述衬底的沟道区上；
第一导电类型源区和第一导电类型漏区，所述第一导电类型源区和所述第一导电类型漏区在所述衬底表面之上，所述第一导电类型源区形成在所述沟道区的一侧，所述第一导电类型漏区形成在所述沟道区的另一侧；以及
漂移区，所述漂移区设置在所述沟道区和所述漏区之间，并且具有超结结构，在所述超结结构中，第一导电类型杂质扩散区和第二导电类型杂质扩散区沿着所述栅电极的栅宽度方向以恒定宽度的规则间隔交替布置，
其中，从平面图来看，所述栅电极被形成为梳状结构，所述梳状结构包括覆盖所述漂移区的所述第二导电类型杂质扩散区的梳齿。
2.根据权利要求1所述的半导体器件，其中，使用所述栅电极的梳齿作为掩模，以自对准方式形成所述漂移区中的所述第一导电类型杂质扩散区。
3.根据权利要求1所述的半导体器件，进一步包括侧壁，所述侧壁在所述衬底之上沿着栅长度方向形成在所述栅电极的两侧，并且填充所述漂移区中所述第一导电类型杂质扩散区上的所述栅电极的所述梳齿之间的区域。
4.根据权利要求3所述的半导体器件，其中，使用所述侧壁作为掩模，以自对准方式形成所述源区和所述漏区。
5.根据权利要求1所述的半导体器件，进一步包括设置在所述沟道区和所述源区之间的另一个漂移区，
其中，所述栅电极的所述梳齿设置在所述沟道区和所述源区之间设置的所述另一个漂移区上。
6.根据权利要求1所述的半导体器件，进一步包括在所述衬底上的第二场效应晶体管，所述第二场效应晶体管设置在与所述场效应晶体管相同的层中，并且所述第二场效应晶体管的耐压低于所述场效应晶体管的耐压，
其中，所述第二场效应晶体管包括：
第二栅电极，所述第二栅电极形成在所述衬底的第二沟道区上；
第一导电类型第二源区和第一导电类型第二漏区，所述第一导电类型第二源区和所述第一导电类型第二漏区在所述衬底的表面之上，所述第一导电类型第二源区形成在所述第二沟道区的一侧，所述第一导电类型第二漏区形成在所述第二沟道区的另一侧；以及
第一导电类型扩展区，在所述第二沟道区和所述第二源区之间以及在所述第二沟道区和所述第二漏区之间都设置了所述第一导电类型扩展区。
7.一种制造半导体器件的方法，所述方法包括形成场效应晶体管，所述形成所述场效应晶体管包括：
在衬底的沟道区上形成梳状的栅电极，所述栅电极包括沿着栅长度方向在所述沟道区的至少一侧的梳齿，所述衬底具有在其上形成有第二导电类型区域的表面；
使用所述栅电极作为掩模，将第一导电类型杂质离子注入到所述衬底中，并且在所述栅电极的所述梳齿之间的区域中形成第一导电类型杂质扩散区，由此形成具有第一超结结构的漂移区，在所述超结结构中，所述第一导电类型杂质扩散区和第二导电类型杂质扩散区沿着所述栅电极的栅宽度方向以恒定宽度的规则间隔交替布置；以及
将所述第一导电类型杂质离子注入到所述衬底的所述沟道区的两侧，由此沿着所述栅长度方向，在所述沟道区的一侧形成第一导电类型漏区并且在所述沟道区的另一侧形成第一导电类型源区。
8.根据权利要求7所述的制造半导体器件的方法，其中，所述形成所述第一导电类型源区和所述第一导电类型漏区进一步包括：
在所述衬底上方在整个表面上形成绝缘膜，并且将所述栅电极嵌入到所述绝缘膜中；
通过干法蚀刻对所述绝缘膜进行回蚀，由此沿着栅长度方向在所述栅电极的两侧形成侧壁，所述侧壁填充所述漂移区的所述第一导电类型杂质扩散区上的所述栅电极的所述梳齿之间的区域；以及
使用所述侧壁作为掩模，注入所述第一导电类型杂质离子，由此形成所述第一导电类型源区和所述第一导电类型漏区。
9.根据权利要求7所述的制造半导体器件的方法，所述半导体器件包括：高耐压区和低耐压区，在所述高耐压区中形成所述场效应晶体管，在所述低耐压区中形成第二场效应晶体管，所述第二场效应晶体管的耐压低于所述场效应晶体管的耐压，其中：
所述形成所述梳状的栅电极进一步包括：
在所述高耐压区中形成所述梳状的栅电极；以及
在所述低耐压区中形成第二栅电极；
所述形成所述漂移区进一步包括：
在所述低耐压区受第一抗蚀剂膜保护的状态下，在所述高耐压区中形成所述漂移区，所述第一抗蚀剂膜选择性地覆盖所述低耐压区，并且在所述高耐压区中开口；以及
在所述高耐压区受第二抗蚀剂膜保护的状态下，在所述低耐压区中，使用所述第二栅电极作为掩模，在所述低耐压区中形成的所述第二栅电极的两侧形成第一导电类型扩展区，所述第二抗蚀剂膜选择性地覆盖所述高耐压区，并且在所述低耐压区中开口；以及
所述形成所述第一导电类型漏区和所述第一导电类型源区进一步包括：在所述高耐压区中，将所述第一导电类型杂质离子注入到所述衬底的所述沟道区的两侧，由此形成所述漏区和所述源区，而同时在所述低耐压区中，将所述第一导电类型杂质离子注入到所述衬底的所述第二沟道区的两侧，由此形成第一导电类型漏区和第一导电类型源区。
10.根据权利要求9所述的制造半导体器件的方法，其中，所述形成所述第一导电类型漏区和所述第一导电类型源区进一步包括：
在所述衬底上方的整个表面上形成绝缘膜，并且将所述栅电极和所述第二栅电极嵌入到所述绝缘膜中；
通过干法蚀刻对所述绝缘膜进行回蚀，由此在所述高耐压区中沿着栅长度方向在所述栅电极的两侧形成侧壁，所述侧壁填充所述漂移区中所述第一导电类型杂质扩散区上的所述栅电极的所述梳齿之间的区域，以及由此在所述低耐压区中在所述第二栅电极的两侧形成侧壁；以及
使用各自侧壁作为掩模，将所述第一导电类型杂质离子注入到所述高耐压区和所述低耐压区中，由此形成所述第一导电类型漏区和所述第一导电类型源区。
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CN102157559A (zh) * 2011-03-01 2011-08-17 北京大学 一种叉指型栅结构的低功耗隧穿场效应晶体管
CN102157559B (zh) * 2011-03-01 2012-05-02 北京大学 一种叉指型栅结构的低功耗隧穿场效应晶体管
WO2012116522A1 (zh) * 2011-03-01 2012-09-07 北京大学 一种叉指型栅结构的低功耗隧穿场效应晶体管
CN103165460A (zh) * 2011-12-16 2013-06-19 中芯国际集成电路制造(上海)有限公司 Ldnmos及ldpmos的制造方法
CN104037214A (zh) * 2014-06-26 2014-09-10 中国电子科技集团公司第十三研究所 改善短沟效应的栅控半导体器件
CN109273364A (zh) * 2015-02-13 2019-01-25 杰华特微电子（杭州）有限公司 一种半导体结构及其形成方法
CN107845675A (zh) * 2017-10-30 2018-03-27 济南大学 带有宽度渐变型场板的横向双扩散金属氧化物半导体场效应管

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