CN101641791B - 超结功率半导体器件 - Google Patents

超结功率半导体器件 Download PDF

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CN101641791B
CN101641791B CN2007800499130A CN200780049913A CN101641791B CN 101641791 B CN101641791 B CN 101641791B CN 2007800499130 A CN2007800499130 A CN 2007800499130A CN 200780049913 A CN200780049913 A CN 200780049913A CN 101641791 B CN101641791 B CN 101641791B
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丹尼尔·M·金策
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INT RECTIFIER CORP (SG)
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Abstract

一种超结功率半导体器件，其包括多个沟槽栅极(16，图1)和多个间隔的漂移区域(32)，各漂移区域从各自的栅极槽(14)延伸至作为漏极的基板(10)，并且仅沿着栅极槽(14)的侧壁的一部分延伸。

Description

超结功率半导体器件
相关申请的交叉引用
本申请基于2007年1月24日提交的美国专利申请No.11/657,150并要求其优先权，所述申请要求2006年1月24日提交的题为“SuperjunctionDevice”的美国专利临时申请No.60/761,701的优先权，将这两件申请的内容通过引用并入此处。
技术领域
本发明涉及半导体器件，具体地涉及具有超结结构的功率半导体开关。
背景技术
超结MOS门器件通常包括多个隔开的一种导电类型的柱或条，这些柱或条垂直地延伸进入作为漂移区的另一种导电类型的硅主体中。MOS门结构使源极电压与相对于主体的这些柱或条相连，该主体与漏极电压相连。在超结结构中，通过周围硅主体中的电荷使柱或条中的总电荷至少接近于平衡。因而，主体区域和柱或条在反向偏置中被完全耗尽以阻挡反向电压。与传统的MOSFET相比，主体中掺杂剂的浓度被增大(降低其电阻率)，从而在正向偏置的过程中，降低了导通电阻。
发明内容
本发明的半导体器件包括：一种导电类型的半导体基板；在所述基板表面上的另一种导电类型的外延的半导体主体；外延的半导体主体中的栅极槽；一种导电类型的漂移区域，其从所述槽的至少底部延伸至基板，并且仅沿着所述栅极槽的侧壁的一部分延伸，所述一种导电类型的漂移区域与所述外延半导体主体处于电荷平衡；一种导电类型的源极区域，其与所述栅极槽相邻地形成于所述外延半导体主体中，并且通过与所述槽相邻的可反转的沟道区域与所述一种导电类型的漂移区域隔开；至少与所述源极区域电阻性接触的源极接触部；与所述基板电阻性接触的漏极接触部。
在本发明的一个实施例中，所述漂移区域延伸进所述基板中。
在本发明的另一个实施例中，所述漂移区域包括与所述基板相邻的高电阻率区域和与所述栅极槽相邻的低电阻率区域。
本发明的器件具体适用于中压应用，例如大约50伏至100伏。
根据以下参照附图的本发明的说明中，本发明的其它特点和优点将是更加清楚。
附图说明
图1示出了本发明第一实施例的功率半导体器件的有源区域的一部分的横剖面图。
图2示出了本发明第二实施例的功率半导体器件的有源区域的一部分的横剖面图。
图3示出了沿图2的3-3线在箭头的方向上所视的横剖面图。
具体实施方式
参照图1，本发明第一实施例的功率半导体器件优选地是功率MOSFET，其包括一种导电类型(例如N型)的半导体基板(例如硅基板)10，以及形成于基板10的表面上的与所述的一种导电类型相反的另一种导电类型(例如P型)的外延半导体主体12(即外延生长的半导体主体)。多个隔开的栅极槽14形成于外延半导体主体12中，每个栅极槽14用于容纳各自的优选地由N型多晶硅形成的栅极16。各栅极16通过各自的氧化物主体18(例如SiO2)与外延主体12绝缘。各氧化物主体18包括与各栅极槽的底部和侧壁部分相邻的厚氧化物部分20，以及与外延主体12中的可反转的沟道区域相邻的栅极氧化物部分22(比厚氧化物部分薄)。一种导电类型(例如N型)的源极区域24与各栅极槽相邻地形成于外延主体12中，且与源极接触部28电阻性耦接，源极接触部28可由铝、硅铝合金等材料形成。应当指出，氧化物覆盖部31使源极接触部28与各栅极16绝缘。源极接触部28还电阻性地耦接至也形成于外延主体12中的另一种导电类型(例如P型)的高电导率区域26。众所周知，高电导率区域26比外延主体12更易导电，从而提供了至源极接触部28的低接触电阻。第一实施例的器件还包括漏极接触部30(例如由铝或硅铝合金形成)，该漏极接触部30与源极接触部28相对地电阻性地连接到基板10。
根据本发明的一方面，一种导电类型(例如N型)的漂移区域32形成于(例如通过注入等类似步骤)外延主体12中，并且从各栅极槽14的底部至少延伸至基板10。应当指出，各漂移区域32还沿着各栅极槽的侧壁延伸，直到至少到达在栅极槽的每一侧的可反转的沟道区域(该沟道区域被定义为在源极24和漂移区域32之间靠近各栅极槽侧壁的区域，一旦给最近的栅极16施加电压，该沟道区域就反转)。各漂移区域32与其周围环境(相反的导电类型)基本上处于电荷平衡状态，从而实现如上所述的超结效应。优选地，各漂移区域32的一部分延伸进基板10中。应当指出，各漂移区域32相互隔开，并且通过外延主体12的P型区域彼此隔开。即，各漂移区域32彼此不直接耦接，而只通过基板10耦接。因此，保持外延主体12的主要体积和其中所含的电荷以实现超结效应，同时，即使漂移区域32中的电荷可能增加，但可使漂移区域32所占的体积最小化以改善器件的导通电阻。
应当指出，在本发明的器件中，漂移区域32形成于外延主体12中。因而，可以通过适当地选择注入浓度控制漂移区域32的电导率，该漂移区域32的电导率控制器件的导通电阻。另一方面，在现有技术的超结器件中，漂移区域是外延生长的，并且通过注入等类似步骤在其中形成导电类型相反的区域。还应当指出，在第一实施例的器件中，外延主体12用作沟道区域，从而免除了通过注入等类似步骤形成沟道区域的需要。
第一实施例的器件的拓扑结构是蜂窝状的或条状的，并且其蜂窝间距约为2微米。对于75伏的器件，外延主体12可以是5微米厚。应当指出，可颠倒所有的导电类型以制成P沟道器件，而不是上述的N沟道器件。
现在参照图2和图3，其中相同的附图标记表示相同的部件，在本发明第二实施例的器件中，漂移区域32包括与基板10相邻的高电阻率区域34(例如3千欧)和与槽14相邻的低电阻率区域36(例如4千欧)。类似于第一实施例，漂移区域32从与栅极氧化物22相邻的可反转的沟道区域延伸至基板10。应当指出，第二实施例的器件还包括与栅极氧化物22相邻的另一种导电类型(例如P型)的沟道注入物38，并且各高电导率区域26在其中具有槽以改善源极接触部28与高电导率区域26和源极区域24的接触。应当指出，沟道注入物38通过外延主体12彼此隔开。优选地，第二实施例的器件具有具体如图3所示的蜂窝状拓扑结构。
为了使用第二实施例的布置获得75伏的器件，对应于6.5E16原子/cm2的浓度，外延主体12可形成为具有大约0.25ohm·cm的电阻率，并且可通过1×1017原子/cm3的浓度的砷注入形成高电阻率区域34。
尽管通过本发明的具体实施例说明了本发明，但本发明的其它变化、改变和其它应用对于本领域技术人员是显而易见的。因而，优选地，本发明并不被这里的具体公开内容所限制，而只由所附权利要求所限定。

Claims (7)

1.一种功率半导体器件，其包括：
一种导电类型的半导体基板；
在所述基板的表面上的另一种导电类型的外延半导体主体；
在所述的外延半导体主体中的栅极槽；
所述一种导电类型的漂移区域，其至少从所述栅极槽的底部延伸至所述基板，并且仅沿着所述栅极槽的侧壁的一部分延伸，所述一种导电类型的所述漂移区域与所述外延半导体主体处于电荷平衡；
所述一种导电类型的源极区域，其与所述栅极槽相邻地形成于所述外延半导体主体中，并且通过与所述栅极槽相邻的可反转的沟道区域与所述一种导电类型的漂移区域隔开；
与至少所述源极区域电阻性接触的源极接触部；和
与所述基板电阻性接触的漏极接触部，其中，所述漂移区域包括与所述基板相邻的高电阻率区域和与所述栅极槽相邻的低电阻率区域。
2.如权利要求1所述的功率半导体器件，其中，所述一种导电类型的漂移区域延伸进入所述基板中。
3.如权利要求1所述的功率半导体器件，还包括：
位于所述栅极槽中的氧化物主体，所述氧化物主体包括至少与所述可反转的沟道区域相邻的栅极氧化物部分以及与所述漂移区域相邻的加厚部分；
以及位于所述栅极槽中且与所述氧化物主体相邻的栅极。
4.如权利要求1所述的功率半导体器件，还包括所述另一种导电类型的高电导率区域，其形成于所述外延半导体主体中并且与所述源极接触部电阻性接触。
5.如权利要求3所述的功率半导体器件，其中，所述栅极由多晶硅制成。
6.如权利要求5所述的功率半导体器件，其中，所述多晶硅为N型。
7.如权利要求1所述的功率半导体器件，其中，所述一种导电类型为N型，并且所述另一种导电类型为P型。
CN2007800499130A 2007-01-24 2007-04-13 超结功率半导体器件 Active CN101641791B (zh)

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US11/657,150 2007-01-24
US11/657,150 US7492003B2 (en) 2006-01-24 2007-01-24 Superjunction power semiconductor device
PCT/US2007/009038 WO2008091269A1 (en) 2007-01-24 2007-04-13 Superjunction power semiconductor device

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JP2010517288A (ja) 2010-05-20
EP2108194A4 (en) 2010-09-15
US7492003B2 (en) 2009-02-17
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TW200832701A (en) 2008-08-01
TWI340468B (en) 2011-04-11
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US20090218617A1 (en) 2009-09-03

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