CN101592696A - Sensor base plate and testing fixture - Google Patents

Abstract

Provide a kind of and can improve sensor base plate and the testing fixture of checking degree of accuracy.The present invention relates to a kind of sensor base plate, this sensor base plate be with the noncontact form and can electromagnetic coupled ground with check the opposed sensor base plate of object substrate, have the sensor electrode that is arranged and the signal acquisition of each sensor electrode is amplified at least with each sensor electrode corresponding sensor circuit, wherein, above-mentioned inspection object substrate is a substrate of checking that the object electrode is aligned to array-like and can drives by each row.The amplifying circuit that is arranged in each sensor circuit replaces to the resistive element in the source ground amplifying circuit diode transistor block that connection in series-parallel connects limited diode unipolar transistor respectively, wherein, above-mentioned diode unipolar transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode.

Description

Sensor base plate and testing fixture

Technical field

The present invention relates to a kind of sensor base plate and testing fixture, for example, the sensor base plate that can be applied in the inspection of the substrate for display as the glass substrate of display panels, to use, with the testing fixture of this sensor base plate as inscape.

Background technology

Substrate for display for example is the glass substrate that possesses a plurality of compositions in a plurality of substrate for display zone that is divided into display panels respectively on a face.As shown in figure 39,1 array-like ground, each substrate for display zone has a plurality of pixel regions (promptly, zone, unit (cell)), and these a plurality of pixel regions possess the pixel electrode 2 of rectangle respectively and are connected on-off element 3 on this pixel electrode 2.

Each pixel electrode 2 is electrodes of the film like parallel with substrate for display 1, for example has the flat shape of rectangle, and this rectangle has the size roughly the same with corresponding pixel region.Each on-off element 3 is the field effect type thin film transistor (TFT)s (TFT) that for example have source electrode, drain electrode and grid, and drain electrode (or source electrode) is connected on the corresponding pixel electrode 2.Grid at the on-off element of arranging on the directions X 3 is connected on the common grid distribution 4, is connected on the shared distribution 5 at the source electrode of the on-off element of arranging on the Y direction 3 (or drain electrode).

Voltage by control gate wirings 4 makes the on-off element 3 of institute's respective column be conducting state, with high-frequency signal the pixel electrode 2 of institute's respective column is discharged and recharged etc. by distribution 5 being applied test, thus can detector switch element 3, the opening circuit etc. of gate wirings 4, distribution 5.For example on directions X (row), be set up in parallel 7168 pixel electrodes 2, carry out the inspection of opening circuit etc. according to every row.One row of directions X for example have the length that is slightly larger than 25cm.

In patent documentation 1, record and make sensor base plate with non-contacting mode and the opposed testing fixture of checking of row of checking object pixels electrode 2.

Figure 40 illustrates the summary structure of this testing fixture, and Figure 41 illustrates the summary plane of sensor base plate.

With the opposed one to one sensor electrode 7 of pixel electrode 2 to arrange identical spacing arrangement on sensor base plate 6 with the directions X of pixel electrode 2.Check as follows: make sensor base plate 6 to the close noncontact distance of the row of checking object pixels electrode 2 to pixel electrode 2 and corresponding sensor electrode 7 electromagnetic coupled degree, sensor electrode 7 picks up the signal that comes out from pixel electrode 2 radiation (above-mentioned test with high-frequency signal etc.), by corresponding sensor circuit 8 (with reference to Fig. 8 of patent documentation 1) amplify, after the rectification etc., existence by flat cable 10 confirmation signal in test department 11 etc.Sensor circuit 8 comprises amplifying circuit, can also attach rectification circuit etc.

Testing fixture 12 possesses the row of inspection changeable mechanism 13, under the control of control part 14, according to the spacing of the Y direction of pixel electrode 2 while each row that substrate for display 1 and sensor base plate 6 is relatively moved off and on check successively pixel electrode 2, wherein, above-mentioned inspection row changeable mechanism 13 keeps substrate for display 1 and sensor base plate 6 noncontacts, and relatively carries substrate for display 1 and sensor base plate 6.

For example, as mentioned above, be set up in parallel 7168 pixel electrodes 2 on the length of 25cm being slightly larger than, therefore being formed on sensor circuit 8 on the sensor base plate 6 for example also needs to be set up in parallel 7168 on the length of 25cm being slightly larger than.Therefore, the amplifying circuits that are made of in the sensor circuit 8 SOG (polysilicon) are practical, and to require this amplifying circuit be as follows: to need this amplifying circuit be high input impedance in order to become small capacitance coupling input; A plurality of in order to dispose side by side, even need to exist the deviation of element characteristic, the supply voltage that is caused by the resistance of the long power lead that is slightly larger than 25cm to descend, deviation does not appear in amplification characteristic (gain, output bias etc.) yet; Needing the side circuit area under the ICization situation is small size.For example studying source ground amplifying circuit shown in Figure 42 is being utilized in each amplifying circuit.

In Figure 42, source ground amplifying circuit 20 constitutes and connect negative feedback source resistance Rs between the source electrode of amplifying mos transistor M 1 and negative supply Vee, between the drain electrode of MOS transistor M1 and positive supply Vdd, connect pull-up resistor RL, with the drain electrode link of the amplifying mos transistor M1 of pull-up resistor RL lead-out terminal Vo as this source ground amplifying circuit 20, wherein, above-mentioned amplifying mos transistor M1 is connected grid on the input terminal Vi of this source ground amplifying circuit 20.The input terminal Vi of source ground amplifying circuit 20 is connected on the output Vso of signal source 22.Figure 42 is considered as the signal that above-mentioned sensor electrode 7 is picked up from the signal of signal source 22 and the figure of signal source 22 is shown with equivalent electrical circuit.Signal source 22 is constructed as follows: be connected in series input direct current biasing power supply Vidc and input exchange signal source Vs, with an end ground connection of this series circuit, export Vso with the other end as signal source.In addition, also among the input direct current biasing power supply Vidc of positive supply Vdd, negative supply Vee, signal source 22 any can be connected on the 0V (that is ground wire).

Because the grid of the MOS transistor M1 of source ground amplifying circuit 20 is the input terminal Vi of source ground amplifying circuit 20, therefore on this input terminal Vi, there is not electric current to flow through.

On the other hand, the DC current of the value that the DC potential difference between input terminal Vi and the negative supply Vee obtains with source resistance Rs sum divided by DC source electrode resistance and the negative feedback of MOS transistor M 1 flows through source electrode and the drain electrode of MOS transistor M1, and the alternating current (marking current) of the value that the voltage of input exchange signal source Vs obtains with source resistance Rs sum divided by interchange source impedance and the negative feedback of MOS transistor M1 flows through this source electrode and the drain electrode of MOS transistor M1.

And the product of this drain electrode alternating current (output signal electric current) and pull-up resistor RL is an output voltage.

By more than, when the interchange source impedance of establishing MOS transistor M1 is RM1s, represent voltage gain A with formula (1), this voltage gain A is that the input impedance of late-class circuit that is connected in the output Vo of source ground amplifying circuit 20 is the voltage gain under the infinitely-great situation.

A＝RL/(RM1s+Rs) (1)

Under the situation of RM1s ≈ Rs, the deviation of the source impedance RM1s of amplifying mos transistor M1 is directly connected to the deviation of gain.

At this, formula (2) is set up if RM1s compares enough little with Rs, but can not ignore RM1s usually, thereby handles with formula (1).

A≈RL/Rs (2)

Patent documentation 1: TOHKEMY 2007-248202 communique

Summary of the invention

The problem that invention will solve

Yet, the voltage gain of usefulness formula (1) expression of source ground amplifying circuit 20 in the past, wait and make sensor base plate 16 and make resistance ratio unanimity in the circuit even use the ICization technology, also produce deviation owing to the source impedance RM1s of amplifying mos transistor M1 and resistance R s, RL change independently of each other.

In addition, when establishing action current and be I, the source impedance RM1s of amplifying mos transistor M1 with Change, pull-up resistor RL and negative feedback change with 1/I with source resistance Rs.Thereby, decide voltage gain with pull-up resistor RL and negative feedback with the ratio of source resistance Rs in order to ignore source impedance RM1s, need reduce action current I.

When reducing action current I and increase pull-up resistor RL and negative feedback with source resistance Rs, it is big that the time constant of the electric capacity between the drain and gate of these resistance R s, RL and amplifying mos transistor M1 etc. becomes, thereby high frequency characteristics variation as amplifying circuit, and, under the situation of carrying out ICization, big resistance increases chip area.

Therefore, as the amplifying circuit that carries on sensor base plate 6, the amplifying circuit that requirement is achieved as follows: the action current with the high frequency characteristics that can guarantee amplifying circuit moves, amplifying deviation with transistorized source impedance (amplification with the deviation of transistorized threshold voltage) does not influence the deviation of voltage gain, and linear characteristic is good.

A plurality of source ground amplifying circuits 20 in the past are connected in parallel between the same power lead needing on the sensor base plate 6.In this case, the supply voltage that is positioned at away from the source ground amplifying circuit 20 of the position of power electrode owing to the resistance of the electric current of power lead and this power lead descends, thereby is positioned at the voltage gain change of the source ground amplifying circuit 20 of described position.That is, according to the position that is arranged on the sensor base plate 6, even realize the source ground amplifying circuit 20 of same structure, voltage gain also dissimilates.

Therefore, as the amplifying circuit that carries on sensor base plate 6, require the amplifying circuit that is achieved as follows: even the decline of this supply voltage takes place, voltage gain does not change yet, and linear characteristic is good.

In the SOG technology of having deposited, there is not resistance to generate operation, if use the source ground amplifying circuit 20 that comprises resistive element in the amplifying circuit in sensor circuit, then need to increase resistance and generate operation, mask increases, operation increases, and the result is that the cost of sensor base plate increases.

Therefore, as the amplifying circuit that carries on sensor base plate 6, require to realize not use resistive element and constitute and amplifying circuit that linear characteristic is good.

That is, require the sensor base plate, the testing fixture that are achieved as follows: carry the better amplifying circuit of characteristic geometric ratio amplifying circuit in the past, consequently can carry out than the more inspection of pinpoint accuracy in the past.

The scheme that is used to deal with problems

First the present invention is a kind of sensor base plate, this sensor base plate be with the noncontact form and can electromagnetic coupled ground with check the opposed sensor base plate of object substrate, have the sensor electrode that is arranged and the signal acquisition of each sensor electrode is amplified at least with each sensor electrode corresponding sensor circuit, wherein, above-mentioned inspection object substrate is a substrate of checking that the object electrode is aligned to array-like and can drives by each row, this sensor base plate is characterised in that, the amplifying circuit that is arranged in each the sensor circuit possesses respectively: (1) amplifies unipolar transistor, and it is with the input terminal of grid as this amplifying circuit; (2) negative feedback source impedance is with the diode transistor block, its connection in series-parallel connects limited (comprising 0) diode unipolar transistor and constitutes, be connected the source side of above-mentioned amplification unipolar transistor, wherein, above-mentioned diode unipolar transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode; (3) load is with the diode transistor block, its connection in series-parallel connects limited diode unipolar transistor and constitutes, be connected the drain side of above-mentioned amplification unipolar transistor, wherein, above-mentioned diode unipolar transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode; And (4) voltage output end, it is connected on the drain electrode side of above-mentioned load with the above-mentioned amplification unipolar transistor of diode transistor block, wherein, (5) amplifying circuit that will be arranged in each the sensor circuit is made as following structure: voltage gain by the source impedance of above-mentioned amplification unipolar transistor and above-mentioned negative feedback source impedance with the impedance of the impedance sum of diode transistor block and above-mentioned load ratio decision with the impedance of diode transistor block.

Second the present invention is a kind of sensor base plate, this sensor base plate be with the noncontact form and can electromagnetic coupled ground with check the opposed sensor base plate of object substrate, have the sensor electrode that is arranged and the signal acquisition of each sensor electrode is amplified at least with each sensor electrode corresponding sensor circuit, wherein, above-mentioned inspection object substrate is a substrate of checking that the object electrode is aligned to array-like and can drives by each row, this sensor base plate is characterised in that, the amplifying circuit that is arranged in each the sensor circuit possesses respectively: (1) first, the second differential amplification unipolar transistor, it is a side grid normal phase input end as this amplifying circuit, and with the opposing party's grid negative-phase input as this amplifying circuit; (2) suction-type constant current source, it makes the source current of above-mentioned first, second differential amplification unipolar transistor and is steady current; (3) first, second negative feedback source impedance is with the diode transistor block, its connection in series-parallel connects limited (comprising 0) diode transistor and constitutes, be connected the source side of above-mentioned first, second differential amplification unipolar transistor, wherein, above-mentioned diode transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode; (4) first, second load is with the diode transistor block, its connection in series-parallel connects limited diode transistor and constitutes, be connected the drain side of above-mentioned first, second differential amplification unipolar transistor, wherein, above-mentioned diode transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode; And (5) are as above-mentioned first, second load is with above-mentioned first of the diode transistor block, one side's of the drain electrode side of the second differential amplification unipolar transistor positive output end and as the opposing party's negative lead-out terminal, wherein, (6) will be arranged on the interior amplifying circuit of each the sensor circuit and be made as following structure: voltage gain is by above-mentioned first, each source impedance of the second differential amplification unipolar transistor and above-mentioned first, the second negative feedback source impedance with each impedance of diode transistor block each and impedance and above-mentioned first, second load decides with the ratio of each impedance of diode transistor block.

The 3rd the present invention is a kind of sensor base plate, this sensor base plate be with the noncontact form and can electromagnetic coupled ground with check the opposed sensor base plate of object substrate, have the sensor electrode that is arranged and the signal acquisition of each sensor electrode is amplified at least with each sensor electrode corresponding sensor circuit, wherein, above-mentioned inspection object substrate is a substrate of checking that the object electrode is aligned to array-like and can drives by each row, this sensor base plate is characterised in that, the amplifying circuit that is arranged in each the sensor circuit possesses respectively: (1) differential enlarging section, it has: (1-1) first, the second differential amplification unipolar transistor, it is a side grid normal phase input end as this amplifying circuit, and with the opposing party's grid negative-phase input as this amplifying circuit; (1-2) first, second negative feedback source resistance, it is connected the source side of above-mentioned first, second differential amplification unipolar transistor; (1-3) first, second pull-up resistor, it is connected the drain side of above-mentioned first, second differential amplification unipolar transistor; And (1-4) as a side's of the drain electrode side of above-mentioned first, second differential amplification unipolar transistor of above-mentioned first, second pull-up resistor positive output end and as the opposing party's negative lead-out terminal; (2) adjunct circuit, it has first, second source follower unipolar transistor that grid is connected to above-mentioned positive output end and above-mentioned negative lead-out terminal; (3) suction-type constant current source, it makes the source current of above-mentioned first, second differential amplification unipolar transistor and is steady current; And (4) power level displacement diode transistor, it makes the power level displacement to above-mentioned differential enlarging section, wherein, (5) export the function of dc offset voltage compensation to the change of the additional threshold voltage to the unipolar transistor in above-mentioned differential enlarging section and the above-mentioned adjunct circuit of above-mentioned suction-type constant current source and above-mentioned power level displacement diode transistor.

The 4th the present invention is a kind of testing fixture, make sensor base plate with the noncontact form and can electromagnetic coupled ground with check that object substrate is opposed, make the inspection object electrode and the sensor electrode electromagnetic coupled on the sensor substrate of any row of above-mentioned inspection object substrate check above-mentioned inspection object substrate, wherein the sensor substrate have the sensor electrode that is arranged and the signal acquisition of each sensor electrode is amplified at least with each sensor electrode corresponding sensor circuit, above-mentioned inspection object substrate is a substrate of checking that the object electrode is aligned to array-like and can drives by each row, this testing fixture is characterised in that, as the sensor substrate, used any sensor base plate among first～the 3rd the present invention.

The effect of invention

According to the present invention, can guarantee high input impedance, alleviate by the deviation of the threshold value of unipolar transistor, power lead resistance supply voltage and descend and the deviation and the output dc offset voltage deviation of the gain amplifier of the amplifying circuit that causes, the amplifying circuit of the side circuit area small sizeization in the time of can making ICization by using can provide and can improve sensor base plate and the testing fixture of checking degree of accuracy.

Description of drawings

Fig. 1 is the circuit diagram of the structure of the related source ground amplifying circuit of expression first embodiment.

Block diagram when Fig. 2 is the related source ground amplifying circuit of multistage connection first embodiment of expression.

Fig. 3 is the circuit diagram of the structure of the related source ground amplifying circuit of expression second embodiment.

Fig. 4 is the circuit diagram of the structure of the related amplifying circuit of expression the 3rd embodiment.

Fig. 5 is the circuit diagram of the structure of the related differential amplifier circuit of expression the 4th embodiment.

Fig. 6 be the expression multistage connection the 4th embodiment differential amplifier circuit the time block diagram.

Fig. 7 is the circuit diagram of the structure of the related differential amplifier circuit of expression the 5th embodiment.

Fig. 8 is the circuit diagram of the structure of the related amplifying circuit of expression the 6th embodiment.

Fig. 9 is the circuit diagram of the structure of the related amplifying circuit of expression the 7th embodiment.

Figure 10 is the circuit diagram of the structure of the related amplifying circuit of expression the 8th embodiment.

Figure 11 is the circuit diagram of the structure of the related amplifying circuit of expression the 9th embodiment.

Figure 12 is the circuit diagram of the structure of the related amplifying circuit of expression the tenth embodiment.

Figure 13 be the expression multistage connection the tenth embodiment amplifying circuit the time block diagram.

Figure 14 be expression the tenth embodiment the distortion embodiment (one of) circuit diagram of the structure of related amplifying circuit.

Figure 15 is the circuit diagram of the structure of the related amplifying circuit of the distortion embodiment (two) of expression the tenth embodiment.

Figure 16 is the circuit diagram of the structure of the related amplifying circuit of expression the 11 embodiment.

Figure 17 is the circuit diagram of the structure of the related amplifying circuit of expression the 12 embodiment.

Figure 18 be expression the 12 embodiment the distortion embodiment (one of) circuit diagram of the structure of related amplifying circuit.

Figure 19 is the circuit diagram of the structure of the related amplifying circuit of the distortion embodiment (two) of expression the 12 embodiment.

Figure 20 is the circuit diagram of the structure of the related amplifying circuit of expression the 13 embodiment.

Figure 21 be expression the 13 embodiment the distortion embodiment (one of) circuit diagram of the structure of related amplifying circuit.

Figure 22 is the circuit diagram of the structure of the related amplifying circuit of the distortion embodiment (two) of expression the 13 embodiment.

Figure 23 is the circuit diagram of the structure of the related amplifying circuit of expression the 14 embodiment.

Figure 24 is the circuit diagram of the structure of the related amplifying circuit of expression the 15 embodiment.

Figure 25 is the circuit diagram of the structure of the related amplifying circuit of expression the 16 embodiment.

Figure 26 is the circuit diagram of the structure of the related amplifying circuit of expression the 17 embodiment.

Figure 27 be the expression signal source other structures (one of) circuit diagram.

Figure 28 is the circuit diagram of other structures (two) of expression signal source.

Figure 29 is the circuit diagram of other structures (three) of expression signal source.

Figure 30 is the circuit diagram of other structures (four) of expression signal source.

Figure 31 is the circuit diagram of other structures (five) of expression signal source.

Figure 32 is the circuit diagram of other structures (six) of expression signal source.

Figure 33 is the circuit diagram of other structures (seven) of expression signal source.

Figure 34 is the circuit diagram of other structures (eight) of expression signal source.

Figure 35 is the circuit diagram of other structures (nine) of expression signal source.

Figure 36 is the circuit diagram of other structures (ten) of expression signal source.

Figure 37 is the circuit diagram of other structures of expression current mirroring circuit.

Figure 38 is the circuit diagram of other structures of expression suction-type constant current source.

Figure 39 is the key diagram of substrate for display.

Figure 40 is the block diagram of summary structure that expression utilizes the testing fixture of sensor base plate.

Figure 41 is the summary planimetric map of the face with sensor electrode of expression sensor base plate.

Figure 42 is a circuit diagram of representing the structure of source ground amplifying circuit in the past.

Description of reference numerals

M1, M1a, M1b: amplifying mos transistor; M2a, M2b: cascade connects transistor (cascaded transistor); M3, M3a, M3b: source follower MOS transistor; MLs, MLs1, MLs2: power level displacement diode transistor; Mis, Misa, Misb: constant current source output mos transistor; Mis1: steady current is set the diode MOS transistor; Miss: constant current source level shift MOS transistor; Mm1～Mm3: mirror currents output mos transistor; Cp: high-frequency compensation electric capacity; CL: high-frequency cut-off electric capacity; Ch: voltage keeps electric capacity; RLa, RLb: pull-up resistor; Rs, Rsa, Rsb: negative feedback source resistance; Rss, Rssa, Rssb: steady current is set resistance; Rsss: the second benchmark steady current is set resistance; Iss: constant current source level shift transistor biasing constant current source; Ida, Idb: source follower load constant current source; VpL: switch drive pulse signal source; Sw: on-off circuit; 1: substrate for display; 2: pixel electrode; 6: sensor base plate; 7: sensor electrode; 8: sensor circuit; 12: testing fixture; 22: signal source; 25: the differential wave source; 30,30A, 30B: source ground amplifying circuit; 31,41a, 41b: source impedance is with the diode transistor block; 32,42a, 42b: load is with the diode transistor block; 33,43a, 43b: current mirroring circuit; 34: source follower/rectification circuit; 40,51,51A, 51B: differential amplifier circuit; 44,44B: source follower circuit; 50,50A, 50B, 60,60A, 60B, 60C, 70,70A, 70B, 80A, 80B, 80C, 90～93: amplifying circuit; 52,52A, 72,72A: differential enlarging section; Is, 53,53A, 53B, 73,73B: suction-type constant current source; 61,61B: full-wave rectifying circuit; 62: the peak holding circuit that band resets; 74: the suction-type steady current is set with the diode transistor block; 75: the benchmark steady current is set with the diode transistor block.

Embodiment

(A) first embodiment

Below, with reference to first embodiment of description of drawings according to sensor base plate of the present invention and testing fixture.

(A-1) structure of first embodiment

Its summary structure of the sensor base plate of first embodiment and testing fixture is also identical with Figure 40, sensor base plate in the past and testing fixture shown in Figure 41.But, be arranged on amplifying circuit in the sensor circuit 8 with different in the past.

Fig. 1 is the circuit diagram of the structure of the related source ground amplifying circuit of expression first embodiment, and, corresponding Reference numeral same for the part additional phase identical, corresponding with the accompanying drawing of having narrated represented.

In Fig. 1, the source ground amplifying circuit 30 of first embodiment has: amplify MO S transistor M 1, negative feedback source impedance with diode transistor block (below be called source impedance with diode transistor block) 31, load with diode transistor block 32.

Replace negative feedback in the source ground amplifying circuit (with reference to Figure 42) in the past source impedance to be set with diode transistor block 31 with source resistance Rs.Source impedance is that connection in series-parallel connects limited (comprising 0) diode transistor and obtains with diode transistor block 31, and wherein, above-mentioned diode transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode.A diode transistor only is shown in Fig. 1, under plural situation, can be connected in series them, also can be connected in parallel them, and, these series circuits that also can after forming a plurality of series circuits, be connected in parallel, these parallel circuits can also be connected in series after forming a plurality of parallel circuits, the transistorized method of attachment of a plurality of diodeizations is arbitrarily, in this manual this method of attachment arbitrarily is called " connection in series-parallel connection ".

Replace the pull-up resistor RL in the source ground amplifying circuit (with reference to Figure 42) in the past and load is set with diode transistor block 32.Load is that connection in series-parallel connects limited diode transistor and constitutes with diode transistor block 32, and wherein, above-mentioned diode transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode.

Following structure shown in Figure 1: as source impedance with diode transistor block 31, between the source electrode of amplifying mos transistor M1 and negative supply Vee, be connected a diode transistor Ms, with diode transistor block 32, five diode transistor ML1～ML5 are connected in series between the drain electrode of amplifying mos transistor M1 and positive supply Vdd as load.

With load with the drain electrode link of the amplifying mos transistor M1 of diode transistor block 32 lead-out terminal Vo as the source ground amplifying circuit of first embodiment.

(A-2) action of first embodiment

As the action of the sensor base plate and the testing fixture of first embodiment, identical with the action of in the past sensor base plate and testing fixture.

The source ground amplifying circuit 30 of first embodiment replaces the negative feedback in the past the source ground amplifying circuit (with reference to Figure 42) to be provided with source impedance with source resistance Rs with diode transistor block 31, replace the pull-up resistor RL in the source ground amplifying circuit in the past and be provided with load with diode transistor block 32, the elemental motion of the source ground amplifying circuit 30 of first embodiment is identical with the action of source ground amplifying circuit in the past, therefore omits its explanation.

Can with the negative feedback of above-mentioned formula (1) with source resistance Rs replace with the negative feedback source impedance with the impedance of diode transistor block 31, pull-up resistor RL replaced with load come the calculated gains characteristic with the impedance of diode transistor block 32.

When the source impedance of establishing amplifying mos transistor M1 is RM1s, source impedance is RMs with the transistorized impedance of each diodeization in the diode transistor block 31, it is m (=1) that source impedance connects number with the transistor series in the diode transistor block 31, load is RML with the transistorized impedance of each diodeization in the diode transistor block 32, it is that n (=5) is when replacing each parameter of above-mentioned formula (1) that load connects numbers with the transistor series in the diode transistor block 32, can draw voltage gain A by through type (3), this voltage gain A is that the input impedance of late-class circuit of output that is connected in the source ground amplifying circuit 30 of first embodiment is the voltage gain under the infinitely-great situation.

A＝RML×n/(RM1s+RMs×m) (3)

At this, if (grid width and the grid length of Ms, ML1～ML5) are identical with the transistor of diode transistor block 32 with diode transistor block 31 and load with constituting source impedance to be made as amplifying mos transistor M1, RML=RMs ≈ RM1s then, therefore, can draw formula (4) from formula (3).

A≈n/(1+m) (4)

As seen from formula (4), when n＞(1+m), voltage gain A is greater than 1, thereby becomes the voltage amplification action.In addition, as can be known in that transistorized series circuit constitutes source impedance respectively with diode transistor block 31 and load under the situation with diode transistor block 32 with diodeization, by selected be connected in series number m, n can the assigned voltage gain A.

Under the identical condition of each above-mentioned transistor size, input direct current biasing power supply Vidc among potential difference (PD) between the dc offset voltage of the output Vo of positive supply Vdd and source ground amplifying circuit 30 and the input voltage Vi that is included in source ground amplifying circuit 30 is identical with formula (4) with the ratio of the potential difference (PD) between the negative supply Vee, therefore, as long as the voltage of input direct current biasing power supply Vidc does not change, even (the threshold voltage vt change of Ms, ML1～ML5), the dc offset voltage of the output Vo of source ground amplifying circuit does not change MOS transistor yet.

Usually, when the grid width of establishing MOS transistor is that W, grid length are that L, grid and voltage between source electrodes are that Vgs, threshold voltage are Vt and when proportionality constant k is set, the drain current I when representing saturated action (* * 2 expression quadratic powers) with formula (5).

I≈(kW/L)×(Vgs-Vt)**2 (5)

If formula (5) is carried out partial differential, then obtain transfer admittance (transferconductance) Gm with Vgs.The inverse of this transfer admittance Gm is a source impedance.

When the grid width of establishing amplifying mos transistor M1 is that Ws1, grid length are Ls1 and when new proportionality constant K is set, with the source impedance RM1s of formula (6) expression amplifying mos transistor M1.

$\mathrm{RM}1s\&ap;(K/\sqrt{I})\&times;\sqrt{(\mathrm{<figure-callout\; id="1"\; label="Ls"\; filenames="A2009101423310086H1.png,A2009101423310088H1.png"\; state="\{\{state\}\}">Ls</figure-callout>}1/\mathrm{Ws}1)}---\left(6\right)$

Become diode if connect the grid of amplifying mos transistor M1 and drain electrode, then the value calculated of through type (6) is the diode impedance.

Equally, be Ws when establishing the grid width of source impedance with the MOS transistor Ms in the diode transistor block 31, when grid length is Ls, represent the diode impedance RMs of this MOS transistor Ms with formula (7).In addition, similarly, be that WL, grid length are LL when establishing the grid width of load with the MOS transistor ML1 in the diode transistor block 32～ML5, represent the diode impedance RML of each transistor ML1～ML5 with formula (8).

$\mathrm{RMs}\&ap;(K/\sqrt{I})\&times;\sqrt{(\mathrm{Ls}/\mathrm{Ws})}---\left(7\right)$

$\mathrm{RML}\&ap;(K/\sqrt{I})\&times;\sqrt{(\mathrm{LL}/\mathrm{WL})}---\left(8\right)$

When the result with above formula (6)～(8) is updated to formula (3),

Be cancelled, thus the formula of obtaining (9), as can be known gain A be not subjected to each MOS transistor threshold voltage vt, bias current influence and become the ratio of the grid size and the number of each MOS transistor.

$A=n\&times;\sqrt{(\mathrm{LL}/\mathrm{WL})}/(\sqrt{(\mathrm{<figure-callout\; id="1"\; label="Ls"\; filenames="A2009101423310086H1.png,A2009101423310088H1.png"\; state="\{\{state\}\}">Ls</figure-callout>}1/\mathrm{Ws}1)}+m\&times;\sqrt{(\mathrm{Ls}/\mathrm{Ws})})---\left(9\right)$

For example, under the situation of the anti-phase output amplifier that has used operational amplifier, the negative feedback resistor of gain decision usefulness reduces the input impedance as amplifying circuit, but in the source ground amplifying circuit 30 of first embodiment, because input impedance is the grid input impedance of MOS transistor M1, therefore the input impedance as amplifying circuit can be maintained high impedance.

Above-mentioned diode impedance is each MOS transistor value in saturated when action, therefore, in can being considered as the actuating range that each MOS transistor is saturated action, always setting up in each moment formula (the 3)～formula (9) of AC signal input action, thereby guarantee linear characteristic and do not produce waveform distortion.

In addition, when obtaining greatly with diode transistor block 31 and load with the diode voltage in the diode transistor block 32 source impedance, change with respect to the threshold voltage vt of each MOS transistor, the change of action current I diminishes, and guarantees that the output voltage range of above-mentioned linear characteristic enlarges.

And, when as decide gain A with formula (4), the size of each MOS transistor being made as when identical, the ratio that is included in the potential difference (PD) between the direct current biasing of the voltage of the direct current biasing power supply Vidc in the input signal source and the potential difference (PD) between the negative supply Vee and positive supply Vdd and output voltage V o becomes identical, even transistorized threshold voltage vt change, the direct current biasing of output voltage V o does not change yet.

Under the situation that is applied to above-mentioned sensor base plate, only AC signal is taken into above-mentioned input terminal Vi by sensor with the form of small capacitance coupling, provides Dc bias to make source ground amplifying circuit action (for example, the form of application Figure 27 described later etc.) by high resistance (for example MOS resistance) to input terminal Vi from positive input direct current biasing power supply Vidc.

(A-3) effect of first embodiment

According to the source ground amplifying circuit 30 of first embodiment, can access following effect (a)～(i), consequently can carry out than the more inspection of pinpoint accuracy in the past according to the sensor base plate and the testing fixture of first embodiment.

The source ground amplifying circuit that (a) can be achieved as follows: gain be not subjected to each MOS transistor threshold voltage vt, MOS transistor action current influence and decide by the grid size of each MOS transistor and the ratio of transistor number.

For example, be set up in parallel on the length of 25cm under the situation 7168, that be formed on the amplifying circuit on the sensor base plate being slightly larger than, even in same IC chemical industry preface, generate the source ground amplifying circuit, also owing to the position on the sensor base plate makes the threshold voltage vt possibility of MOS transistor slightly different.But,, therefore can make the gain unanimity of the amplifying circuit that is set up in parallel because gain is not subjected to the influence of the threshold voltage vt etc. of each MOS transistor.

(b) input impedance is the grid input impedance of MOS transistor, therefore the input impedance as amplifying circuit can be maintained high impedance.

(c) use the diode impedance, in can being considered as the actuating range that each MOS transistor is saturated action, guaranteeing linear characteristic and do not produce waveform distortion.

(d) when make load with and the structure of the MOS transistor used of source impedance when consistent, from low frequency to the high frequency loaded impedance and the ratio of source side impedance do not change, from the low frequency to the high-frequency energy, access smooth gain characteristic.

(e) do not need as the operational amplification circuit from outputing to the loop negative-feedback circuit of input, therefore do not have the worry of vibration.

(f) owing to do not need therefore can set the bias voltage of input part and the bias voltage of efferent for value arbitrarily from outputing to the loop negative-feedback circuit of input.

(g) can constitute by the MOS transistor of the single type of N type (or P type), and for not using the circuit of resistive element, therefore under the situation of carrying out ICization, do not need any transistor of P type (or N type) to generate operation and resistance generation operation, thereby realize low manufacturing costization and casual labourer's phaseization.

(h) do not use to compare with MOS transistor and need large-area resistive element, therefore under the situation of having carried out ICization, comparing with the source ground amplifying circuit of in the past use resistive element can small sizeization (miniaturization).

(i) by with amplifying mos transistor M1 with constitute source impedance and be made as identical with the transistorized grid width and the grid length of diode transistor block 32 with diode transistor block 31 and load, and positive supply Vdd, the input direct current biasing power supply Vidc, the negative supply Vee that are included among the input voltage Vi of source ground amplifying circuit 30 are made as fixed value (not change), even can realize the source ground amplifying circuit that the dc offset voltage of the threshold voltage vt change output Vo of MOS transistor does not also change.

Shown in Fig. 2 signal, decide source ground amplifying circuit 30 plural parallel stages of first embodiment of structure of the ratio of the positive power terminal of each source ground amplifying circuit 30 and potential difference (PD) between the lead-out terminal Vo and the potential difference (PD) between input terminal Vi and the negative power source terminal to be connected between positive supply Vdd line and the negative supply Vee line with being made as ratio by the transistor number of each transistor block and size, if make the ratio of the negative power source terminal of the positive power terminal of each source ground amplifying circuit 30 and the power lead resistance till the positive supply Vdd splicing ear and each source ground amplifying circuit 30 and the power lead resistance till the negative supply Vee splicing ear, transistor number and big or small ratio consistent (making the ratio unanimity of power supply line length/power lead amplitude) with above-mentioned transistor block, then flowing through the electric current (from the electric current of positive supply Vdd) of drain electrode of MOS transistor M1 of this source ground amplifying circuit and the electric current (flowing to the electric current of negative supply Vee) that flows through source electrode equates, therefore, power line voltage till from positive supply Vdd splicing ear to the positive power terminal of each source ground amplifying circuit 30 descend with from the negative power source terminal of each source ground amplifying circuit 30 to negative supply Vee splicing ear till the ratio that descends of power line voltage, equate with the ratio of above-mentioned transistor number and size, thus, voltage till the lead-out terminal Vo from positive supply Vdd splicing ear to each source ground amplifying circuit 30 descend with from the input terminal Vi (being connected on the positive input direct current biasing power supply Vidc) of each source ground amplifying circuit 30 to negative supply Vee splicing ear till the ratio of voltage decline, equate with the ratio of above-mentioned transistor number and size, input terminal Vi is the grid of MOS transistor M1, on positive input direct current biasing power supply Vidc supply power line, there is not dc bias current to flow through, therefore, the current potential that is connected the input terminal Vi of each the source ground amplifying circuit 30 on this power lead is fixed, and the result is that the current potential of the lead-out terminal Vo of each source ground amplifying circuit 30 is retained as fixing.

Make each power lead resistance not influence ac gain if between the appropriate location of each power lead pars intermedia and ground wire, be connected power capacitor, then become the voltage gain result consistent with output offset voltage.

(B) second embodiment

Then, with reference to second embodiment of description of drawings according to sensor base plate of the present invention and testing fixture.The second embodiment only amplifying circuit in the sensor circuit 8 is different with first embodiment, below, the amplifying circuit in second embodiment is described.

Fig. 3 is the circuit diagram of the structure of the related source ground amplifying circuit of expression second embodiment, and, corresponding Reference numeral same to the part additional phase identical, corresponding with the drawing of having stated represented.

In Fig. 3, the related source ground amplifying circuit 30A of second embodiment constitute remove the amplifying mos transistor M1 in the related source ground amplifying circuit 30 of the first above-mentioned embodiment drain electrode with lead-out terminal Vo and load being connected with diode transistor block 32, and the additional P channel current mirror circuit 33 that common terminal is connected to positive supply Vdd, the drain electrode of amplifying mos transistor M1 is connected in the input of this current mirroring circuit 33, and between the output of current mirroring circuit 33 and the second negative supply Vee1, connect load with diode transistor block 32, with this load with diode transistor block 32 and the lead-out terminal Vo of link current mirroring circuit 33 as this source ground amplifying circuit 30A.

The concrete structure of P channel current mirror circuit 33 figure 3 illustrates an example for arbitrarily.Current mirroring circuit 33 constitutes as follows: each source electrode of P channel current mirror current reference MOS transistor Mpm and P channel current mirror electric current output mos transistor Mpm1 is connected is used as common terminal, the drain and gate of P channel current mirror current reference MOS transistor Mpm is connected the input terminal that is used as P channel current mirror circuit 33, grid is connected the lead-out terminal of the drain electrode of the P channel current mirror electric current output mos transistor Mpm1 on this input terminal as current mirroring circuit 33.

In the related source ground amplifying circuit 30A of second embodiment, drain electrode output current with amplifying mos transistor M1 in current mirroring circuit 33 turns back to the second negative supply Vee1 direction, change the direct current biasing current potential of the lead-out terminal Vo of source ground amplifying circuit 30A thus, and the polarity of the AC signal of this lead-out terminal Vo that reverses.

In the related source ground amplifying circuit 30A of second embodiment, can carry out electric current by P channel current mirror circuit 33 amplifies, if establish current amplification factor is k, and then load with the diode impedance RML of each the MOS transistor ML1～ML5 in the diode transistor block 32 is

Gain A is when current amplification factor k

Doubly.That is, be not with above-mentioned formula (9) but can enough formulas (10) represent the gain A of the source ground amplifying circuit 30A that second embodiment is related.

$A=\sqrt{k}\&times;n\&times;\sqrt{(\mathrm{LL}/\mathrm{WL})}/(\sqrt{(\mathrm{<figure-callout\; id="1"\; label="Ls"\; filenames="A2009101423310086H1.png,A2009101423310088H1.png"\; state="\{\{state\}\}">Ls</figure-callout>}1/\mathrm{Ws}1)}+m\&times;\sqrt{(\mathrm{Ls}/\mathrm{Ws})})---\left(10\right)$

Even utilize second embodiment also can access the effect identical with first embodiment.

(C) the 3rd embodiment

Below, with reference to three embodiment of description of drawings according to sensor base plate of the present invention and testing fixture.The 3rd embodiment only amplifying circuit in the sensor circuit 8 is different with the embodiment of having stated, below, the amplifying circuit in the 3rd embodiment is described.

Fig. 4 is the circuit diagram of the structure of the related amplifying circuit of expression the 3rd embodiment, and, corresponding Reference numeral same to the part additional phase identical, corresponding with the accompanying drawing of having stated represented.

In Fig. 4, the amplifying circuit of the 3rd embodiment is to having added on the source ground amplifying circuit 30B as source follower circuit or rectification circuit and the amplifying circuit of the source follower/rectification circuit 34 that plays a role.In addition, also can go up the additional source follower/rectification circuit 34 that plays a role as source follower circuit or rectification circuit to the source ground amplifying circuit 30A of the source ground amplifying circuit 30 of first embodiment, second embodiment.

There is following difference in the source ground amplifying circuit 30B of the 3rd embodiment with respect to the source ground amplifying circuit 30 of first embodiment.

In the source ground amplifying circuit 30B of the 3rd embodiment, remove the drain electrode of amplifying mos transistor M1 and being connected of lead-out terminal Vo in the source ground amplifying circuit 30 of first embodiment, lead-out terminal Vo is connected cascade to be connected in the drain electrode of MOS transistor M2, the grid that cascade is connected MOS transistor M2 is connected that cascade gate bias power supply Vb goes up and the source electrode that this cascade connects MOS transistor M2 is connected in the drain electrode of amplifying mos transistor M1, between the source electrode of amplifying mos transistor M1 and ground wire, be connected the high-frequency compensation capacity cell (below, be called high-frequency compensation electric capacity) Cp (comprising electric capacity 0), between lead-out terminal Vo and ground wire, be connected high-frequency cut-off capacity cell (below, be called high-frequency cut-off electric capacity) CL (comprising electric capacity 0).

At this, except above-mentioned tie point, high-frequency compensation capacitor C p also can be connected source impedance with on the transistorized terminal of any diodeization in the diode transistor block 31, equally, high-frequency cut-off capacitor C L also can be connected load with on the transistorized terminal of any diodeization in the diode transistor block 32.High-frequency compensation characteristic and high-frequency cut-off characteristic change according to the link position and the capacitance of electric capacity.

The action of the source ground amplifying circuit 30B of the 3rd embodiment source ground amplifying circuit 30 with first embodiment basically is identical.But, in the source ground amplifying circuit 30B of the 3rd embodiment, from the drain electrode of amplifying mos transistor M1 load is estimated in interior impedance to be the source impedance of cascade MOS transistor M2 with diode transistor block 32 sides, therefore, by source impedance being set for, can improve the deterioration of the high frequency characteristics that causes by the Miller capacitance effect of amplifying mos transistor M1 less than the impedance RML * n of load with diode transistor block 32.

Under the unchallenged situation of Miller capacitance effect of amplifying mos transistor M1, also can not add cascade MOS transistor M2.Also can be to the source ground amplifying circuit 30 of the first above-mentioned embodiment, the additional cascade MOS transistor M2 of source ground amplifying circuit 30A of second embodiment.

In the source ground amplifying circuit 30B of the 3rd embodiment, in the frequency field more than the time constant that is determined with the impedance RMs * m of diode transistor block 31 by high-frequency compensation capacitor C p and source impedance, the AC impedance that is connected the source side of amplifying mos transistor M1 descends and voltage gain increases.By suitably setting the gain decline that this time constant can compensate high frequency side.

At this, to compare source impedance enough big with the impedance RMs * m of diode transistor block 31 with the source impedance RM1s of amplifying mos transistor M1 if be set in advance, then by the time constant of Cp and RMs * m decision with lower frequency in, formula (11) is set up, by the time constant of Cp and RM1s decision with upper frequency in, formula (12) is set up, if will be set near the 1/f noise zone by the time constant of Cp and RMs * m decision, then can reduce this 1/f noise.

A≈RML×n/RMs×m (11)

A≈RML×n/RM1s (12)

In addition, constitute low-pass filter (LPF) with the impedance RML * n of diode transistor block 32, therefore can remove unwanted radio-frequency component (noise) by suitably setting this time constant by high-frequency cut-off capacitor C L and load.

In addition, under the situation that does not need high-frequency compensation, also can omit high-frequency compensation capacitor C p, under the situation that does not need high-frequency cut-off, also can omit high-frequency cut-off capacitor C L.Also can be to the source ground amplifying circuit 30 of the first above-mentioned embodiment, source ground amplifying circuit 30A additional high building-out capacitor Cp, the high-frequency cut-off capacitor C L of second embodiment.

In addition, for the change with respect to the dc bias current I of the change of the threshold voltage vt of MOS transistor is diminished, preferably increase source impedance with the MOS transistor number m in the diode transistor block 31, and and the increase of MOS transistor number m increase input direct current biasing power supply Vidc among the input voltage Vi that is included in source ground amplifying circuit 30B and the voltage between the negative supply Vee accordingly.

When increasing source impedance with the MOS transistor number m in the diode transistor block 31, gain descends, if therefore high-frequency compensation capacitor C p is made as and in by the signal band, is the capacitance of low-down impedance, and source impedance is made as with the link position of the electric capacity in the diode transistor block 31 can guarantees the position of gaining, then can suppress change, and can guarantee gain with respect to the dc bias current I of the change of the threshold voltage vt of MOS transistor.

On the output Vo of the source ground amplifying circuit 30B of the 3rd embodiment, be connected with the input terminal Vi1 of source follower/rectification circuit 34.

As source follower circuit or rectification circuit and the source follower/rectification circuit 34 that plays a role constitutes the drain electrode that grid is connected the source follower MOS transistor M3 on the input terminal Vi1 of this source follower/rectification circuit 34 is connected on the second positive supply Vdd1, be connected in parallel between the source electrode of source follower MOS transistor M3 and the ground wire source follower load constant current source Ida and voltage keep capacity cell (below, be called voltage and keep electric capacity) Ch, with the source electrode of source follower MOS transistor M3 output Vo1 as source follower/rectification circuit 34.In addition, also can keep any value of capacitor C h to be made as 0 source follower load constant current source Ida and voltage.In addition, also source follower load constant current source Ida can be replaced as fixed resistance.

Under the situation that steady current Ida is very big, voltage maintenance capacitor C h is very little that source follower load constant current source Ida is flowed out, source follower/rectification circuit 34 moves as the voltage buffer circuit (source follower circuit) of high input impedance, low output impedance, and has the level shift circuit function of the DC potential of making displacement.

On the contrary,, voltage very little at the steady current Ida that source follower load constant current source Ida is flowed out keeps becoming the peak holding circuit of high input impedance under the very large situation of capacitor C h.

If suitably select the size of the steady current Ida that source follower load constant current source Ida flowed out and the capacitance that voltage keeps capacitor C h, the envelope (envelope) of the amplitude peak of the AC signal of the output Vo1 trace signals source of source follower/rectification circuit 34 (the source ground amplifying circuit 30B of the 3rd embodiment) then, thus the action identical become with the detecting circuit of AM modulation signal.

Can reach amplifying circuit (source ground amplifying circuit 30) the identical effect related according to the related amplifying circuit of the 3rd embodiment with first embodiment, can also reach following effect (a)～(e), consequently can carry out than the more inspection of pinpoint accuracy in the past according to the sensor base plate and the testing fixture of the 3rd embodiment.

(a) by the deterioration that cascade MOS transistor M2 can improve high frequency characteristics is set.

(b) by the gain decline that high-frequency compensation capacitor C p can compensate high frequency side is set.

(c) by being set, high-frequency cut-off capacitor C L can remove unwanted radio-frequency component (noise).

(d) increase source impedance with the MOS transistor number m in the diode transistor block 31, high-frequency compensation capacitor C p is made as in by the signal band, is the capacitance of low-down impedance, source impedance is made as with the electric capacity link positions in the diode transistor block 31 can guarantees the position of gaining, change can be suppressed thus, and gain can be guaranteed with respect to the dc bias current I of the change of the threshold voltage vt of MOS transistor.

(e) by being set, source follower/rectification circuit 34 can suitably select signal waveform to test department etc.

(D) the 4th embodiment

Below, with reference to four embodiment of description of drawings according to sensor base plate of the present invention and testing fixture.The 4th embodiment only amplifying circuit in the sensor circuit 8 is different with the embodiment of having stated, below, the amplifying circuit in the 4th embodiment is described.The amplifying circuit of the 4th embodiment is transistor differential amplifier circuit (below, abbreviate differential amplifier circuit as).

(D-1) structure of the 4th embodiment

Fig. 5 is the circuit diagram of the structure of the related differential amplifier circuit of expression the 4th embodiment, and, corresponding Reference numeral same to the part additional phase identical, corresponding with the accompanying drawing of having stated represented.

In Fig. 5, never the differential amplifier circuit 40 of 25 pairs the 4th embodiments in balanced type differential wave source is imported unbalanced signal.In Fig. 5, signal source 25 is shown with equivalent electrical circuit.

Signal source 25 structures are as follows: input direct current biasing power supply Vidc and input exchange signal source Vs and with an end ground connection is connected in series, with the positive output Vsop of the other end as this signal source 25, and with the output of the above-mentioned input direct current biasing power supply Vidc negative output Vson as this signal source 25.

The differential amplifier circuit 40 of the 4th embodiment constitutes as follows: with grid as being connected first source impedance between the source electrode of the first differential amplifying mos transistor M1a of the sub-Vip of normal phase input end of this differential amplifier circuit 40 and the suction-type constant current source Is with diode transistor block 41a, between the drain electrode of the first differential amplifying mos transistor M1a and positive supply Vdd, be connected first load with diode transistor block 42a, and with grid as being connected second source impedance between the source electrode of the second differential amplifying mos transistor M1b of the sub-Vin of negative-phase input of this differential amplifier circuit 40 and the suction-type constant current source Is with diode transistor block 41b, between the drain electrode of the second differential amplifying mos transistor M1b and positive supply Vdd, connect second load with diode transistor block 42b, with first load with (drain electrode) link of the first differential amplifying mos transistor M1a of diode transistor block 42a negative lead-out terminal Von as this differential amplifier circuit 40; With second load with (drain electrode) link of the second differential amplifying mos transistor M1b of diode transistor block 42b as the sub-Vop of the positive output end of this differential amplifier circuit 40.

First, second source impedance constitutes connection in series-parallel respectively with diode transistor block 41a, 41b and connects limited (comprising 0) diode transistor, and this diode transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode.In the example of Fig. 5, first, second source impedance is made of diode MOS transistor Msa, a Msb respectively with diode transistor block 41a, 41b.

First, second load constitutes connection in series-parallel respectively with diode transistor block 42a, 42b and connects limited diode transistor, and this diode transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode.In the example of Fig. 5, first, second load constitutes be connected in series four diode MOS transistor ML1a～ML4a, ML1b～ML4b respectively with diode transistor block 42a, 42b.

(D-2) action of the 4th embodiment

In Fig. 5, the input terminal Vip of differential amplifier circuit 40 and Vin are the grid of the first and second differential amplifying mos transistor M1a and M1b, therefore do not have electric current to flow through in input terminal Vip, Vin.

First, second source impedance is with diode transistor block 41a, among the 41b, electric current and the differential input voltage that is applied between input terminal Vip and the Vin correspondingly flow through, because first, second source impedance is with diode transistor block 41a, the tie point of 41b is connected on the suction-type constant current source Is, therefore the current potential that suitably changes this tie point (suction-type constant current source Is splicing ear) moves, and makes to flow through first and second source impedance and always equate with the constant current value Is that suction-type constant current source Is flows out with the electric current sum of diode transistor block 41a and 41b.

Promptly, become such action: flow through second source impedance and reduce (increase) with the electric current of diode transistor block 41b and flow through first source impedance and increase the amount of (minimizing), thereby flow through and the corresponding difference current of the differential voltage of input terminal Vip and Vin in diode transistor block 41a, 41b in these first, second source impedance with the electric current of diode transistor block 41a.

Flow through first load with diode transistor block 42a with electric current that first source impedance equates with the electric current of diode transistor block 41a, flow through second load with diode transistor block 42b with electric current that second source impedance equates with the electric current of diode transistor block 41b, thereby between sub-Vop of positive output end and negative lead-out terminal Von, produce differential output voltage.

The action bias current of the differential amplifying mos transistor M1a of first, second of this differential amplifier circuit 40, M1b does not rely on input direct current biasing power supply Vidc, and the action bias current sum of these MOS transistor M1a, M1b is the constant current value Is that suction-type constant current source Is is flowed out.

Can consider that similarly the pull-up resistor of the rear-stage side of this differential amplifier circuit 40 is the differential voltage gain A under the infinitely-great situation with the source ground amplifying circuit 30 of first embodiment, when with first, the second differential amplifying mos transistor M1a, the source impedance of M1b is made as RM1sa respectively, RM1sb, with first, second source impedance is with diode transistor block 41a, the transistorized impedance of each diodeization in the 41b is made as RMsa, RMsb, with first, second source impedance is with diode transistor block 41a, transistor series in the 41b connects number and is made as ma, mb, with first and second loads with diode transistor block 42a, the transistorized impedance of each diodeization in the 42b is made as RMLa, RMLb, with first, second load is with diode transistor block 42a, transistor series in the 42b connects number and is made as na, during nb, can represent differential voltage gain A with formula (13).Wherein, formula (13) illustrates following situation: first, second differential amplifying mos transistor M1a, M1b are identical structure as RM1sa=RM1sb=RM1s, first, second source impedance is identical structure with diode transistor block 41a, 41b as RMsa=RMsb=RMs, ma=mb=m, and first, second load is identical structure with diode transistor block 42a, 42b as RMLa=RMLb=RML, na=nb=n.

A＝RML×n/(RM1s+RMs×m) (13)

When similarly making the transistorized shape of MO S that constitutes this differential amplifier circuit 40 consistent with the situation of first embodiment, RML=RM1s ≈ RMs, therefore, formula (13) can be deformed into formula (14), when n＞(1+m), becomes voltage amplification and moves.

A≈n/(1+m) (14)

When the situation with first embodiment similarly the grid width of first, second amplifying mos transistor M1a, M1b is made as Ws1, when grid length is made as Ls1 and new proportionality constant K is set, can enough formulas (15) represent first, second source impedance RM1sa, the RM1sb of first, second amplifying mos transistor M1a, M1b.

$\mathrm{RM}1s\&ap;(K/\sqrt{I})\&times;\sqrt{(\mathrm{<figure-callout\; id="1"\; label="Ls"\; filenames="A2009101423310086H1.png,A2009101423310088H1.png"\; state="\{\{state\}\}">Ls</figure-callout>}1/\mathrm{Ws}1)}---\left(15\right)$

When becoming diode when connecting grid and drain electrode, the value of calculating with formula (15) is the diode impedance.

Similarly, when the grid width with transistor Ms be made as Ws, when grid length is made as Ls, can enough formulas (16) represent the diode impedance RMs of first, second source impedance with transistor Msa, Msb in diode transistor block 41a, the 41b, when first, second load is made as WL, when grid length is made as LL, can enough formulas (17) represents the diode impedance RML of these transistors ML1a～ML4a, ML1b～ML4b with the grid width of transistor ML1a～ML4a, ML1b～ML4b in diode transistor block 42a, the 42b.

$\mathrm{RMs}\&ap;(K/\sqrt{I})\&times;\sqrt{(\mathrm{Ls}/\mathrm{Ws})}---\left(16\right)$

$\mathrm{RML}\&ap;(K/\sqrt{I})\&times;\sqrt{(\mathrm{LL}/\mathrm{WL})}---\left(17\right)$

When the result with formula (15)～(17) is brought into formula (13),

Be cancelled, obtain formula (18), as can be known gain A be not subjected to each MOS transistor threshold voltage vt, bias current influence and become the ratio of the grid size and the number of each MOS transistor.

$A=n\&times;\sqrt{(\mathrm{LL}/\mathrm{WL})}/(\sqrt{(\mathrm{<figure-callout\; id="1"\; label="Ls"\; filenames="A2009101423310086H1.png,A2009101423310088H1.png"\; state="\{\{state\}\}">Ls</figure-callout>}1/\mathrm{Ws}1)}+m\&times;\sqrt{(\mathrm{Ls}/\mathrm{Ws})})---\left(18\right)$

Under the situation of the anti-phase output amplifier that has used operational amplifier, the negative feedback resistor of gain decision usefulness reduces the input impedance as amplifying circuit, but in the differential amplifier circuit 40 of the 4th embodiment, input impedance is the grid input impedance of MOS transistor, therefore the input impedance as amplifying circuit can be maintained high impedance.

Each MOS transistor can be considered as in the actuating range of saturated action, with first embodiment similarly, therefore always set up formula (13)～(18), guarantees linear characteristic and do not produce waveform distortion.

Gain be not subjected to each MOS transistor threshold voltage vt, bias current influence and to become only be the grid size of each MOS transistor and the function of number, therefore, even shown in the synoptic diagram of Fig. 6, plural parallel stage connects this differential amplifier circuit 40 between power lead, supply voltage because the caused voltage of power lead electric current and power lead resistance descends away from the amplifying circuit 40 of power supply terminal descends, source current reduces, and all multipole differential amplifying circuits 40 also can obtain identical voltage gain.

Under plural parallel stage is connected situation between the power lead, even supply voltage descends, source current reduces and also can obtain identical voltage gain this point in the source ground amplifying circuit 30 of first～the 3rd embodiment, 30A, 30B also identical (with reference to formula (9)), but under the situation of the 4th embodiment, the influence of the direct current biasing that differential amplification action causes can be got rid of, more identical voltage gain can be reached.

As mentioned above, on the sensor base plate of the inspection that is used in substrate for display, as shown in Figure 6, a plurality of amplifying circuits need be connected in parallel between same power lead.

In the differential amplifier circuit 40 of the 4th embodiment, the action current of first, second differential amplifying mos transistor does not rely on the voltage of input direct current biasing power supply Vidc and is decided by above-mentioned suction-type constant current source Is, therefore, even transistorized threshold voltage vt change, the action current I of first, second amplifying mos transistor M1, M2 does not change yet, and takes into account the high stable of high-gain and action current easily.

In addition, connecting under the situation of amplifying circuit at plural parallel stage between the power lead as shown in Figure 6, source ground amplifying circuit 30 at first～the 3rd embodiment, 30A, among the 30B, if it is big that output amplitude becomes, then the fluctuation of circuital current becomes big, might directly become the fluctuation (being related to power line noise) of the source current of positive supply Vdd and direct current source electrode bias supply Vidc, but in the differential amplifier circuit 40 of the 4th embodiment, because positive load current and negative load current and the fluctuation of circuital current are cancelled out each other and are diminished, thereby the possibility that produces power line noise diminishes.

Under the situation that is applied to above-mentioned sensor base plate, by the small capacitance coupling sensor only AC signal be taken into some among the input terminal Vip of above-mentioned positive or negative or the Vin, provide direct current biasing by high resistance (for example MOS resistance) to the positive that is taken into AC signal or the input terminal of negative from positive input direct current biasing power supply Vidc, the input terminal that is not taken into the AC signal side is directly connected to positive input direct current biasing power supply Vidc to be gone up and makes amplifier move (for example, use Figure 28～Figure 31 described later etc. form).

(D-3) effect of the 4th embodiment

Differential amplifier circuit 40 according to the 4th embodiment can access following effect (a)～(k), consequently can carry out than the more inspection of pinpoint accuracy in the past according to the sensor base plate and the testing fixture of the 4th embodiment.

(a) can realize the gaining influence of the threshold voltage vt that is not subjected to each MOS transistor, bias current and the differential amplifier circuit that decides by the ratio of the grid size of each MOS transistor and transistor number.

For example, on being slightly larger than the length of 25cm, be set up in parallel under the situation 7168, that be formed on the differential amplifier circuit of using the 4th embodiment in the amplifying circuit in the sensor circuit on the sensor base plate, even in same IC chemical industry preface, generate differential amplifier circuit, according to the position on the sensor base plate, the threshold voltage vt of MOS transistor also might be slightly different.But,, therefore can make the gain unanimity of the amplifying circuit of sensing (sensing) usefulness that is set up in parallel because gain is not subjected to the influence of the threshold voltage vt etc. of each MOS transistor.

(b) under the situation of the anti-phase output amplifier that has used operational amplifier, the gain decision reduces the input impedance as amplifying circuit with negative feedback resistor, but in the amplifying circuit of the 4th embodiment, because input impedance is the grid input impedance of MOS transistor, therefore the input impedance as amplifying circuit can be maintained high impedance.

(c) used the diode impedance, in can being considered as the actuating range that each MOS transistor is saturated action, having guaranteed linear characteristic and do not produce waveform distortion.

(d) when make load with and the structure of the MOS transistor used of source impedance when consistent, from low frequency to the high frequency loaded impedance and the ratio of source side impedance do not change, from the low frequency to the high frequency, can obtain smooth gain characteristic.

(e) do not need as the operation amplifier circuit from outputing to the loop negative-feedback circuit of input, therefore do not have the worry that produces vibration.

(f) do not need therefore can set the bias voltage of input part and the bias voltage of efferent for value arbitrarily from outputing to the loop negative-feedback circuit of input.

(g) can constitute by the transistor of the single type of N type (or P type), and for not using the circuit of resistive element, therefore under the situation of carrying out ICization, do not need any transistor of P type (or N type) to generate operation and resistance generation operation, can realize low manufacturing costization, casual labourer's phaseization.

(h) not having use to compare with transistor needs large-area resistive element, and therefore under the situation of having carried out ICization, comparing with the amplifying circuit that uses resistive element in the past can small sizeization (miniaturization).

(i) the action current I of first, second differential amplifying mos transistor does not rely on the voltage of input direct current biasing power supply Vidc and is determined by suction-type constant current source Is, therefore be not subjected to the influence of the change of transistorized threshold voltage vt, take into account the high stable of high-gain and action current easily.

(j) source current fluctuation is because positive load current and negative load current are cancelled each other diminishes, thereby the possibility of generation power line noise diminishes.

(k) this differential amplifier circuit plural parallel stage is connected between the power lead, even because power lead electric current and power lead resistance and descend away from the supply voltage of the differential amplifier circuit of power supply terminal, differential amplifier circuit at different levels also can both obtain stable voltage gain.

(E) the 5th embodiment

Below, with reference to five embodiment of description of drawings according to sensor base plate of the present invention and testing fixture.The 5th embodiment only amplifying circuit in the sensor circuit 8 is different with the embodiment of having stated, below, the amplifying circuit in the 5th embodiment is described.The amplifying circuit of the 5th embodiment also is a differential amplifier circuit.

Fig. 7 is the circuit diagram of the structure of the related differential amplifier circuit of expression the 5th embodiment, and, corresponding Reference numeral same to the part additional phase identical, corresponding with the accompanying drawing of having stated represented.

The related differential amplifier circuit 40A differential amplifier circuit 40 related with respect to the 4th embodiment of the 5th embodiment has the following similarities and differences.

In Fig. 7, the related differential amplifier circuit 40A of the 5th embodiment constitutes first in the differential amplifier circuit 40 of having removed the 4th embodiment, the second amplifying mos transistor M1a, each drain electrode of M1b and the sub-Vop of positive-negative output end of this differential amplifier circuit, the connection of Von and with first, second load is with diode transistor block 42a, the connection of 42b, additional common terminal is connected P raceway groove first on the positive supply Vdd, second current mirroring circuit 43a and the 43b, the drain electrode of the first amplifying mos transistor M1a is connected in the input of the first current mirroring circuit 43a, be connected second load between the output and the second negative supply Vee1 of the first current mirroring circuit 43a with diode transistor block 42b, with second load with the output link of the first current mirroring circuit 43a of diode transistor block 42b positive output terminal Vop as this differential amplifier circuit 40A, the drain electrode of the second amplifying mos transistor M1b is connected in the input of the second current mirroring circuit 43b, first load is connected with diode transistor block 42a between the output and the second negative supply Vee1 of the second current mirroring circuit 43b, with first load with the output link of the second current mirroring circuit 43b of diode transistor block 42a negative output terminal Von as this differential amplifier circuit 40A.

From as can be known above-mentioned, the relation of the source ground amplifying circuit 30A that the relation of the differential amplifier circuit 40A that the 5th embodiment is related and the differential amplifier circuit 40 of the 4th embodiment and second embodiment are related and the source ground amplifying circuit 30 of first embodiment is identical, explanation according to the differential amplifier circuit 40 of related source ground amplifying circuit 30A of second embodiment and the 4th embodiment can be understood action, therefore omits its action specification.

But the gain for the related differential amplifier circuit 40A of the 5th embodiment remarks additionally simply.In the related differential amplifier circuit 40A of the 5th embodiment, can carry out electric current by first, second current mirroring circuit 43a, 43b and amplify, be k if establish current amplification factor, then RML is

Gain A is when current amplification factor k

Doubly, be not that above-mentioned formula (18) but formula (19) are set up, but with the situation of formula (18) similarly, gain A is not subjected to the influence of threshold voltage vt, bias current of each MOS transistor and corresponding with the ratio of the grid size of each MOS transistor and number.

$A=\sqrt{k}\&times;n\&times;\sqrt{(\mathrm{LL}/\mathrm{WL})}/(\sqrt{(\mathrm{<figure-callout\; id="1"\; label="Ls"\; filenames="A2009101423310086H1.png,A2009101423310088H1.png"\; state="\{\{state\}\}">Ls</figure-callout>}1/\mathrm{Ws}1)}+m\&times;\sqrt{(\mathrm{Ls}/\mathrm{Ws})})---\left(19\right)$

Also can reach the effect identical by the 5th embodiment with the 4th embodiment.

(F) the 6th embodiment

Below, with reference to six embodiment of description of drawings according to sensor base plate of the present invention and testing fixture.The 6th embodiment only amplifying circuit in the sensor circuit 8 is different with the embodiment of having stated, below, the amplifying circuit in the 6th embodiment is described.

Fig. 8 is the circuit diagram of the structure of the related amplifying circuit of expression the 6th embodiment, and, corresponding Reference numeral same to the part additional phase identical, corresponding with the accompanying drawing of having stated represented.

In Fig. 8, the amplifying circuit of the 6th embodiment is the circuit to the additional source follower circuit 44 of differential amplifier circuit 40B.In addition, also can be to the differential amplifier circuit 40 of the 4th embodiment, the additional source follower circuit 44 of differential amplifier circuit 40A of the 5th embodiment.

The differential amplifier circuit 40B of the 6th embodiment has the following similarities and differences with respect to the differential amplifier circuit 40 of the 4th embodiment.

The differential amplifier circuit 40B of the 6th embodiment constitutes first in the differential amplifier circuit 40 of having removed the 4th embodiment, the second amplifying mos transistor M1a, the drain electrode of M1b and negative lead-out terminal Von, the connection of the sub-Vop of positive output end, negative lead-out terminal Von is connected in the drain electrode of the first cascade MOS transistor M2a, the grid of the first cascade MOS transistor M2a is connected on the cascade gate bias power supply Vb, the source electrode of the first cascade MOS transistor M2a is connected in the drain electrode of the first amplifying mos transistor M1a, the sub-Vop of positive output end is connected in the drain electrode of the second cascade MOS transistor M2b, the grid of the second cascade MOS transistor M2b is connected on the cascade gate bias power supply Vb, the source electrode of the second cascade MOS transistor M2b is connected in the drain electrode of the second amplifying mos transistor M1b, at the first and second amplifying mos transistor M1a, connect high-frequency compensation capacitor C p between the source electrode of M1b, at negative lead-out terminal Von, connect high-frequency cut-off capacitor C L between the sub-Vop of positive output end.

In addition, under the situation that does not need high-frequency compensation, also can omit high-frequency compensation capacitor C p, under the situation that does not need high-frequency cut-off, also can omit high-frequency cut-off capacitor C L.Also can be to the differential amplifier circuit 40 of the 4th above-mentioned embodiment, differential amplifier circuit 40A additional high building-out capacitor Cp, the high-frequency cut-off capacitor C L of the 5th embodiment.

The position that replaces above-mentioned tie point, also high-frequency compensation capacitor C p can be connected first, second source impedance with between the transistorized terminal of any diodeization in diode transistor block 41a, the 41b, equally, also high-frequency cut-off can be connected first, second load with between the transistorized terminal of any diodeization in diode transistor block 42a, the 42b with electric capacity CL.High-frequency compensation characteristic and high-frequency cut-off characteristic change according to the link position and the capacitance of electric capacity.

The function of high-frequency compensation capacitor C p, high-frequency cut-off capacitor C L is identical with above-mentioned the 3rd embodiment.

In differential amplifier circuit, also can add source follower circuit, rectification circuit to positive output Vop terminal and negative output Von terminal, Fig. 8 illustrates the example that is connected with source follower circuit 44.

The sub-Vip1 of the normal phase input end of source follower circuit 44 is connected on the sub-Vop of positive output end of differential amplifier circuit 40B, and the sub-Vin1 of the negative-phase input of source follower circuit 44 is connected on the negative lead-out terminal Von of differential amplifier circuit 40B.

Source follower circuit 44 have positive with and negative with two source follower circuits.

Source follower circuit 44 constitutes source follower MOS transistor M3b, the drain electrode of M3a is connected on the second positive supply Vdd1, this source follower MOS transistor M3b, M3a is connected grid on the side of the sub-Vip1 of normal phase input end of this source follower circuit 44 and the sub-Vin1 of negative-phase input, at source follower MOS transistor M3b, connect source follower load constant current source Ida between the source electrode of M3a and the ground wire, Idb, the source electrode of source follower MOS transistor M3b is exported Vop1 as the positive of source follower circuit 44, the source electrode of source follower MOS transistor M3a is exported Von1 as the negative of source follower circuit 44.In addition, with the 3rd embodiment similarly, also can keep electric capacity to source follower load constant current source Ida, the Idb voltage that is connected in parallel respectively.

The source follower circuit 44 of the 6th embodiment also with the source follower/rectification circuit 34 of the 3rd embodiment similarly, voltage buffer circuit as high input impedance, low output impedance moves, and has the level shift circuit function of the DC potential of making displacement.

According to the 6th embodiment, aspect differential amplification action, the effect identical can be reached,, the effect identical can be reached with the 3rd embodiment in the function of high-frequency compensation capacitor C p, high-frequency cut-off capacitor C L, the function aspects of source follower circuit 44 with the 4th embodiment.

(G) the 7th embodiment

Below, with reference to seven embodiment of description of drawings according to sensor base plate of the present invention and testing fixture.The 7th embodiment only amplifying circuit in the sensor circuit 8 is different with the embodiment of having stated, below the amplifying circuit in the 7th embodiment is described.

(G-1) structure of the 7th embodiment

Fig. 9 is the circuit diagram of the structure of the related amplifying circuit of expression the 7th embodiment, and, corresponding Reference numeral same to the part additional phase identical, corresponding with the accompanying drawing of having stated represented.

In Fig. 9, the amplifying circuit 50 of the 7th embodiment is the circuit to the differential amplifier circuit 51 additional source follower circuits 44 with differential enlarging section 52 and suction-type constant current source 53.

Below, omit explanation to source follower circuit 44, differential amplifier circuit 51 is described.

Differential amplifier circuit 51 has differential enlarging section 52, suction-type constant current source 53 and power level displacement diode transistor MLs.Differential enlarging section 52 is equivalent to remove the part of suction-type constant current source 53 from the differential amplifier circuit structure.The suction-type constant current source 53 of the 7th embodiment and power level displacement diode transistor MLs has the function of dc offset voltage compensation is exported in the change of transistor threshold voltage Vt in the amplifying circuit 50, wherein, above-mentioned amplifying circuit 50 interior transistors comprise MOS transistor M3a, the M3b in the source follower circuit 44.

Differential enlarging section 52 is being connected first negative feedback source resistance Rsa with grid as between the source electrode of the first differential amplifying mos transistor M1a of the sub-Vip of normal phase input end of this differential amplifier circuit 51 and the suction-type constant current source terminal Is, between the drain electrode of the first differential amplifying mos transistor M1a and positive power terminal Vd, be connected the first pull-up resistor RLa, grid is being connected second negative feedback source resistance Rsb as between the source electrode of the second differential amplifying mos transistor M1b of the sub-Vin of negative-phase input of this differential amplifier circuit 50 and the suction-type constant current source terminal Is, between the drain electrode of the second differential amplifying mos transistor M1b and positive power terminal Vd, be connected the second pull-up resistor RLb, with first differential amplifying mos transistor M1a (drain electrode) link of the first pull-up resistor RLa negative lead-out terminal Von as this differential amplifier circuit 50, with second differential amplifying mos transistor M1b (drain electrode) link of the second pull-up resistor RLb as the sub-Vop of the positive output end of this differential amplifier circuit 51.

In addition, the power level displacement diode MOS transistor MLs that has connected grid and drain electrode is connected between the positive power terminal Vd of positive supply Vdd and differential enlarging section 52 and is forward bias.

Suction-type constant current source 53 constitutes and is connected steady current sets resistance R ss between the source electrode that drain electrode is connected the constant current source output mos transistor Mis on the suction-type constant current source terminal Is of differential enlarging section 52 and negative supply Vee, on constant current source level shift transistor biasing constant current source Iss, connect the grid of constant current source output mos transistor Mis and the source electrode of constant current source level shift MOS transistor Miss, on the grid of constant current source level shift MOS transistor Miss, connect constant-current source circuit gate bias power supply Vb1, in the drain electrode of constant current source level shift MOS transistor Miss, connect the 3rd positive supply Vdd2.

(G-2) action of the 7th embodiment

About differential amplification action in the amplifying circuit of the 7th embodiment and source follower circuit action, can understand according to above-mentioned explanation, therefore omit explanation.

Be set at the forward bias voltage of the power level displacement diode MOS transistor MLs between the positive power terminal Vd that is connected positive supply Vdd and differential enlarging section 52 in advance and drain electrode be connected the grid of the constant current source output mos transistor Mis on the suction-type constant current source terminal Is of differential enlarging section 52 identical, be connected first with the voltage between source electrode, the second differential amplifying mos transistor M1a, between each drain electrode of M1b and the positive power terminal Vd first, the second pull-up resistor RLa, voltage between terminals during the no signal of RLb is identical with the voltage between terminals that the steady current between source electrode that is connected constant current source output mos transistor Mis and the negative supply Vee is set resistance R ss.

Specifically, owing in power level displacement diode MOS transistor MLs and constant current source output mos transistor Mis, flow through identical electric current, therefore be made as the MOS transistor of identical grid width, identical grid length, identical threshold voltage vt, flow through first, second pull-up resistor RLa, RLb owing to flow through half electric current of the electric current of steady current setting resistance R ss, therefore be made as RLa=RLb=2 * Rss.

By above setting, the source potential Vb1o of potential difference (PD) between sub-Vop of the positive-negative output end of positive supply Vdd and differential enlarging section 52 and the Von and constant current source level shift MOS transistor Miss and the potential difference (PD) between the negative supply Vee, as the formula (20), irrespectively always equate with the change of transistorized threshold voltage vt.Below, the relation of formula (20) is called condition 1.

Vdd-Vop=Vdd-Von=Vb1o-Vee (20) (condition 1)

And, when with constant current source level shift MOS transistor Miss and first, the second source follower MOS transistor M3a, the grid length of M3b is set for equal, with first, the second source follower MOS transistor M3a, the grid width ratio of M3b and constant current source level shift MOS transistor Miss is set for and first, the second source follower load constant current source Ida, the output current Ida of Idb, when the current ratio of the output current Iss of Idb and constant current source level shift transistor biasing constant current source Iss equates, then as the formula (21), first, the second source follower MOS transistor M3a, the grid of M3b and the voltage between the source electrode equate with the grid of constant current source level shift MOS transistor Miss and the voltage between the source electrode.

Vip1-Vop1＝Vin1-Von1＝Vb1-Vb1o (21)

Because Vip1=Vop, Vin1=Von, therefore, formula (21) can be rewritten as formula (22).Below, the relation of formula (22) is called condition 2.

Vop-Vop1=Von-Von1=Vb1-Vb1o (22) (condition 2)

When additive operation is carried out respectively in each limit of above-mentioned formula (20) and formula (22), can access formula (23), when being made as Vo1=Vop1=Von1, then formula (23) can be deformed into formula (24).

Vdd-Vop1＝Vdd-Von1＝Vb1-Vee (23)

Vo1＝Vdd-Vb1+Vee (24)

Promptly, can with the change of transistorized threshold voltage vt irrespectively, make between the sub-Vop1 of positive-negative output end, the Von1 of positive supply Vdd and source follower circuit 44 potential difference (PD) always with constant-current source circuit gate bias power supply Vb1 and negative supply Vee between potential difference (PD) equate.

Because can carry out the bias voltage compensation (condition 1) of 53 of differential enlarging section 52 and suction-type constant current sources respectively independently, to the compensation (condition 2) of the level shifting voltage of two source follower circuits in the source follower circuit 44, therefore can make the MOS transistor optimal sizeization (performance) of differential enlarging section 52, suction-type constant current source 53 and source follower circuit 44.

Be schematically shown as Fig. 6, when between power lead, being connected in parallel the amplifying circuit of a plurality of the 7th embodiments, the positive supply electric current of positive supply Vdd and the negative supply current of negative supply Vee have proportionate relationship, do not have source current to flow through in constant-current source circuit gate bias power supply Vb1.Thereby the power line voltage of constant-current source circuit gate bias power supply Vb1 is all identical in any position.

On the other hand, because each source current flows through in positive supply Vdd line and negative supply Vee line, therefore along with leaving feeder ear, the current potential of positive power line voltage descends because the voltage of power lead electric current and power lead resistance descends, and, along with leaving feeder ear, because the voltage of power lead electric current and power lead resistance descends and the current potential rising (sense of current is opposite in positive supply and negative supply) of negative power line voltage, when the ratio of the unit head's of the unit head's who is set at positive power line in advance resistance and negative power line resistance is inversely proportional to the current ratio that flows through in these positive-negative power lines, then the voltage Δ Vee that rises of the voltage of the voltage Δ Vdd that descends of the voltage of positive power line and negative power line equates.When this relationship delta Vdd=Δ Vee is applied to above-mentioned formula (24), can obtain formula (25), as can be known the output offset Vo1 of differential amplifier circuit with leave feeder ear range-independence fix, that is the change of the output offset Vo1 of differential amplifier circuit and transistorized threshold voltage vt,, leave feeder ear range-independence fix.

Vo1＝Vdd-ΔVdd-Vb1+Vee+ΔVee

＝Vdd-Vb1+Vee (25)

(G-3) effect of the 7th embodiment

According to the amplifying circuit 50 of the 7th embodiment, can reach following effect (a)～(c), consequently can carry out than the more inspection of pinpoint accuracy in the past according to the sensor base plate and the testing fixture of the 7th embodiment.

(a) there is not the differential amplifier circuit that the rectification output dc offset voltage when importing is also always fixed even can access the threshold voltage vt change of MOS transistor.

(b) connect under the situation of differential amplifier circuit at plural parallel stage between power lead, can access following differential amplifier circuit: the supply voltage because the voltage that power lead electric current and power lead resistance cause descends away from the amplifying circuit of power supply terminal descends, but descend with respect to this supply voltage, the output dc offset voltage when not having input does not change.

(c) since can independently carry out for 53 of the differential enlarging section 52 of the change of the threshold voltage vt of MOS transistor and suction-type constant current sources bias voltage compensation (above-mentioned condition 1), to the compensation (above-mentioned condition 2) of the level shifting voltage of two source follower circuits in the source follower circuit 44, therefore can make the MOS transistor optimal sizeization (performance) of differential enlarging section 52, suction-type constant current source 53 and source follower circuit 44.

(H) the 8th embodiment

Then, with reference to eight embodiment of description of drawings according to sensor base plate of the present invention and testing fixture.The 8th embodiment only amplifying circuit in the sensor circuit 8 is different with the embodiment of having stated, below, the amplifying circuit in the 8th embodiment is described.

Figure 10 is the circuit diagram of the structure of the related amplifying circuit of expression the 8th embodiment, and, corresponding Reference numeral same to the part additional phase identical, corresponding with the accompanying drawing of having stated represented.

The related amplifying circuit 50A of the 8th embodiment compares with the amplifying circuit of the 7th embodiment, has the following similarities and differences.

In the related amplifying circuit 50A of the 8th embodiment, constitute differential enlarging section 52A as follows: first negative feedback source resistance Rsa that removes the differential enlarging section 52 in the amplifying circuit 50 of the 7th embodiment, with the source electrode of the first differential amplifying mos transistor M1a as the first suction-type constant current source terminal Isa, and remove second negative feedback source resistance Rsb of differential enlarging section 52, the source electrode of the second differential amplifying mos transistor M1b as the second suction-type constant current source terminal Isb, is connected source resistance Rs between the source electrode of the first and second differential amplifying mos transistor M1a and M1b.

In addition, constitute suction-type constant current source 53A as follows in the related amplifying circuit 50A of the 8th embodiment: constant current source output mos transistor Mis and the steady current removed in the amplifying circuit 50 of the 7th embodiment are set resistance R ss, between source electrode that drain electrode is connected the first constant current source output mos transistor Misa on the first suction-type constant current source terminal Isa and negative supply Vee, connect first steady current and set resistance R ssa, and, between source electrode that drain electrode is connected the second constant current source output mos transistor Misb on the second suction-type constant current source terminal Isb and negative supply Vee, connect second steady current and set resistance R ssb, with first, the second constant current source output mos transistor Misa, the source electrode of each grid of Misb and constant current source level shift MOS transistor Miss is connected on the constant current source level shift transistor biasing constant current source Iss.

In the related amplifying circuit 50A of the 8th embodiment, the forward bias voltage that is set at power level displacement diode MOS transistor MLs in advance equates with each grid of first, second constant current source output mos transistor Misa, Misb and the voltage between source electrode, and the voltage between terminals the during no signal of first, second pull-up resistor RLa, RLb equates with the voltage between terminals of first, second steady current setting resistance R ssa, Rssb.

Specifically, flow through first owing to flow through half electric current of the electric current of power level displacement diode MOS transistor MLs, the second constant current source output mos transistor Misa, Misb, therefore, set the be shifted grid width of diode MOS transistor MLs of power level for first, the second constant current source output mos transistor Misa, the twice of the grid width of Misb, and be made as identical grid length, the MOS transistor of identical threshold voltage vt, be made as RLa=RLb=Rssa=Rssb, make the electric current that equates flow through first, the second pull-up resistor RLa, RLb and first, second steady current is set resistance R ssa, Rssb.

By above setting, the source potential Vb1o of potential difference (PD) between the sub-Vop of the positive-negative output end of positive supply Vdd and differential enlarging section, the Von and constant current source level shift MOS transistor Miss and the potential difference (PD) between the negative supply Vee, irrespectively always equate with the change of transistorized threshold voltage vt, thereby above-mentioned condition 1 is set up.

The related amplifying circuit 50A of the 8th embodiment also with the related amplifying circuit 50 of the 7th embodiment similarly, condition 2 is set up.

If make above-mentioned condition 1 and condition 2 set up simultaneously, then with the related amplifying circuit 50 of the 7th embodiment similarly, the change that can make potential difference (PD) and transistorized threshold voltage vt between the sub-Vop1 of positive-negative output end, the Von1 of positive supply Vdd and first, second source follower circuit irrespectively always with constant-current source circuit gate bias power supply Vb1 and negative supply Vee between potential difference (PD) equate.

Also can reach the effect identical by the 8th embodiment with the 7th above-mentioned embodiment.

(I) the 9th embodiment

Below, with reference to nine embodiment of description of drawings according to sensor base plate of the present invention and testing fixture.The 9th embodiment only amplifying circuit in the sensor circuit 8 is different with the embodiment of having stated, below, the amplifying circuit in the 9th embodiment is described.

Figure 11 is the circuit diagram of the structure of the related amplifying circuit of expression the 9th embodiment, and, corresponding Reference numeral same to the part additional phase identical, corresponding with the accompanying drawing of having stated represented.

The related amplifying circuit 50B of the 9th embodiment compares with the amplifying circuit 50 of the 7th embodiment, has the following similarities and differences.

In the related amplifying circuit 50B of the 9th embodiment, remove constant current source output mos transistor Mis, steady current in the amplifying circuit 50 of the 7th embodiment and set first, second source follower load constant current source Ida and the Idb of resistance R ss, constant current source level shift transistor biasing constant current source Iss, source follower circuit 44.

In the related amplifying circuit 50B of the 9th embodiment, on the source electrode of constant current source level shift MOS transistor Miss, connect the end that the second benchmark steady current is set resistance R sss, be connected with on the other end of this second benchmark steady current setting resistance R sss: (1) steady current is set diode MOS transistor Mis1, its grid that will become the input terminal of current mirroring circuit is connected with drain electrode, and the source electrode that will become the common terminal of this current mirroring circuit is connected on the negative supply Vee; (2) first mirror currents output mos transistor Mm1, it is connected drain electrode on the suction-type constant current source terminal Is of differential enlarging section 53, grid is connected on the input terminal of this current mirroring circuit, source electrode is connected on the common terminal of this current mirroring circuit; (3) second mirror currents output mos transistor Mm2, it is connected drain electrode on the source electrode of the first source follower MOS transistor M3a, grid is connected on the input terminal of this current mirroring circuit, source electrode is connected on the common terminal of this current mirroring circuit; (4) the 3rd mirror currents output mos transistor Mm3, it is connected drain electrode on the source electrode of the second source follower MOS transistor M3b, grid is connected on the input terminal of this current mirroring circuit, source electrode is connected on the common terminal of this current mirroring circuit.

In the related amplifying circuit 50B of the 9th embodiment, the forward bias voltage that is set at power level displacement diode MOS transistor MLs in advance equates with the forward bias voltage that the steady current of current mirroring circuit is set diode MOS transistor Mis1, and the voltage between terminals the during no signal of first, second pull-up resistor RLa, RLb equates with the voltage between terminals of second benchmark steady current setting resistance R sss.

Perhaps, grid and the voltage between source electrode of setting first, second source follower MOS transistor M3a, M3b in advance for equate with the forward bias voltage that the steady current of current mirroring circuit is set diode MOS transistor Mis1, the forward bias voltage of power level displacement diode MOS transistor MLs equates with the grid of constant current source level shift MOS transistor Miss and the voltage between source electrode, and the voltage between terminals the during no signal of first, second pull-up resistor RLa, RLb equates with the voltage between terminals of second benchmark steady current setting resistance R sss.

Specifically, transistorized grid length and threshold voltage vt are equated, grid width and the current value that will flow through are become greatly with being directly proportional, resistance value and the current ratio that will flow through are inversely proportional to.

By more than, with the related amplifying circuit 50 of the 7th embodiment similarly, the change that can make potential difference (PD) and transistorized threshold voltage vt between the sub-Vop1 of positive-negative output end, the Von1 of positive supply Vdd and source follower circuit 44B irrespectively always with constant-current source circuit gate bias power supply Vb1 and negative supply Vee between potential difference (PD) equate.

(J) the tenth embodiment

Then, with reference to ten embodiment of description of drawings according to sensor base plate of the present invention and testing fixture.The tenth embodiment only amplifying circuit in the sensor circuit 8 is different with the embodiment of having stated, below, the amplifying circuit in the tenth embodiment is described.The amplifying circuit of the tenth embodiment is the differential amplifier circuit of band full-wave rectifying circuit.

(J-1) structure of the tenth embodiment

Figure 12 is the circuit diagram of the structure of the related amplifying circuit of expression the tenth embodiment, and, corresponding Reference numeral same to the part additional phase identical, corresponding with the accompanying drawing of having stated represented.

The related amplifying circuit 60 of the tenth embodiment is the differential amplifier circuits that the source follower circuit 44 in the amplifying circuit 50 of the 7th embodiment replaced to the band full-wave rectifying circuit of full-wave rectifying circuit 61.That is, the source follower circuit 44 that is connected on positive negative output Vop, the Von of differential enlarging section 52 is replaced to from the full-wave rectifying circuit 61 of first, second input terminal Vin1, Vip1 input.

Full-wave rectifying circuit 61 is following circuit: the second source follower load constant current source Idb that has removed source follower circuit 44, connect between the source electrode of first, second source follower MOS transistor M3a, M3b as full-wave rectification lead-out terminal Vo1, voltage is kept capacitor C h is additional to be connected between this full-wave rectification lead-out terminal Vo1 and the ground wire.

(J-2) action of the tenth embodiment

About the differential amplifier circuit in the related amplifying circuit 60 of the tenth embodiment action, for the compensating movement of the direct current biasing current potential of the change (when full-wave rectification output Vo1 does not have input) of the threshold voltage vt of MOS transistor, since identical with the amplifying circuit 50 of above-mentioned the 7th embodiment, its detailed description therefore omitted.

Full-wave rectifying circuit 61 in the tenth embodiment is with source follower/rectification circuit corresponding with the sub-Vin1 of first input end (with reference to above-mentioned Fig. 4) and the circuit that merges with the corresponding source follower/rectification circuit of the second input terminal Vip1.Promptly, be following circuit: the output of two source follower/rectification circuits is merged, two source follower load constant current source Ida, Idb are merged into one and again as Ida, equally, keep capacitor C ha, Chb to be merged into one and keep capacitor C h as voltage again two voltages, thereby the noble potential that becomes among two input voltage Vip1 and the Vin1 is effective action of ignoring low potential side, because two input voltage Vip1 and Vin1 are differential wave, therefore become the full-wave rectification action.

With the 7th embodiment similarly, can carry out independently to the bias voltage compensation (above-mentioned condition 1) of 53 of the differential enlarging section 52 of the change of the threshold voltage vt of MOS transistor and suction-type constant current sources with to the compensation (above-mentioned condition 2) of the level shifting voltage of the source follower MOS transistor of full-wave rectifying circuit 61, therefore, can make the MOS transistor of differential enlarging section 52, suction-type constant current source 53, full-wave rectifying circuit 61 carry out optimal sizeization (performance).

In addition, be schematically shown as Figure 13, connect at plural parallel stage between power lead under the situation of amplifying circuit 60 of the tenth embodiment, supply voltage because the voltage that power lead electric current and power lead resistance cause descends away from the amplifying circuit 60 of power supply terminal descends, but, become with respect to supply voltage and descend and direct current biasing current potential during the nothing input of full-wave rectification output Vo1 is compensated differential amplification action, the full-wave rectification action of not change with similarly in the explanation of the 7th embodiment.

(J-3) effect of the tenth embodiment

According to the amplifying circuit 60 of the tenth embodiment, can reach following effect (a)～(c), consequently can carry out than the more inspection of pinpoint accuracy in the past according to the sensor base plate and the testing fixture of the 7th embodiment.

(a) even the also always fixing additional full-wave rectification action of differential amplification action of rectification output dc offset voltage when can the threshold voltage vt change of the MOS transistor of differential amplifier circuit 51 not had input.

(b) can be to the additional full-wave rectification action of following differential amplification action: connect at plural parallel stage between power lead under the situation of amplifying circuit 60 of the tenth embodiment, supply voltage because the voltage that power lead electric current and power lead resistance cause descends away from the amplifying circuit of power supply terminal descends, but descends and output dc offset voltage when not having input does not change with respect to supply voltage.

(c) owing to can independently carry out therefore can making the MOS transistor optimal sizeization (performance) of differential enlarging section 52, suction-type constant current source 53, full-wave rectifying circuit 61 to the bias voltage compensation (above-mentioned condition 1) of 53 of the differential enlarging section 52 of the change of the threshold voltage vt of MOS transistor and suction-type constant current sources with to the compensation (above-mentioned condition 2) of the level shifting voltage of the source follower MOS transistor of full-wave rectifying circuit 61.

(J-4) the distortion embodiment of the tenth embodiment

The amplifying circuit 60 of the tenth embodiment is the circuit that the source follower circuit 44 in the amplifying circuit 50 of the 7th embodiment is replaced to full-wave rectifying circuit 61, but also source follower circuit 44, the 44B among amplifying circuit 50A, the 50B of the 8th, the 9th embodiment can be replaced to full-wave rectifying circuit.

Though detailed, but Figure 14 illustrates the figure that the source follower circuit 44 among the amplifying circuit 50A of the 8th embodiment is replaced to full-wave rectifying circuit 61, and Figure 15 illustrates the figure that the source follower circuit 44B among the amplifying circuit 50B of the 9th embodiment is replaced to full-wave rectifying circuit 61B.

(K) the 11 embodiment

Then, with reference to ten one embodiment of description of drawings according to sensor base plate of the present invention and testing fixture.The 11 embodiment only amplifying circuit in the sensor circuit 8 is different with the embodiment of having stated, below, the amplifying circuit in the 11 embodiment is described.The amplifying circuit of the 11 embodiment is the differential amplifier circuit of band peak holding circuit.By the subsidiary reset function of additional peak holding circuit.

(K-1) structure of the 11 embodiment

Figure 16 is the circuit diagram of the structure of the related amplifying circuit of expression the 11 embodiment, and, corresponding Reference numeral same to the part additional phase identical, corresponding with the accompanying drawing of having stated represented.

The related amplifying circuit 60C of the 11 embodiment is the differential amplifier circuit that the source follower circuit 44 in the amplifying circuit 50 of the 7th embodiment is replaced to the band peak holding circuit of peak holding circuit 62.That is be that the source follower circuit 44 that will be connected on positive negative output Vop, the Von of differential enlarging section 52 replaces to from the circuit of the peak holding circuit 62 of first, second input terminal Vin1, Vip1 input.

The related amplifying circuit 60C of the 11 embodiment has removed first of source follower circuit 44 in the amplifying circuit 50 of the 7th embodiment, the second source follower load constant current source Ida, Idb, connect first, the second source follower MOS transistor M3a, keep lead-out terminal Vo1 as peak value between the source electrode of M3b, keep the additional voltage maintenance capacitor C h that connects between lead-out terminal Vo1 and the ground wire at this peak value, and the additional series circuit that is connected with the on-off circuit Sw and the resistance R o of the electric current that limits this on-off circuit Sw, wherein, said switching circuit Sw will keep the voltage on the lead-out terminal Vo1 to keep the terminal of capacitor C h to be connected on the peak value hold reset bias supply Vb3 by will be connected peak value off and on from the pulse signal of switch drive pulse signal source VpL.

Promptly, in the related amplifying circuit 60C of the 11 embodiment, the steady current Ida that source follower load constant current source Ida (with reference to Figure 12) is flowed out is made as 0 (deletion), replace, be provided with on-off circuit Sw, this on-off circuit Sw will keep the voltage on the lead-out terminal Vo1 to keep the terminal of capacitor C h to be connected on the peak value hold reset bias supply Vb3 by will be connected peak value off and on from the pulse signal of switch drive pulse signal source VpL.

The peak holding circuit 62 that band shown in Figure 16 resets is circuit of schematically representing, and concrete circuit is not limited to structure shown in Figure 16.

In the related amplifying circuit 60C of the 11 embodiment, from first, the second source follower MOS transistor M3a, the threshold voltage vt that the grid of M3b and the voltage between source electrode are roughly MOS transistor begins to carry out the rectification action, therefore, grid and the voltage between source electrode of constant current source level shift MOS transistor Miss also need be made as the roughly threshold voltage vt of MOS transistor, the output current Iss of constant current source level shift transistor biasing constant current source Iss is made as far as possible little electric current, and, make the grid width of constant current source level shift MOS transistor Miss big as far as possible.

(K-2) action of the 11 embodiment

Change the compensating movement of the direct current biasing current potential of (when peak value keeps output Vo1 not have input) about the action of the differential amplifier circuit among the related amplifying circuit 60C of the 11 embodiment, to the threshold voltage vt of MOS transistor, identical with the amplifying circuit 50 of above-mentioned the 7th embodiment, therefore, omit its detailed description.

The 11 embodiment replaces to peak holding circuit 62 with the source follower circuit 44 in the amplifying circuit 50 of the 7th embodiment, therefore, the peak value maintenance action that band resets is carried out in the output of differential enlarging section 52.When on-off circuit Sw disconnects, keep output Vop of (detection peak) differential enlarging section 52 and the peak value of Von, when on-off circuit Sw connects, peak value is detected the output voltage values that output resets to peak value hold reset bias supply Vb3.In addition, resistance R o is when on-off circuit Sw is on-state, and the resetting current that is used for flowing through this on-off circuit Sw is restricted to the resistance of appropriate value.

With the 7th embodiment similarly, can carry out independently to the bias voltage compensation (above-mentioned condition 1) of 53 of the differential enlarging section 52 of the change of the transistorized threshold voltage vt of MO S and suction-type constant current sources with to the compensation (above-mentioned condition 2) of the level shifting voltage of the source follower MOS transistor of peak holding circuit 62, therefore, can make the MOS transistor optimal sizeization (performance) of differential enlarging section 52, suction-type constant current source 53, peak holding circuit 62.

In addition, as being schematically shown at above-mentioned Figure 13, connect at plural parallel stage between power lead under the situation of amplifying circuit 60C of the 11 embodiment, become following differential amplification action, peak value and keep action: the supply voltage because the voltage that power lead electric current and power lead resistance cause descends away from the amplifying circuit 60C of power supply terminal descends, but with in the 3rd embodiment, illustrate in the same manner, descend with respect to supply voltage, the direct current biasing current potential when peak value keeps the nothing of output Vo1 to import is not changed by compensation.

(K-3) effect of the 11 embodiment

Amplifying circuit 60C according to the 11 embodiment can reach following effect (a)～(c), consequently can carry out than the more inspection of pinpoint accuracy in the past according to the sensor base plate and the testing fixture of the 11 embodiment.

(a) even the peak value when can the threshold voltage vt change of the MOS transistor of differential amplifier circuit 60C not had input keeps the also always fixing additional peak value of differential amplification action of dc offset voltage of output to keep action.

(b) can keep action to the additional peak value of following differential amplification action: connect at plural parallel stage between power lead under the situation of amplifying circuit 60C of the 11 embodiment, supply voltage because the voltage that power lead electric current and power lead resistance cause descends away from the amplifying circuit of power supply terminal descends, but descend with respect to supply voltage, the output dc offset voltage when not having input does not change.

(c) owing to can carry out independently therefore can making the MOS transistor optimal sizeization (performance) of differential enlarging section 52, suction-type constant current source 53 and peak holding circuit 62 to the bias voltage compensation (above-mentioned condition 1) of 53 of the differential enlarging section 52 of the change of the threshold voltage vt of MOS transistor and suction-type constant current sources with to the compensation (above-mentioned condition 2) of the level shifting voltage of the source follower MOS transistor of peak holding circuit 62.

(K-4) the distortion embodiment of the 11 embodiment

The amplifying circuit 60C of the 11 embodiment is the circuit that the source follower circuit 44 in the amplifying circuit 50 of the 7th embodiment is replaced to peak holding circuit 62, though the diagram of omission also can replace to peak holding circuit 62 with source follower circuit 44, the 44B among amplifying circuit 50A, the 50B of the 8th, the 9th embodiment.

(L) the 12 embodiment

Then, with reference to ten two embodiment of description of drawings according to sensor base plate of the present invention and testing fixture.The 12 embodiment only amplifying circuit in the sensor circuit 8 is different with the embodiment of having stated, below, the amplifying circuit in the 12 embodiment is described.The related amplifying circuit of the 12 embodiment is the circuit that the resistance of amplifying circuit that the 7th embodiment is related replaces to the diode transistor block.

(L-1) structure of the 12 embodiment

Figure 17 is the circuit diagram of the structure of the related amplifying circuit of expression the 12 embodiment, and, corresponding Reference numeral same to the part additional phase identical, corresponding with the accompanying drawing of having stated represented.

In Figure 17, the amplifying circuit 70 of the 12 embodiment is the circuit to the differential amplifier circuit 71 additional source follower circuits 44 with differential enlarging section 72 and suction-type constant current source 73.

Below, omit explanation to source follower circuit 44, differential amplifier circuit 71 is described.

The differential amplifier circuit 51 of differential amplifier circuit 71 and the 7th embodiment shown in Figure 9 similarly has differential enlarging section 72, suction-type constant current source 73 and power level displacement diode transistor MLs.

Differential enlarging section 72 has the structure identical with following structure: with first in the differential enlarging section 52 of the 7th embodiment, second negative feedback source resistance Rsa, Rsb replaces to first, second source impedance is with diode transistor block 41a, 41b, this diode transistor block 41a, 41b is that connection in series-parallel connects limited (comprising 0) diode transistor and constitutes, this diode transistor is that connection grid and drain electrode make the transistor that becomes diode between drain electrode and source electrode, and with first in the differential enlarging section 52 of the 7th embodiment, the second pull-up resistor RLa, RLb replaces to first, second load is with diode transistor block 42a, 42b, this diode transistor block 42a, 42b is that connection in series-parallel connects limited diode transistor and constitutes, and this diode transistor is to connect grid and drain electrode makes the transistor that becomes diode between drain electrode and source electrode.

In addition, suction-type constant current source 73 has the structure identical with following structure: the setting of the steady current in the suction-type constant current source 53 of the 7th embodiment resistance R ss is replaced to the suction steady current set with diode transistor block 74, this diode transistor block 74 is that connection in series-parallel connects limited diode transistor and constitutes, and this diode transistor is to connect grid and drain electrode makes the transistor that becomes diode between drain electrode and source electrode.

(L-2) action of the 12 embodiment

Below, the characteristic action of the amplifying circuit 70 that simple declaration the 12 embodiment is related.

Embodiment similarly for voltage gain and above-mentioned the 4th (～the six), grid size and the transistorized number decision of each diodeization by MOS transistor, with respect to the change of the threshold voltage vt of MOS transistor and not change, and, embodiment similarly with the 7th (～the nine), by making the voltage between corresponding elements descend consistent, embodiment similarly with the 7th (～the nine), even obtain the threshold voltage vt change of MOS transistor, the also always fixing differential amplifier circuit of rectification output dc offset voltage when not having input.

Above action and the 4th (～the six) embodiment, embodiment similarly for the 7th (～the nine), can access following amplifying circuit: connect at plural parallel stage between power lead under the situation of the related amplifying circuit of the 12 embodiment 70 (with reference to Fig. 6), supply voltage because the voltage that power lead electric current and power lead resistance cause descends away from the amplifying circuit of power supply terminal descends, but descend with respect to this supply voltage, voltage gain and the output dc offset voltage that does not have when importing do not change, and consequently can access identical voltage gain in all multistage amplifier circuits 70.

(L-3) effect of the 12 embodiment

According to the amplifying circuit 70 of the 12 embodiment, can reach following effect (a)～(i), consequently can carry out than the more inspection of pinpoint accuracy in the past according to the sensor base plate and the testing fixture of the 12 embodiment.Following a part of effect is to reach according to illustrated reason in the embodiment of having stated.

(a) can realize gaining the threshold voltage vt that is not subjected to each MOS transistor, bias current influence and move by the differential amplification of the ratio decision of the grid size of each MOS transistor and transistor number.

(b) under the situation of the anti-phase output amplifier that has used operational amplifier, the gain decision reduces the input impedance as amplifying circuit with negative feedback resistor, but in the amplifying circuit of this embodiment, because input impedance is the grid input impedance of MOS transistor, therefore the input impedance as amplifying circuit can be maintained high impedance.

(c) use the diode impedance, each MOS transistor can be considered as in the actuating range of saturated action, keep linear characteristic, do not produce waveform distortion.

(d) if make load with and the structure of the MOS transistor used of source impedance consistent, then from low frequency to the high frequency loaded impedance and the ratio of source side impedance do not change, from the low frequency to the high frequency, can access smooth gain characteristic.

(e) do not need as the operation amplifier circuit from outputing to the loop negative-feedback circuit of input, therefore do not have the worry of vibration.

(f) do not need therefore can set the bias voltage of input part and the bias voltage of efferent for value arbitrarily from outputing to the loop negative-feedback circuit of input.

(g) can constitute by the transistor of the single type of N type (or P type), and for not using the circuit of resistive element, therefore, under the situation of carrying out ICization, do not need any transistor of P type (or N type) to generate operation and resistance generation operation, thereby realize low manufacturing costization, casual labourer's phaseization.

(h) with the embodiment of the 4th (～the six) embodiment similarly, consistent by voltage between corresponding elements is descended, even the also always fixing differential amplifier circuit of rectification output dc offset voltage can access the threshold voltage vt change of MOS transistor and do not have input the time.

(i) connect under the situation of amplifying circuit of this embodiment at plural parallel stage between power lead, can access following amplifying circuit: the supply voltage because the voltage that power lead electric current and power lead resistance cause descends away from the amplifier of power supply terminal descends, but descend with respect to this supply voltage, voltage gain and the output dc offset voltage that does not have when importing do not change.

(L-4) the distortion embodiment of the 12 embodiment

Figure 18 represents the amplifying circuit 70 of the 12 embodiment has been carried out the partly circuit diagram of the amplifying circuit 70A of distortion.

Amplifying circuit 70A is following circuit: in the amplifying circuit 70 of the 12 embodiment, the power level diode MOS transistor MLs that is shifted is divided into first, second power level displacement diode MOS transistor MLsa, MLsb, and it is appended to first, second load respectively with on diode transistor block 42a, the 42b as load elements respectively, wherein, above-mentioned power level displacement diode MOS transistor is to be connected transistor between the positive power terminal Vd of positive supply Vdd and differential enlarging section 72, that be connected grid and drain electrode.

Also can reach the effect identical by this amplifying circuit 70A with the amplifying circuit 70 of the 12 embodiment.

Figure 19 is the circuit diagram that expression has been carried out the amplifying circuit 70 of the 12 embodiment partly to be out of shape the amplifying circuit 70B that obtains.

Amplifying circuit 70B and amplifying circuit 70A similarly are divided into first, second power level displacement diode MOS transistor MLsa, MLsb with the displacement of the power level in the amplifying circuit 70 of the 12 embodiment diode MOS transistor MLs.

In addition, amplifying circuit 70B constitutes as follows: in amplifying circuit 70A, (1) removed constant current source output mos transistor Mis, connection in series-parallel connects limited diode transistor Mis1～Mis3 and the suction-type steady current that constitutes is set with diode transistor block 74, constant current source level shift transistor biasing constant current source Iss, first of source follower circuit 44, the second source follower load constant current source Ida, Idb, replace (2) on the source electrode of constant current source level shift MOS transistor Miss, connect the benchmark steady current and set a end with diode transistor block 75, it is that connection in series-parallel connects limited diode transistor Mis2～Mis4 and constitutes that this benchmark steady current is set with diode transistor block 75, this diode transistor Mis2～Mis4 connects grid and drain electrode and makes the transistor that becomes diode between drain electrode and source electrode, (3) connect on the other end of benchmark steady current setting with diode transistor block 75: (3-1) steady current is set diode MOS transistor Mis1, grid and drain electrode that it is connected to become the input terminal of current mirroring circuit, the source electrode that will become the common terminal of this current mirroring circuit is connected on the negative supply Vee; (3-2) the first mirror currents output mos transistor Mm1, it is connected drain electrode on the suction-type constant current source terminal Is of differential enlarging section 72A, grid is connected on the input terminal of this current mirroring circuit, source electrode is connected on the common terminal of this current mirroring circuit; (3-3) the second mirror currents output mos transistor Mm2, it is connected drain electrode on the source electrode of the first source follower MOS transistor M3a, grid is connected on the input terminal of this current mirroring circuit, source electrode is connected on the common terminal of this current mirroring circuit; And (3-4) the 3rd mirror currents output mos transistor Mm3, it is connected drain electrode on the source electrode of the second source follower MOS transistor M3b, grid is connected on the input terminal of this current mirroring circuit, source electrode is connected on the common terminal of this current mirroring circuit.

The benchmark steady current is set with diode transistor block 75 and is set resistance R sss corresponding to the benchmark steady current in the 9th embodiment shown in Figure 11.

Thereby suction-type constant current source 73B among the amplifying circuit 70B and the action effect of source follower circuit 44B are identical with the 9th embodiment.

(M) the 13 embodiment

Below, with reference to ten three embodiment of description of drawings according to sensor base plate of the present invention and testing fixture.The 13 embodiment only amplifying circuit in the sensor circuit 8 is different with the embodiment of having stated, below, the amplifying circuit in the 13 embodiment is described.

Figure 20 is the circuit diagram of the structure of the related amplifying circuit of expression the 13 embodiment, and, corresponding Reference numeral same to the part additional phase identical, corresponding with the accompanying drawing of having stated represented.

The related amplifying circuit 80 of the 13 embodiment is the amplifying circuits that the source follower circuit 44 of the amplifying circuit 70A in the first distortion embodiment of the 12 embodiment shown in Figure 180 replaced to full-wave rectifying circuit 61.

Full-wave rectifying circuit 61 has the identical structure of full-wave rectifying circuit 61 in the amplifying circuit 60 with the tenth embodiment shown in Figure 12 and reaches identical action effect.

Even the threshold voltage vt of MOS transistor change, voltage gain and do not have the yet always fixing action of the rectification output dc offset voltage in when input and the 12 embodiment or its to be out of shape embodiment identical, replace to full-wave rectifying circuit 61 by will be connected the positive negative output Vop of differential enlarging section 72A and the source follower circuit 44 on the Von from first, second input terminal Vin1, Vip1, change to the action of the differential amplifier circuit of band full-wave rectifying circuit from simple differential amplification action.

Be out of shape embodiment similarly with the 12 embodiment or its, can access the differential amplifier circuit of following band full-wave rectifying circuit: under the situation of plural parallel stage connection amplifying circuit between power lead (with reference to Figure 13), supply voltage because the voltage that power lead electric current and power lead resistance cause descends away from the amplifying circuit of power supply terminal descends, but descend with respect to this supply voltage, voltage gain and the output dc offset voltage that does not have when importing do not change.

The amplifying circuit 80 related by the 13 embodiment also can reach the effect identical with the 12 embodiment, and, can make output become full-wave rectification output, consequently can carry out than the more inspection of pinpoint accuracy in the past according to the sensor base plate and the testing fixture of the 13 embodiment.

The related amplifying circuit 80 of the 13 embodiment is the circuit that the source follower circuit 44 of the amplifying circuit 70A in the first distortion embodiment of the 12 embodiment shown in Figure 180 replaced to full-wave rectifying circuit 61, still also can replace to other circuit.

Figure 21 illustrates the amplifying circuit 80A (to the first distortion embodiment of the 13 embodiment) that the source follower circuit 44B among the amplifying circuit 70B of the second distortion embodiment of the 12 embodiment is replaced to full-wave rectifying circuit 61B, and the source follower circuit 44 that Figure 22 illustrates the amplifying circuit 70A in the first distortion embodiment of the 12 embodiment replaces to the amplifying circuit 80B (to the second distortion embodiment of the 13 embodiment) that is with the peak holding circuit 62 that resets.

About action, the action effect of amplifying circuit 80A shown in Figure 21, amplifying circuit 80B shown in Figure 22, can easily understand according to the explanation of the embodiment of having stated, therefore omit its explanation.

(N) other embodiments

In the explanation of the respective embodiments described above, also speak of various distortion embodiments, but can also enumerate following illustrated distortion embodiment.

(N-1) amplifying circuit of the adjunct circuits such as peak holding circuit that the additional source follower circuit of differential amplifier circuit, full-wave rectifying circuit or band are resetted is as long as satisfy following condition etc., the distortion embodiment of the embodiment that is not limited to state, the embodiment of having stated.

Have in the amplifying circuit of adjunct circuit additional, focus on the change of threshold voltage vt, positive-negative power voltage Vdd and Vee with respect to MOS transistor, above-mentioned formula (23)～formula (25) is always set up, and its prerequisite is that condition 1 shown in formula (20) and the formula (22) and condition 2 are set up.Below, put down in writing formula (23)～formula (25), formula (20) and formula (22) again.

Vdd-Vop1＝Vdd-Von1＝Vb1-Vee (23)

Vo1＝Vdd-Vb1+Vee (24)

Vo1＝Vdd-ΔVdd-Vb1+Vee+ΔVee

＝Vdd-Vb1+Vee (25)

Vdd-Vop=Vdd-Von=Vb1o-Vee (20) (condition 1)

Vop-Vop1=Von-Von1=Vb1-Vb1o (22) (condition 2)

So long as the circuit structure that above condition 1 and condition 2 set up, just be not limited to above-mentioned amplifying circuit embodiment, it is out of shape embodiment.

For example, the amplifying circuit 90 of the 14 embodiment as shown in figure 23 is such, if being made as the value of the suction steady current Is of the value that makes constant current source level shift transistor biasing steady current Iss and differential enlarging section is identical value, make constant current source level shift transistor Miss have both the structure of the effect of constant current source output mos transistor Mis, then as long as follows: make first, the second source follower MOS transistor M3a, each grid of M3b and the voltage between source electrode are not to equate with the grid of constant current source level shift transistor Miss and the voltage between source electrode, but equate with any diode voltage that steady current is set with diode transistor block (in Figure 23 from Mis1 to Mis4), and make remaining steady current set with the grid of transistorized diode voltage of diodeization and constant current source level shift transistor Miss and the voltage between source electrode and, with load with the diode voltage of diode transistor block (in Figure 23 from MLsa to ML3a, perhaps from MLsb to ML3b) and equate.

In addition, also can be following structure: the grid of constant current source level shift transistor Miss be identical with the voltage between source electrode with each grid of first, second source follower MOS transistor M3a, M3b with voltage between source electrode, steady current set with the diode voltage of diode transistor block (in Figure 23 from Mis1 to Mis4) and with load with the diode voltage of diode transistor block (in Figure 23 from MLsa to ML3a, perhaps from MLsb to ML3b) with identical.

In addition, for example, the amplifying circuit 91 of the 15 embodiment that also can be as shown in figure 24 is such, on the contrary, use current mirroring circuit, from steady current Is, generate source follower load steady current Ida and the Idb of constant current source level shift transistor biasing steady current Iss, the first and second source follower MOS transistor M3a and M3b the generative circuit of the suction steady current Is of differential enlarging section.

And, at efferent is not under the situation of the peak holding circuit that resets of source follower output circuit structure but full-wave rectifying circuit structure, band, the source follower load current Ida of first, second source follower MOS transistor M3a, M3b becomes Weak current, so the steady current Iss of constant current source level shift MOS transistor Miss also becomes Weak current.In this case, the amplifying circuit 92 of the 16 embodiment that also can be as shown in figure 25 is such, the additional second benchmark steady current generative circuit that generates the second benchmark steady current Isss, use current mirroring circuit, generate the suction steady current Is of differential enlarging section by this second reference current Isss, the steady current Iss of constant current source level shift MOS transistor Miss, the source follower load current Ida of the first and second source follower MOS transistor M3a and M3b, wherein, the above-mentioned second benchmark steady current Isss is between the bigger suction steady current Is of differential enlarging section and centre as the steady current Iss of the constant current source level shift MOS transistor Miss of Weak current.

The idea of the amplifying circuit 92 of the 16 embodiment shown in Figure 25 also can be applied to the such resistance of the 4th～the 9th embodiment and MOS transistor is mixed situation about existing, the amplifying circuit 93 of having used the 17 embodiment of above-mentioned idea shown in Figure 26.In amplifying circuit 93, make the second benchmark steady current of differential amplifier circuit suction-type constant current source set the voltage decline of resistance R sss and the resistance R La of load-side, the voltage of RLb descends consistent, and, owing to be connected with the second constant current source level shift MOS transistor Misss and two MOS transistor of mirror currents benchmark MOS transistor Mis1 between the source potential Vb1o of the constant current source level shift MO of differential amplifier circuit suction-type constant current source S transistor Miss and negative supply Vee, therefore the power level of load-side displacement diode MOS transistor also is connected with MLs1 and two MOS transistor of MLs2 correspondingly.

In condition 1 and condition 2, preferably also make corresponding transistor drain consistent with the bias voltage between source electrode.

(N-2) signal source that provides the signal source of signal also to be not limited to the respective embodiments described above to the amplifying circuit that is arranged on the sensor base plate of the present invention also can be used following illustrated signal source.For example, when the signal that sensor electrode picked up on the above-mentioned sensor base plate is offered amplifying circuit, make signal can be considered as the signal that the signal source of equivalent electrical circuit is shown from following, and offer amplifying circuit and get final product.

Signal source shown in Figure 27 is that the input biasing resistor Ri that is connected in parallel between ground wire and signal source output Vso is connected the formation that input direct current biasing power supply Vidc in the output and input DC decoupling capacitance Ci are connected the input exchange signal source Vs in the output.Constitute Hi-pass filter by these resistance R i and capacitor C i.

Signal source shown in Figure 28 be output with signal source shown in Figure 27 as positive output Vspo, output that will input dc bias current Vidc is as the differential wave source of the unbalanced type of the negative output Vsno of signal source.

Input biasing resistor Ri in Figure 27 and the signal source shown in Figure 28 also can be made as input biasing MO S resistance, input biasing resistor with the diode MOS transistor.Figure 29 is the figure that the input biasing resistor Ri of signal source shown in Figure 28 is replaced to input biasing MOS resistance.Figure 30 is that the input biasing resistor Ri with signal source shown in Figure 28 constitutes the figure of input biasing resistor with the series circuit of diode MOS transistor, and Figure 31 is that the input biasing resistor Ri with signal source shown in Figure 28 constitutes the figure of input biasing resistor with the parallel circuit of diode MOS transistor.

Though show the amplifying circuit of the respective embodiments described above with differential enlarging section and be being the circuit that the signal in the unbalanced type differential wave source of single-phase signal amplifies from ac signal which, the signal that also can be applied as have the balanced type differential wave source that positive output and negative export from ac signal which amplifies.

The structure in the balanced type differential wave source corresponding with above-mentioned various unbalanced type differential waves source has been shown in Figure 32～Figure 36.

(N-3) in the respective embodiments described above, various circuit have been described, still, can certainly have used the current mirroring circuit of other structures as current mirroring circuit.

For example, also can use the circuit of structure as shown in figure 37.Figure 37 is following current mirroring circuit: connect steady current and set with the diode transistor block between the source electrode of constant current source output mos transistor Mis and negative supply Vee, a plurality of MOS transistor Mis1～Mis3 (being not limited to 3) that this steady current is set with diode transistor block diodeization by connecting drain and gate constitutes, the steady current Iss that is generated is flow through connect grid and drain electrode and the mirror currents reference transistor Mis1 of diodeization, additional cascade connects MOS transistor Mis2 to the current mirroring circuit that is made of mirror currents output mos transistor Mm1 to Mm2, Mm1a and Mm2a, wherein, above-mentioned mirror currents output mos transistor is connected grid on the grid of this mirror currents reference transistor Mis1, source electrode is connected on the source electrode of this mirror currents reference transistor Mis1, by drain electrode output steady current, current mirroring circuit is not limited to these structures.

(N-4) to show the suction-type constant current source of introducing steady current from first, second differential amplifying mos transistor M1a, M1b side be one situation to the respective embodiments described above, but as shown in figure 38, also can have two constant current sources.

In Figure 38, constitute between the source electrode of first, second differential amplifying mos transistor M1a, M1b connect with in the past first, second negative feedback with source resistance Rsa and Rsb's and the suitable source resistance Rs of value, single suction-type constant current source is divided into two, be made as first, second suction-type constant current source Isa, the Isb of half suction steady current of outflow constant current value Is in the past respectively, be connected on first, second differential amplifying mos transistor M1a, the M1b source electrode separately.

Even also needing to make above-mentioned condition 1 and condition 2 under the situation of having used two-layer configuration as shown in figure 38 sets up.

If can replace the suction-type constant current source that illustrates in the respective embodiments described above, then also can be replaced as the suction-type constant current source that illustrates in other embodiments.

As the circuit that carries out with suction-type constant current source similar movement, exist high resistance is connected first, second negative feedback with source resistance Rsa, the link of Rsb and the circuit between the negative supply Vee, also can use this circuit.

(N-5) the various power supplys in the amplifying circuit of the respective embodiments described above, any one be 0V (ground connection) can, with under the voltage condition, also can a shared power supply.

(N-6) also can make the PN reversal of poles of each MOS transistor in the amplifying circuit of the respective embodiments described above, even the counter-rotating of supply voltage relation is moved similarly.

(N-7) for not comprising that first, second cascade connects the structure of the various embodiments of transistor M2a, Msb, high-frequency compensation capacitor C p, high-frequency cut-off capacitor C L, also can add first, second cascade and connect transistor M2a, Msb, high-frequency compensation capacitor C p, high-frequency cut-off capacitor C L.

(N-8) for the amplifying circuit of the respective embodiments described above of positive and two outputs of negative, also can delete Vop terminal or Von terminal, perhaps any in Vop11 terminal or the Von1 terminal and be made as single-phase output.According to the structure of test department 11, suitably be made as single-phase output and get final product.

Also can omit the key element that does not need side in such decision under the situation of single-phase output, for example first or second load is with a side of two source follower circuits parts in diode transistor block, the source follower circuit etc.

If carry out single-phase outputization, then the circuit elements number of packages reduces, and can dwindle chip area under the situation of carrying out ICization.

(N-9) also can be made as following amplifying circuit: omit any among first, second source follower MOS transistor M3a, the M3b of the peak holding circuit that full-wave rectifying circuit in the respective embodiments described above or band reset and half-wave peak holding circuit that additional half-wave rectifying circuit or band reset.

(N-10) except above-mentioned,, then also can be used in combination the technological thought of the respective embodiments described above if can make up.

(N-11) in the respective embodiments described above, the situation of having utilized MOS type field effect transistor (FET) as transistor is shown, but also can utilizes other unipolar transistor such as MES type, MIS type field effect transistor.

(N-12) in the above description, the situation that sensor base plate of the present invention is used in the inspection of substrate for display has been described, but so long as the substrate that electrode spread becomes array-like and can drive by each row checks that object substrate just is not limited to substrate for display.

Claims (32)

1. sensor base plate, this sensor base plate be with the noncontact form and can electromagnetic coupled ground with check the opposed sensor base plate of object substrate, have the sensor electrode that is arranged and the signal acquisition of each sensor electrode is amplified at least with each sensor electrode corresponding sensor circuit, wherein, above-mentioned inspection object substrate is a substrate of checking that the object electrode is aligned to array-like and can drives by each row, this sensor base plate is characterised in that

The amplifying circuit that is arranged in each the sensor circuit possesses respectively:

Amplify unipolar transistor, it is with the input terminal of grid as this amplifying circuit;

The negative feedback source impedance is with the diode transistor block, its connection in series-parallel connects limited (comprising 0) diode unipolar transistor and constitutes, be connected the source side of above-mentioned amplification unipolar transistor, wherein, above-mentioned diode unipolar transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode;

Load is with the diode transistor block, its connection in series-parallel connects limited diode unipolar transistor and constitutes, be connected the drain side of above-mentioned amplification unipolar transistor, wherein, above-mentioned diode unipolar transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode; And

Voltage output end, it is connected on the drain electrode side of above-mentioned load with the above-mentioned amplification unipolar transistor of diode transistor block,

Wherein, the amplifying circuit that is arranged in each the sensor circuit is made as following structure: voltage gain by the source impedance of above-mentioned amplification unipolar transistor and above-mentioned negative feedback source impedance with the impedance of the impedance sum of diode transistor block and above-mentioned load ratio decision with the impedance of diode transistor block.

2. sensor base plate according to claim 1 is characterized in that,

Between the source electrode of above-mentioned amplification unipolar transistor and first second polarity power, connect above-mentioned negative feedback source impedance with the diode transistor block as a side of positive supply or negative supply,

Between the drain electrode of above-mentioned amplification unipolar transistor and first first polarity power, connect above-mentioned load with the diode transistor block as the opposing party of positive supply or negative supply,

With above-mentioned load with the drain electrode link of the above-mentioned amplification unipolar transistor of diode transistor block voltage output end as above-mentioned amplifying circuit.

3. sensor base plate according to claim 1 is characterized in that,

Have current mirroring circuit, this current mirroring circuit is connected common terminal on first first polarity power as a side of positive supply or negative supply,

In the input of above-mentioned current mirroring circuit, connect the drain electrode of above-mentioned amplification unipolar transistor,

Between the output of above-mentioned current mirroring circuit and second second polarity power, be connected above-mentioned load with the diode transistor block as the opposing party of positive supply or negative supply,

With above-mentioned load with the above-mentioned current mirroring circuit link of diode transistor block voltage output end as above-mentioned amplifying circuit.

4. sensor base plate according to claim 1 is characterized in that,

Have the cascade that grid is connected on the cascade gate bias power supply and connect unipolar transistor,

Connect above-mentioned voltage output end in the drain electrode of above-mentioned cascade connection unipolar transistor, the source electrode that above-mentioned cascade is connected unipolar transistor is connected in the drain electrode of above-mentioned amplification unipolar transistor.

5. sensor base plate according to claim 1 is characterized in that,

Be connected high-frequency compensation electric capacity (comprising electric capacity 0) in above-mentioned negative feedback source impedance with between the transistorized terminal of any diodeization in the diode transistor block and the ground wire,

Be connected high-frequency cut-off electric capacity (comprising electric capacity 0) in above-mentioned load with between the transistorized terminal of any diodeization in the diode transistor block and the ground wire.

6. sensor base plate according to claim 1 is characterized in that,

On above-mentioned voltage output end, be connected with as source follower circuit and rectification circuit and the source follower/rectification circuit that plays a role.

7. sensor base plate according to claim 1 is characterized in that,

On above-mentioned voltage output end, be connected with the peak holding circuit that band resets.

8. sensor base plate, this sensor base plate be with the noncontact form and can electromagnetic coupled ground with check the opposed sensor base plate of object substrate, have the sensor electrode that is arranged and the signal acquisition of each sensor electrode is amplified at least with each sensor electrode corresponding sensor circuit, wherein, above-mentioned inspection object substrate is a substrate of checking that the object electrode is aligned to array-like and can drives by each row, this sensor base plate is characterised in that

The amplifying circuit that is arranged in each the sensor circuit possesses respectively:

First, second differential amplification unipolar transistor, it is a side grid normal phase input end as this amplifying circuit, and with the opposing party's grid negative-phase input as this amplifying circuit;

The suction-type constant current source, it makes the source current of above-mentioned first, second differential amplification unipolar transistor and is steady current;

First, second negative feedback source impedance is with the diode transistor block, its connection in series-parallel connects limited (comprising 0) diode transistor and constitutes, be connected the source side of above-mentioned first, second differential amplification unipolar transistor, wherein, above-mentioned diode transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode;

First, second load is with the diode transistor block, its connection in series-parallel connects limited diode transistor and constitutes, be connected the drain side of above-mentioned first, second differential amplification unipolar transistor, wherein, above-mentioned diode transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode; And

As above-mentioned first, second load with a side's of the drain electrode side of above-mentioned first, second differential amplification unipolar transistor of diode transistor block positive output end with as the opposing party's negative lead-out terminal,

The amplifying circuit that is arranged in each the sensor circuit is made as following structure: voltage gain by each source impedance of above-mentioned first, second differential amplification unipolar transistor and above-mentioned first, second negative feedback source impedance with each impedance of diode transistor block each and impedance and above-mentioned first, second load with the ratio decision of each impedance of diode transistor block.

9. sensor base plate according to claim 8 is characterized in that,

Grid is being connected the above-mentioned first negative feedback source impedance between as the source electrode of the above-mentioned first differential amplification unipolar transistor of normal phase input end of this amplifying circuit and above-mentioned suction-type constant current source with the diode transistor block,

Between the drain electrode of the above-mentioned first differential amplification unipolar transistor and first first polarity power, connect above-mentioned first load with the diode transistor block as a side of positive supply or negative supply,

Grid is being connected the above-mentioned second negative feedback source impedance between as the source electrode of the above-mentioned second differential amplification unipolar transistor of negative-phase input of this amplifying circuit and above-mentioned suction-type constant current source with the diode transistor block,

Between first polarity power of the drain electrode of the above-mentioned second differential amplification unipolar transistor and above-mentioned first, connect above-mentioned second load with the diode transistor block.

10. sensor base plate according to claim 8 is characterized in that,

Have common terminal be connected first, second current mirroring circuit on above-mentioned first first polarity power,

In the input of above-mentioned first current mirroring circuit, connect above-mentioned first drain electrode of amplifying unipolar transistor,

Between the output of above-mentioned first current mirroring circuit and second second polarity power, connect above-mentioned second load with the diode transistor block as the opposing party of positive supply or negative supply,

With above-mentioned second load with the diode transistor block and link above-mentioned first current mirroring circuit as positive output end,

In the input of above-mentioned second current mirroring circuit, connect above-mentioned second drain electrode of amplifying unipolar transistor,

Between second polarity power of the output of above-mentioned second current mirroring circuit and above-mentioned second, connect above-mentioned first load with the diode transistor block,

With above-mentioned first load with the diode transistor block and link above-mentioned second current mirroring circuit as the negative lead-out terminal.

11. sensor base plate according to claim 8 is characterized in that,

Have grid be connected first, second cascade unipolar transistor on the cascade gate bias power supply,

In the drain electrode of above-mentioned first order receipts or other documents in duplicate bipolar transistor, connect the negative lead-out terminal,

On the source electrode of above-mentioned first order receipts or other documents in duplicate bipolar transistor, connect above-mentioned first drain electrode of amplifying unipolar transistor,

In the drain electrode of above-mentioned second level receipts or other documents in duplicate bipolar transistor, connect positive output end,

On the source electrode of above-mentioned second level receipts or other documents in duplicate bipolar transistor, connect above-mentioned second drain electrode of amplifying unipolar transistor.

12. sensor base plate according to claim 8 is characterized in that,

Be connected high-frequency compensation electric capacity (comprise electric capacity 0) with the transistorized terminal of any diodeization in the diode transistor block and the above-mentioned second negative feedback source impedance between with the transistorized terminal of any diodeization in the diode transistor block in the above-mentioned first negative feedback source impedance

Be connected high-frequency cut-off electric capacity (comprise electric capacity 0) with the transistorized terminal of any diodeization in the diode transistor block and above-mentioned second load between with the transistorized terminal of any diodeization in the diode transistor block in above-mentioned first load.

13. sensor base plate, this sensor base plate be with the noncontact form and can electromagnetic coupled ground with check the opposed sensor base plate of object substrate, have the sensor electrode that is arranged and the signal acquisition of each sensor electrode is amplified at least with each sensor electrode corresponding sensor circuit, wherein, above-mentioned inspection object substrate is a substrate of checking that the object electrode is aligned to array-like and can drives by each row, this sensor base plate is characterised in that

The amplifying circuit that is arranged in each the sensor circuit possesses respectively:

Differential enlarging section, it has: first, second differential amplification unipolar transistor, it is a side grid normal phase input end as this amplifying circuit, and with the opposing party's grid negative-phase input as this amplifying circuit; First, second negative feedback source resistance, it is connected the source side of above-mentioned first, second differential amplification unipolar transistor; First, second pull-up resistor, it is connected the drain side of above-mentioned first, second differential amplification unipolar transistor; And as a side's of the drain electrode side of above-mentioned first, second differential amplification unipolar transistor of above-mentioned first, second pull-up resistor positive output end and as the opposing party's negative lead-out terminal;

Adjunct circuit, it is made of first, second source follower circuit with first, second source follower unipolar transistor, and the grid of this first, second source follower unipolar transistor is connected on above-mentioned positive output end and the above-mentioned negative lead-out terminal;

The suction-type constant current source, it makes the source current of above-mentioned first, second differential amplification unipolar transistor and is steady current; And

Power level displacement diode transistor, it makes the power level displacement to above-mentioned differential enlarging section,

Wherein, make above-mentioned suction-type constant current source and above-mentioned power level displacement diode transistor additional have the function of dc offset voltage compensation is exported in the change of the threshold voltage of the unipolar transistor in above-mentioned differential enlarging section and the above-mentioned adjunct circuit.

14. sensor base plate according to claim 13 is characterized in that,

Grid is being connected the above-mentioned first negative feedback source resistance between as the source electrode of the above-mentioned first differential amplification unipolar transistor of normal phase input end of this amplifying circuit and suction-type constant current source terminal, between the drain electrode of the above-mentioned first differential amplification unipolar transistor and the first polarity power terminal, connect above-mentioned first pull-up resistor

Grid is being connected the above-mentioned second negative feedback source resistance between as the source electrode of the above-mentioned second differential amplification unipolar transistor of negative-phase input of this amplifying circuit and suction-type constant current source terminal, between the drain electrode of the above-mentioned second differential amplification unipolar transistor and the above-mentioned first polarity power terminal, connect above-mentioned second pull-up resistor

With the drain electrode link of the above-mentioned first differential amplification unipolar transistor of above-mentioned first pull-up resistor negative lead-out terminal as above-mentioned differential enlarging section,

With the drain electrode link of the above-mentioned second differential amplification unipolar transistor of above-mentioned second pull-up resistor positive output end as above-mentioned differential enlarging section,

The grid that connects the above-mentioned first source follower unipolar transistor on the negative lead-out terminal of above-mentioned differential enlarging section, the drain electrode of this first source follower unipolar transistor are connected on second first polarity power,

On the source electrode of the above-mentioned first source follower unipolar transistor of first lead-out terminal that becomes above-mentioned adjunct circuit, connect the first source follower load constant current source as the key element of above-mentioned adjunct circuit, the grid that on positive output end of above-mentioned differential enlarging section, connects the above-mentioned second source follower unipolar transistor, the drain electrode of this second source follower unipolar transistor is connected on above-mentioned second first polarity power

On the source electrode of the above-mentioned second source follower unipolar transistor of second lead-out terminal that becomes above-mentioned adjunct circuit, connect the second source follower load constant current source as the key element of above-mentioned adjunct circuit, connect the power level displacement diode unipolar transistor that grid is connected with drain electrode between the above-mentioned first polarity power terminal of first polarity power first and above-mentioned differential enlarging section and be forward bias

Above-mentioned suction-type constant current source has constant current source output unipolar transistor, steady current is set resistance, constant current source level shift unipolar transistor and constant current source level shift transistor biasing constant current source,

Between second polarity power of the source electrode of above-mentioned constant current source output unipolar transistor and first, connect above-mentioned steady current and set resistance, the drain electrode of above-mentioned constant current source output unipolar transistor is connected on the suction-type constant current source terminal of above-mentioned differential enlarging section, the grid of above-mentioned constant current source output unipolar transistor and the source electrode of above-mentioned constant current source level shift unipolar transistor are connected on the above-mentioned constant current source level shift transistor biasing constant current source

On the grid of above-mentioned constant current source level shift unipolar transistor, connect constant-current source circuit gate bias power supply,

In the drain electrode of above-mentioned constant current source level shift unipolar transistor, connect the 3rd first polarity power.

15. sensor base plate according to claim 14 is characterized in that,

Replace above-mentioned first, second negative feedback with source resistance application strings be connected in parallel limited (comprising 0) diode transistor and first, second negative feedback source impedance of constituting with the diode transistor block, wherein, above-mentioned diode transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode

Replace above-mentioned first, second pull-up resistor and application strings is connected in parallel limited diode transistor and first, second load of constituting with the diode transistor block, wherein, above-mentioned diode transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode

Replace above-mentioned each steady current to set resistance and application strings is connected in parallel limited diode transistor and the suction steady current that constitutes is set with the diode transistor block, wherein, above-mentioned diode transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode.

16. sensor base plate according to claim 15 is characterized in that,

Above-mentioned power level displacement diode unipolar transistor is divided into first, second power level displacement diode unipolar transistor, and is connected to above-mentioned first, second loaded impedance with on the diode transistor block as load elements respectively.

17. sensor base plate according to claim 15 is characterized in that,

Remove the second source follower load constant current source of above-mentioned second source follower circuit,

Connect between the source electrode of above-mentioned first, second source follower unipolar transistor as the full-wave rectification lead-out terminal, between above-mentioned full-wave rectification lead-out terminal and ground wire, be connected voltage and keep electric capacity,

Make above-mentioned adjunct circuit become full-wave rectifying circuit.

18. sensor base plate according to claim 15 is characterized in that,

Remove first, second source follower load constant current source of above-mentioned first, second source follower circuit,

Connect between the source electrode of above-mentioned first, second source follower unipolar transistor and keep lead-out terminal, keep connecting between lead-out terminal and the ground wire voltage at above-mentioned peak value and keep electric capacity as peak value, and

Have switch, this switch makes above-mentioned peak value keep lead-out terminal to be connected off and on the peak value hold reset bias voltage by the driving of switch drive pulse signal source,

Make above-mentioned adjunct circuit become the peak holding circuit that band resets.

19. sensor base plate according to claim 13 is characterized in that,

Above-mentioned differential enlarging section, replace above-mentioned first, second negative feedback to have source resistance between the source electrode that is connected above-mentioned first, second differential amplification unipolar transistor with source resistance, and with the source electrode of above-mentioned first, second differential amplification unipolar transistor as first, second suction-type constant current source terminal

Above-mentioned suction-type constant current source has first, second constant current source output unipolar transistor, first, second steady current is set resistance, constant current source level shift unipolar transistor and constant current source level shift transistor biasing constant current source,

Between second polarity power of the source electrode that drain electrode is connected above-mentioned first constant current source output unipolar transistor on the above-mentioned first suction-type constant current source terminal and first, connect above-mentioned first steady current and set resistance,

Between second polarity power of the source electrode that drain electrode is connected above-mentioned second constant current source output unipolar transistor on the above-mentioned second suction-type constant current source terminal and above-mentioned first, connect second steady current and set resistance,

On above-mentioned constant current source level shift transistor biasing constant current source, connect each grid of above-mentioned first, second constant current source output unipolar transistor and the source electrode of above-mentioned constant current source level shift unipolar transistor.

20. sensor base plate according to claim 13 is characterized in that,

Above-mentioned suction-type constant current source has constant current source level shift unipolar transistor, the second benchmark steady current is set resistance, steady current setting diode unipolar transistor and first mirror currents output unipolar transistor,

Above-mentioned adjunct circuit has above-mentioned first, second source follower unipolar transistor and second, third mirror currents output unipolar transistor,

On the source electrode of above-mentioned constant current source level shift unipolar transistor, connect the end that the above-mentioned second benchmark steady current is set resistance,

The above-mentioned steady current that is connected to become the input terminal of current mirroring circuit on the other end of above-mentioned second benchmark steady current setting resistance is set the grid and the drain electrode of diode unipolar transistor, and the above-mentioned steady current that is connected to become the common terminal of above-mentioned current mirroring circuit on first second polarity power is set the source electrode of diode unipolar transistor

On the suction-type constant current source terminal of above-mentioned differential enlarging section, connect the drain electrode of above-mentioned first mirror currents output unipolar transistor, the grid of above-mentioned first mirror currents output unipolar transistor is connected on the input terminal of above-mentioned current mirroring circuit, the source electrode of above-mentioned first mirror currents output unipolar transistor is connected on the common terminal of above-mentioned current mirroring circuit

On the source electrode of the above-mentioned first source follower unipolar transistor, connect the drain electrode of above-mentioned second mirror currents output unipolar transistor, the grid of above-mentioned second mirror currents output unipolar transistor is connected on the input terminal of above-mentioned current mirroring circuit, the source electrode of above-mentioned second mirror currents output unipolar transistor is connected on the common terminal of above-mentioned current mirroring circuit

On the source electrode of the above-mentioned second source follower unipolar transistor, connect the drain electrode of above-mentioned the 3rd mirror currents output unipolar transistor, the grid of above-mentioned the 3rd mirror currents output unipolar transistor is connected on the input terminal of above-mentioned current mirroring circuit, and the source electrode of above-mentioned the 3rd mirror currents being exported unipolar transistor is connected on the common terminal of above-mentioned current mirroring circuit.

21. sensor base plate according to claim 20 is characterized in that,

Remove above-mentioned the 3rd mirror currents output unipolar transistor,

Connect between the source electrode of above-mentioned first, second source follower unipolar transistor as the full-wave rectification lead-out terminal, between above-mentioned full-wave rectification lead-out terminal and ground wire, be connected voltage and keep electric capacity,

Make above-mentioned adjunct circuit become full-wave rectifying circuit.

22. sensor base plate according to claim 20 is characterized in that,

Remove above-mentioned second, third mirror currents output unipolar transistor,

Connect between the source electrode of above-mentioned first, second source follower unipolar transistor and keep lead-out terminal, between above-mentioned peak value keeps lead-out terminal and ground wire, is connected voltage maintenance electric capacity as peak value, and

Have switch, this switch makes above-mentioned peak value keep lead-out terminal to be connected off and on the peak value hold reset bias voltage by the driving of switch drive pulse signal source,

Make above-mentioned adjunct circuit become the peak holding circuit that band resets.

23. sensor base plate according to claim 20 is characterized in that,

Replace above-mentioned first, second negative feedback source resistance, application strings be connected in parallel limited (comprising 0) diode transistor and first, second negative feedback source impedance of constituting with the diode transistor block, wherein, above-mentioned diode transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode

Replace above-mentioned first, second pull-up resistor, application strings be connected in parallel limited diode transistor and first, second load of constituting with the diode transistor block, wherein, above-mentioned diode transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode

Replace the above-mentioned second benchmark steady current to set resistance, application strings is connected in parallel limited diode transistor and the benchmark steady current that constitutes is set with the diode transistor block, wherein, above-mentioned diode transistor connects grid and drain electrode and makes the transistor that becomes diode between drain electrode and source electrode.

24. sensor base plate according to claim 23 is characterized in that,

Above-mentioned power level displacement diode unipolar transistor is divided into first, second power level displacement diode unipolar transistor, is connected to above-mentioned first, second loaded impedance with on the diode transistor block as load elements respectively.

25. sensor base plate according to claim 23 is characterized in that,

Remove above-mentioned the 3rd mirror currents output unipolar transistor,

Connect between the source electrode of above-mentioned first, second source follower unipolar transistor as the full-wave rectification lead-out terminal, between above-mentioned full-wave rectification lead-out terminal and ground wire, be connected voltage and keep electric capacity,

Make above-mentioned adjunct circuit become full-wave rectifying circuit.

26. sensor base plate according to claim 23 is characterized in that,

Remove above-mentioned second, third mirror currents output unipolar transistor,

Connect between the source electrode of above-mentioned first, second source follower unipolar transistor and keep lead-out terminal, between above-mentioned peak value keeps lead-out terminal and ground wire, is connected voltage maintenance electric capacity as peak value, and

Have switch, this switch makes above-mentioned peak value keep lead-out terminal to be connected off and on the peak value hold reset bias voltage by the driving of switch drive pulse signal source,

Make above-mentioned adjunct circuit become the peak holding circuit that band resets.

27. sensor base plate according to claim 13 is characterized in that,

Replace having the above-mentioned adjunct circuit of first, second source follower circuit, used the adjunct circuit that is made of full-wave rectifying circuit, first, second input terminal of this full-wave rectifying circuit is connected on positive output end of above-mentioned differential enlarging section, the negative lead-out terminal.

28. sensor base plate according to claim 13 is characterized in that,

Replace having the above-mentioned adjunct circuit of first, second source follower circuit, used the adjunct circuit that the peak holding circuit that resetted by band constitutes, first, second input terminal of the peak holding circuit that this band resets is connected on positive output end of above-mentioned differential enlarging section, the negative lead-out terminal.

29. sensor base plate according to claim 13 is characterized in that,

Remove the second source follower load constant current source of above-mentioned second source follower circuit,

Connect between the source electrode of above-mentioned first, second source follower unipolar transistor as the full-wave rectification lead-out terminal, between above-mentioned full-wave rectification lead-out terminal and ground wire, be connected voltage and keep electric capacity,

Make above-mentioned adjunct circuit become full-wave rectifying circuit.

30. sensor base plate according to claim 13 is characterized in that,

Remove first, second source follower load constant current source of above-mentioned first, second source follower circuit,

Connect between the source electrode of above-mentioned first, second source follower unipolar transistor and keep lead-out terminal, between above-mentioned peak value keeps lead-out terminal and ground wire, is connected voltage maintenance electric capacity as peak value, and

Have switch, this switch makes above-mentioned peak value keep lead-out terminal to be connected off and on the peak value hold reset bias voltage by the driving of switch drive pulse signal source,

Make above-mentioned adjunct circuit become the peak holding circuit that band resets.

31. sensor base plate according to claim 13 is characterized in that,

The above-mentioned resistive element that replaces part or all, the diode transistor block of having used connection in series-parallel connection limited (comprise 0) diode transistor corresponding and having constituted with the function of each resistive element, wherein, above-mentioned diode transistor is to connect grid and drain electrode and make the transistor that becomes diode between drain electrode and source electrode.

32. testing fixture, make sensor base plate with non-contacting form and can electromagnetic coupled ground with check that object substrate is opposed, make the inspection object electrode and the sensor electrode electromagnetic coupled on the sensor substrate of any row of above-mentioned inspection object substrate check above-mentioned inspection object substrate, wherein, the sensor substrate be have the sensor electrode that is arranged and to the signal acquisition of each sensor electrode that amplify at least with substrate each sensor electrode corresponding sensor circuit, above-mentioned inspection object substrate is a substrate of checking that the object electrode is aligned to array-like and can drives by each row, this testing fixture is characterised in that

As the sensor substrate, used each the described sensor base plate in the claim 1,8,13.

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