CN210431390U

CN210431390U - Buffer type analog-to-digital converter and integrated circuit

Info

Publication number: CN210431390U
Application number: CN201921221580.1U
Authority: CN
Inventors: 夏书香; 许建超
Original assignee: SHENZHEN RENERGY TECHNOLOGY CO LTD
Current assignee: SHENZHEN RENERGY TECHNOLOGY CO LTD
Priority date: 2019-07-29
Filing date: 2019-07-29
Publication date: 2020-04-28
Anticipated expiration: 2029-07-29

Abstract

A buffer type analog-to-digital converter and an integrated circuit are provided, the buffer type analog-to-digital converter comprises an input buffer unit and an analog-to-digital conversion unit, the input buffer unit comprises a main source follower and an auxiliary source follower, and the auxiliary source follower is used for eliminating the channel length modulation effect of the main source follower; the input of the analog-to-digital conversion unit is connected with the output of the input buffer unit, and the analog-to-digital conversion unit is used for converting the analog signal output by the input buffer unit into a digital signal and outputting the digital signal. The auxiliary source follower can eliminate the channel length modulation effect of the main source follower, thereby greatly improving the linearity and the gain precision of the buffer type analog-to-digital converter.

Description

Buffer type analog-to-digital converter and integrated circuit

Technical Field

The application belongs to the technical field of CMOS (complementary metal oxide semiconductor) integrated devices, and particularly relates to a buffer type analog-to-digital converter and an integrated circuit.

Background

An Analog-to-Digital Converter (ADC) is used to convert an Analog signal into a Digital signal representing a proportional voltage value. Analog-to-digital converters are commonly used in many applications ranging from direct current signal and low frequency sensor applications to high frequency analog-to-digital converters for wireless communications. The analog signal is continuous in the time domain, so it can be converted into a series of digital signals that are continuous in time. However, the actual analog-to-digital converter cannot perform full real-time conversion, so that the input signal must be kept constant by some external method during one conversion. A sample-and-hold circuit is commonly used, and in most cases, an input analog voltage can be stored by using a capacitor, and the capacitor is connected to and disconnected from an input signal by a switch or a gate circuit.

However, the sampling switch in the internal sample-and-hold circuit of the analog-to-digital converter has a charge-collapsing effect, which has a charge-injection effect on the signal source, and this results in a decrease in the linearity of the analog-to-digital converter. On the other hand, the effective input impedance of the sample-and-hold circuit may limit the external interface of the analog-to-digital converter to have a low impedance input, which limits the application of the analog-to-digital converter. To solve this problem, it is usually necessary to add an input buffer circuit in the front end of the analog-to-digital converter to isolate the signal source and the sampling capacitor, so as to provide high input impedance.

Currently common input buffer structures include: 1. based on an operational amplifier, a closed loop feedback structure with unit gain is formed. The structure has the input signal required to provide a proper bias voltage, namely, conditions are provided for the sensor. In addition, the operational amplifier has a complex structure and high noise, and the performance of the analog-to-digital converter is limited by the noise of the operational amplifier, so that the buffer type analog-to-digital converter needs high cost to have good performance. 2. A source-follower (source-follower) structure based on a single MOS tube. The structure exists because of an open-loop structure and no feedback, so that the output impedance of the structure is a limited value (generally about 1k omega, depending on the current magnitude), and is limited by the gain precision and the linearity of the channel length modulation effect. 3. A source follower structure based on bipolar transistor devices. The structure needs the support of a BiCMOS special process, the common CMOS process is difficult to realize, and the BiCMOS process is very expensive and high in cost. In addition, the base of the bipolar transistor has to carry current, which causes the input impedance to be not infinite, resulting in poor impedance isolation.

Disclosure of Invention

The application aims to provide a buffer analog-to-digital converter and an integrated circuit, and aims to solve the problem that the traditional buffer analog-to-digital converter formed by a single MOS transistor is limited to the general gain accuracy and linearity of the channel length modulation effect.

A first aspect of an embodiment of the present application provides a buffer type analog-to-digital converter, an input buffer unit, and an analog-to-digital conversion unit, where:

the input buffer unit comprises a first current source, a first main source follower and a first auxiliary source follower, wherein the first current source, the first main source follower and the first auxiliary source follower are connected in series in the same direction or in an opposite direction between a power supply and a common potential, the first main source follower is composed of a first transistor, the first auxiliary source follower is composed of at least one second transistor, grid electrodes of the first transistor and the second transistor are connected in common and used as the input of the buffer type analog-to-digital converter to be connected with an analog signal, a common connection point between the first current source and the first main source follower is used as the output of the input buffer unit to output the buffered analog signal, and the first auxiliary source follower is used for eliminating the channel length modulation effect of the first main source follower;

the input of the analog-to-digital conversion unit is connected with the output of the input buffer unit, and the analog-to-digital conversion unit is used for converting the analog signal output by the input buffer unit into a digital signal and outputting the digital signal.

A second aspect of embodiments of the present application provides an integrated circuit comprising a buffered analog-to-digital converter as described above.

The first-stage input buffer stage in the buffer type analog-to-digital converter utilizes different transistors to form two source followers, wherein one source follower is used as a main source follower, the other source follower is used as an auxiliary source follower, and the auxiliary source follower is used for eliminating the channel length modulation effect of the main source follower, so that the linearity and the gain precision of the buffer type analog-to-digital converter are greatly improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1A and 1B are schematic diagrams of two structures of a buffer type analog-to-digital converter according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an exemplary circuit of a first embodiment of the buffer ADC shown in FIG. 1A;

FIG. 3 is a schematic diagram of an exemplary circuit of an input buffer unit in the second embodiment of the buffer ADC shown in FIG. 1A;

FIG. 4 is a schematic diagram of an exemplary circuit of a third embodiment of the buffer ADC shown in FIG. 1B;

FIG. 5 is a schematic diagram of an exemplary circuit of an input buffer unit in the fourth embodiment of the buffer ADC shown in FIG. 1B;

FIG. 6 is a schematic diagram of an exemplary circuit of a fifth embodiment of the buffer ADC shown in FIG. 1A;

FIG. 7 is a schematic diagram of an exemplary circuit of an input buffer unit in a sixth embodiment of the buffer ADC shown in FIG. 1A;

FIG. 8 is a schematic diagram of a conventional buffer ADC with a source follower structure and a single PMOS transistor, and a waveform diagram of input/output signals thereof;

FIG. 9 is a schematic diagram of an input buffer unit of the buffer ADC shown in FIG. 2 and input/output signal waveforms thereof;

fig. 10 is a schematic circuit diagram of an example of a first differential buffer type analog-to-digital converter provided in an embodiment of the present application;

fig. 11 is a schematic circuit diagram of an example of a second differential buffer type analog-to-digital converter provided in an embodiment of the present application;

fig. 12 is a schematic circuit diagram of an example of a third differential buffer analog-to-digital converter according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

Referring to fig. 1A and 1B, the buffer adc according to the embodiment of the present invention includes an input buffer unit 10 and an adc unit 20, where the input buffer unit 10 includes a first current source Iss connected in series in the same direction (see fig. 1A) or in series in reverse (see fig. 1B) between a power supply Vcc and a common potential Vss, a first master follower 100 formed by a first transistor, and a first slave follower 200 formed by at least one second transistor, gates of the first transistor and the second transistor are connected in common as an input of the buffer adc for receiving an analog signal vin, a common node between the first current source Iss and the first master follower 100 is used as an output of the input buffer unit 10 for outputting a buffered analog signal vbuffer, and the first slave follower 200 is used for eliminating a channel length modulation effect of the first master follower 100. The input of the analog-to-digital conversion unit 20 is connected to the output of the input buffer unit 10, and the analog-to-digital conversion unit 20 is configured to convert the analog signal output by the input buffer unit 10 into a digital signal Dout for output.

The scheme is an improvement on the basis of an input buffer unit 10 formed by a single MOS tube, wherein the first main source follower 100 is also a single transistor, and the first auxiliary source follower 200 is a single or a plurality of transistors connected in series. And the first current source Iss, the first primary source follower 100 and the first secondary source follower 200 are connected in series in sequence, either forward or reverse, between the power supply Vcc and a common potential Vss (e.g., ground), depending on whether the transistor is P-type or N-type. The input buffer unit 10 uses different transistors to form two source followers, one of which is used as a main source follower, and the other is used as an auxiliary source follower, and the auxiliary source follower is used for eliminating the channel length modulation effect of the main source follower, so that the linearity and the gain precision of the buffer type analog-to-digital converter are greatly improved.

An embodiment of the input buffer unit 10 is as follows:

the first embodiment is as follows:

referring to fig. 2, the first transistor and the second transistor in the input buffer unit 10 are PMOS transistors, and then the first current source Iss, the first main source follower 100 and the first auxiliary source follower 200 are sequentially connected in series between the power supply Vcc and the common potential Vss, the source of the first transistor is connected to the power supply Vcc through the first current source Iss, and at least one second transistor is connected in series in the same direction and then connected between the drain of the first transistor and the common potential Vss. Specifically, the first transistor is a PMOS transistor PM1, the second transistor is a PMOS transistor PM0, the substrate of the PMOS transistor PM0 is connected to the source thereof, and the drain of the PMOS transistor PM0 is grounded; the substrate of the PMOS transistor PM1 is connected with the source electrode thereof, and the drain electrode of the PMOS transistor PM1 is connected with the source electrode of the PMOS transistor PM 0. The first current source Iss provides a bias current, which is placed between the power supply Vcc and the source of the PMOS transistor PM1, in the direction from the power supply Vcc to the PMOS transistor PM 1. An input signal vin is simultaneously applied to the input gates of the PMOS transistor PM0 and the PMOS transistor PM1, and an output signal vbuffer is taken from the source of the PMOS transistor PM 1.

Example two:

referring to fig. 3, the input buffer unit 10 of the present embodiment is extended to a series structure of a plurality of PMOS source followers based on the first embodiment, wherein the first transistor PMOS transistor PM1 forms a "main" source follower, the remaining second transistors PMOS transistors PM _ a0 to PM _ an together form a first auxiliary source follower 200, the gates of the PMOS transistor PM1 and the PMOS transistors PM _ a0 to PM _ an are connected in common as the input of the buffer adc, and the output signal vbuffer is taken from the source of the PMOS transistor PM1 as the output of the buffer adc.

Example three:

referring to fig. 4, the first transistor and the second transistor of the input buffer unit 10 are NMOS transistors, the first auxiliary source follower 200, the first main source follower 100, and the first current source Iss are sequentially connected in series between the power supply Vcc and the common potential Vss, the source of the first transistor is connected to the common potential Vss through the first current source Iss, and at least one second transistor is connected in series in the same direction between the drain of the first transistor and the power supply Vcc. Specifically, the first transistor is an NMOS transistor NM1, the second transistor is an NMOS transistor NM0, the substrate of the NMOS transistor NM0 is connected to the source thereof, and the drain of the NMOS transistor NM0 is connected to the power supply Vcc; the substrate of the NMOS transistor NM1 is connected to the source thereof, and the drain of the NMOS transistor NM1 is connected to the source of the NMOS transistor NM 0. The first current source Iss supplies a bias current, which is placed between the common potential Vss and the source of the NMOS transistor NM1, in a direction from the power supply Vcc to the NMOS transistor NM1 to the common potential Vss. The input signal vin is applied to the input gates of the NMOS transistor NM0 and the NMOS transistor NM1, and the output signal vbuffer is taken from the source of the NMOS transistor NM 1. In this embodiment, a series structure formed by 2 NMOS source followers is completely dual to the 2 PMOS transistor structures of the first embodiment. The common mode level of the input signal vin may be high at this time, for example, directly from the supply voltage.

Example four:

referring to fig. 5, the input buffer unit 10 of the present embodiment is extended to a series structure of a plurality of NMOS source followers based on the third embodiment, in which the first transistor NMOS 1 forms a "main" source follower, the remaining second transistors NMOS _ a 0-NM _ an form a first auxiliary source follower 200, the gates of the NMOS NM1 and NMOS NM _ a 0-NM _ an are connected in common as the input of the buffer adc, and the output signal vbuffer is taken from the source of the NMOS NM1 as the output of the buffer adc. The series structure of the NMOS source followers in this embodiment is completely dual to the series structure of the PMOS source followers in the second embodiment.

Example five:

referring to fig. 6, the input buffer unit 10 of the present embodiment is extended to add a dc level shift module 300 on the basis of any one of the first to fourth embodiments. In this embodiment, the level shift module 300 is connected between the first current source Iss and the first master follower 100, a common node between the level shift module 300 and the first current source Iss is used as an output of the buffer type analog-to-digital converter, and the level shift module 300 is used to increase an output level shift. The main and first auxiliary source followers 200 are not limited to PMOS transistors or NMOS transistors, and the number of MOS transistors of the first auxiliary source follower 200 is also not limited.

In the example shown in fig. 6, the dc level shifting module 300 is a resistor R0 serially connected between the output and the PMOS transistor PM1 of the first master follower, which can solve the problem that the output level shift is not enough due to the PMOS transistor PM1 alone, and at this time, the addition of the level shifting module 300 can further increase the dc level shift without affecting the signal quality. Sometimes, this level shifting module 300 is necessary to let the gain amplifying unit 20 of the second stage operate at a comfortable bias voltage vbias. In other embodiments, the resistor R0 may be replaced by a circuit module, and regardless of the specific implementation of the circuit module, it is within the scope of the present disclosure as long as its function is to increase the dc level shift without affecting the signal quality.

Example six:

referring to fig. 7, the input buffer unit 10 of the present embodiment is extended to add a dc level shift module 400 based on any one of the first to fourth embodiments. In this embodiment, the level shift module 400 is connected between the first main source follower 100 and the first auxiliary source follower 200, and the level shift module 400 is used to increase the output level shift. The main and first auxiliary source followers 200 are not limited to PMOS transistors or NMOS transistors, and the number of MOS transistors of the first auxiliary source follower 200 is also not limited. In addition, the scheme in the present embodiment may be used in combination with the scheme in the fifth embodiment.

In the example shown in fig. 7, the dc level shifting block 400 is a resistor R1, and is connected in series between the PMOS transistor PM1 of the first main source follower 100 and the PMOS transistor PM0 of the first auxiliary source follower 200. The problem that the output level shift is insufficient due to the PMOS transistor PM1 alone can be solved, and the addition of the level shift module 400 can further increase the dc level shift without affecting the signal quality. In other embodiments, the resistor may be replaced by a circuit module, and regardless of the specific implementation of the circuit module, it is within the protection scope of the present solution as long as its function is to increase the dc level shift without affecting the signal quality.

It should be noted that, although fig. 6 and 7 illustrate a 2-stage MOS source follower series structure as an example, the structure is applicable to a multi-stage MOS source follower series structure, and the insertion of a level shift module in these structures falls within the protection scope.

Referring to fig. 2, the first transistor and the second transistor in the input buffer unit 10 are PMOS transistors, and the first slave follower 200 is a PMOS transistor, for example, to illustrate the related principle. Specifically, the core part of the buffer analog-to-digital converter adopts 2 PMOS tubes PM0 and PM1 and a first current source Iss. Therefore, from the structural point of view, the two PMOS transistors PM0 and PM1 both form a source follower, but their inputs are connected in parallel and their outputs are connected "in series". The PMOS pipe PM1 forms a main source follower, and the PMOS pipe PM0 forms an auxiliary source follower; the existence of the PMOS pipe PM0 carries out linearization processing on the PMOS pipe PM1, so that the linearity of the PMOS pipe PM1 is greatly improved, and the output signal vbuffer is generated by the PMOS pipe PM 1. Due to the ingenious connection relation, the linearity is greatly improved, the gain accuracy is greatly improved, and the performances in other aspects (such as the consumption of output impedance, noise, power consumption and voltage margin) are equivalent to those of a common single PMOS tube source follower. This is a very rare phenomenon in the field of analog circuit design, because in the field of analog circuit design, various trade-offs (tradeoff) are filled, and usually one circuit architecture is superior to another in performance in some respect, often at the expense of performance in other respect.

In the structure of fig. 2, PMOS transistor PM0 and PMOS transistor PM1 need to be carefully designed and dimensioned to ensure that 2 MOS transistors are operated in the saturation region, which is the basic requirement for this structure to function effectively. The difficulty of making the PMOS transistor PM0 work in the saturation region is that it must satisfy the following conditions:

|Vds1|≥(|Vgs1|-|Vth1|)+margin

vds1, Vgs1, Vth1 and margin are respectively the drain-source voltage, gate-source voltage, threshold voltage and voltage margin of a PMOS tube PM1, and margin is generally about 100-200 mV. Assuming that the common mode level of the input signal yin is 0, the above equation is further written as:

vbuffer-vt≥vbuffer-|Vth1|+margin

further comprises the following steps:

|Vth1|≥Vt+margin

since vt is | Vgs0| Vth0| + Vod0, vt is the drain of PMOS transistor PM1 and PMOThe source electrode common junction voltage of the S tube PM0, Vgs0, Vth0 and Vod0 are the gate-source voltage, the threshold voltage and the overdrive voltage of the PMOS tube PM0,

thus, the above equation is further written as:

|Vth1|-|Vth0|≥Vod0+margin≈Vod0+100mV

this means that the threshold voltage of PMOS transistor PM1 must be larger than the threshold voltage of PMOS transistor PM0 by Vod0+ margin, i.e., at least over 100 mV. To achieve this goal, there are at least 2 possible solutions:

the first method comprises the following steps: the process will generally provide a variety of threshold MOS transistor options. The PM1 can be selected as a high-threshold transistor MOS and the PM0 as a low-threshold transistor MOS, which can easily achieve the goal.

And the second method comprises the following steps: by fine and smart sizing. When the W/L (W is the width of the conductive channel and L is the length of the conductive channel) of the PMOS transistor PM0 is large enough to operate in the subthreshold region, Vod0 is very small (e.g., 50 mV). Meanwhile, let L of the PMOS transistor PM0 be the minimum length in the current process (for example, for a 0.35um CMOS process, L is 0.35um), and the smaller threshold voltage is usually brought about by the lrin. In addition, the W/L of the PMOS transistor PM1 is made as small as possible, and L is made as large as possible under the current process (for example, for a 0.35um CMOS process, L is made 4um), so that Vod1 of the PMOS transistor PM1 is large enough, the channel length modulation effect of the PMOS transistor PM1 is small enough, and the linearity is good as possible. And a larger L for the PMOS transistor PM1 generally results in a larger threshold voltage. In this way, by making | Vth1| as large as possible, | Vth0| as small as possible, and Vod0 as small as possible, the above equation is satisfied, and the effect of the structure of the present scheme is exerted, and the linearity is further improved.

As a further analysis follows, the proposed structure of the solution can greatly improve the linearity and gain accuracy, and it is necessary to examine the problem through a comparative analysis.

Fig. 8 shows an input buffer cell 10 of a source follower structure formed of a conventional single PMOS transistor, with a substrate connected to a source. The gain from input to output is:

wherein gm is transconductance of the PMOS transistor PM1, and gds is output intrinsic admittance of the PMOS transistor PM 1. gm/gds is called the intrinsic gain of the MOS transistor, and usually this value is around 100, i.e. gds ≈ gm/100, which is usually negligible compared to gm, so that Av is approximately equal to 1. If used in high precision and high linearity applications, the effect of gds cannot be ignored. gds influences what characterizes the channel length modulation effect, and in this structure gds determines the accuracy and linearity of the gain completely. Note the definition of gds:

gds is therefore a function of vds (drain-source voltage of the MOS transistor). For the source follower of fig. 8, since vds ≈ vbuffer-0 ≈ vin, the gain Av is still actually a weak function of the input signal due to the influence of gds:

this is nonlinear and harmonic distortion is generated. Design and simulation results on a typical CMOS process show that the components of the 2 nd harmonic and the 3 rd harmonic of the input buffer unit 10 of the source follower structure formed by the traditional single PMOS tube are difficult to be lower than-80 dBc, which means that the effective digit (precision index, defined as ENOB ═ SNDR-1.76)/6.02) of a measurement system based on the input buffer unit 10 of the source follower structure of the single PMOS tube is at most about 13bits, and the input buffer unit is far from enough for high-precision application.

From an analysis of fig. 8, we know that the bottleneck is gds. It is the proposal of our patent that almost completely eliminates the effect of gds.

As shown in fig. 9, the input signal vin passes through 2 source followers, which generate vbuffer and vt, respectively. We call PMOS transistor PM1 first master source follower 100 and PMOS transistor PM0 first slave source follower 200. vbuffer and vt are almost exactly equal to the input signal vin, and the magnitude of the error is the harmonic component (around-80 dBc, i.e., around one ten thousandth of the signal itself).

Further, note the PMOS transistor PM1, which

vds＝vbuffer-vt≈vin+o(vin)-[vin+o(vin)]＝o(vin)≈0

Where mathematical notation is used, a small o means "much less than", e.g. o (vin) means a quantity much less than vin. Therefore, the source and drain of the PMOS transistor PM1 synchronously follow the input signal swing, but are almost 0 (fluctuation is about ten-thousandth of the input signal) in terms of their difference, so that the change in vds is not felt. Since vds is not sensed, gds of the PMOS transistor PM1 is also almost equal to 0. Thus, for the circuit structure of the present application:

the nonlinear components are greatly reduced, and therefore harmonic distortion is greatly reduced. Design and simulation results on the same CMOS process show that components of 2 th harmonic and 3 rd harmonic of the input buffer unit 10 adopting the new source follower structure provided by the application can be less than-120 dBc, which means that the highest effective digit of a measurement system of the input buffer unit 10 based on the source follower can reach a level close to 20bits, and the measurement system is enough for high-precision application occasions (generally, about 16bits is common).

On the other hand, the gain accuracy is an indicator to be considered, which is also crucial for high-accuracy measurement systems. In practice, each stage (buffer isolation, amplification, filtering, analog-to-digital conversion ….) in the signal processing chain introduces a gain, and the gain of each stage is affected by PVT (process variation, power supply fluctuation, temperature), and is often very complicated or even difficult to accurately depict. In the influence of PVT:

usually the influence of the supply ripple V can be solved by design, for example by placing it under LDO (Low dropout linear regulator) to keep V constant.

The influence of the process deviation P is usually solved by a calibration link before the chip/complete machine leaves a factory. The calibration is to record the gain value Av0 before the chip/complete machine leaves the factory and store it in the nonvolatile memory of the chip, which is called calibration. In normal use, the actual gain Av is calibrated with Av 0. In this way, sheet-to-sheet process variation is eliminated;

the influence of the temperature T is to make the gain of the circuit insensitive to the temperature through an excellent design level and a smart circuit structure.

For the source follower structure input buffer unit 10 formed by the conventional single PMOS transistor shown in fig. 8, the gain is:

wherein

gds (PVT) and gm (PVT) are both strongly temperature dependent, ranging from-40 ℃ to +85 ℃, with gds (PVT)/gm (PVT) variations often being more than 2 times higher. As before, a typical value for gds/gm is approximately 1%, and a typical value for Av is approximately 0.99; however, if considering the temperature variation of gds/gm, the variation of Av with temperature is as high as 1% or more, which brings a large measurement error, so that the high-precision measurement system becomes inaccurate. Since gds (pvt)/gm (pvt) is not only related to T but also to P, this means that the temperature curves of gds (pvt)/gm (pvt) may be different for each chip, making the idea of considering temperature compensation impractical (requiring temperature compensation for each, which is extremely expensive).

However, for the patent scheme proposed in the present application, the gain is:

wherein

Assuming that x itself has a value of about 1%, the variation over the full temperature range is also about 1%. As before, o (x) is an amount that is about 40dB (about 100 times) smaller than x, so that o (x) itself has a value of about 0.01%, and changes in the whole temperature range are also about 0.01% in order of magnitude, which translates to a temperature coefficient of about 8 ppm/c, which is the top level from the literature currently available, and meets the application of most high-precision measurement systems.

This application is with the source follower that 2 MOS pipes constitute, and the input is parallelly connected together, and the output "is established ties" together. One of the MOS transistors serves as a first main source follower 100, and the other or more MOS transistors serve as a first auxiliary source follower 200, and the output is taken from the first main source follower 100. The first auxiliary source follower 200 functions to eliminate the channel length modulation effect of the first main source follower 100, thereby greatly improving the linearity and gain accuracy of the input buffer unit 10.

In order to make the MOS transistors of the main and first auxiliary source followers 200 work in the saturation region, the design method adopted is as follows: one is to adopt a design method of a multi-threshold tube; and the other method adopts a more skillful tube size selection method. Both of these methods are described in detail above.

The input buffer unit 10 and the integrated circuit have excellent linearity and extremely accurate gain; the input signal does not need to provide an additional bias voltage vbias (the sensor can directly take ground as a common-mode signal); the circuit is extremely simple, is completely compatible with a CMOS (complementary metal oxide semiconductor) process, and does not need special devices; impedance isolation (high impedance input, low impedance output); other performances (such as noise, power consumption and consumption of voltage margin) are equivalent to those of the common single MOS tube source follower structure. This is a very rare phenomenon in the field of circuit design. In the field of circuit design, various trade-offs (tradeoff) are filled, and one circuit architecture has better performance than another in some aspects, often at the expense of performance in other aspects.

The analog-to-digital conversion unit 20 in the buffer type analog-to-digital converter of the present application has many selectable architectures, and it can achieve better linearity and precision, so the linearity and performance of the buffer type analog-to-digital converter are generally limited by the input buffer 10. The linearity and performance of the input buffer unit 10, which is located at the signal front-end input, will limit the performance of the whole buffer type analog-to-digital converter.

Referring to fig. 1A and fig. 2, in an example, the analog-to-digital conversion unit 20 includes a sample-and-hold circuit 21 and a signal processing circuit 22 that are connected to each other, an input terminal of the sample-and-hold circuit 21 serves as an input of the analog-to-digital conversion unit 20, the sample-and-hold circuit 21 is configured to sample the analog signal vbuffer output by the input buffer unit 10 according to a preset rule and store the analog signal vbuffer as a voltage signal, an output terminal of the signal processing circuit 22 serves as an output of the analog-to-digital conversion unit 20, and the signal processing circuit 22 is configured to convert the voltage signal stored in the sample-and-.

In one example, the sample-and-hold circuit 21 includes a first switch S₁A second switch S₂And a third switch S₃And an energy storage capacitor C_sFirst switch S₁As an input of the sample-and-hold circuit 21, a first switch S₁Second terminal, second switch S₂First terminal and energy storage capacitor C_sIs connected in common with an energy storage capacitor C_sSecond terminal and third switch S₃Is connected to the signal processing circuit 22 as the output terminal of the sample-and-hold circuit 21, and a second switch S₂Second terminal and third switch S₃Is connected to the operating voltage Vcm. The operating voltage Vcm is a common mode voltage, and is mainly used for providing a proper operating level for the subsequent signal processing circuit. In particular, when switch S is on₁And S₃Closed, switch S₂When the circuit is disconnected, the circuit is in a sampling state, and the capacitor C_sThe input analog signal vbuffer output from the input buffer unit 10 is stored. When the switch S₁And S₃Open, switch S₂When closed, the circuit is in a hold state, and the post-stage circuit of the analog-to-digital converter is coupled with the capacitor C_sConverting the stored voltage signal to convert the analog voltage to a digital signal Dout。

The input buffer structure adopted by the invention greatly improves the linearity and the gain precision. Design and simulation results on a typical CMOS process show that components of 2 th harmonic and 3 rd harmonic of a source follower structure input buffer formed by a traditional single MOS tube are hardly lower than < -80dBc, and the variation of gain with temperature is up to +/-1%, which is far from enough for high-precision application. By adopting the input buffer structure, the components of the 2 nd harmonic and the 3 rd harmonic can be < -120dBc, the variation of the gain along with the temperature is as low as +/-0.01 percent, and the input buffer structure is enough for most high-precision systems. Most importantly, this is achieved on a pure CMOS process without any special devices and without the support of an expensive BiCMOS process.

Referring to fig. 10, the present application further discloses a differential buffer type analog-to-digital converter, where the number of input buffer units 10 in the differential buffer type analog-to-digital converter is two, the inputs of the two input buffer units 10 are used to access a pair of differential analog signals vin and vip, and the outputs of the two input buffer units 10 buffer differential analog signals von and vop; the input of the analog-to-digital conversion unit 20 includes a first input and a second input, the first input and the second input of the analog-to-digital conversion unit 20 are respectively connected to the outputs of the two input buffer units 10, and the analog-to-digital conversion unit 20 is further configured to respectively convert the differential analog signals von and vop output by the input buffer units 10 into digital signals out and output the digital signals out. The differential circuit has symmetry and is widely used because of its ability to suppress even harmonics, and most analog-to-digital converter circuits in practical use are in differential (or pseudo-differential) form.

Referring to fig. 11 and 12, the present application discloses that the differential buffer adc further includes a gain amplifying unit 30, a first input end and a second input end of the gain amplifying unit 30 are respectively connected to the outputs of the two input buffer units 10, a first output end and a second output end of the gain amplifying unit 30 are respectively connected to a first input and a second input of the analog-to-digital converting unit 20, and the gain amplifying unit 30 is configured to gain and output the signal output by the input buffer units 10.

Referring to fig. 11, in one embodiment, the gain amplifying unit 30 includes a first operational amplifier A3, a second operational amplifier a4, a first voltage dividing element R21, a second voltage dividing element R22 and a third voltage dividing element R23, a positive phase input terminal of the first operational amplifier A3 is used as a first input terminal vbf _ p of the gain amplifying unit 30, one terminal of the first voltage dividing element R21 is connected to an output terminal of the first operational amplifier A3, the other terminal of the first voltage dividing element R21 is connected to an inverting input terminal of the first operational amplifier A3 and one terminal of the second voltage dividing element R22, the other terminal of the second voltage dividing element R22 is connected to an inverting input terminal of the second operational amplifier a4 and one terminal of the third voltage dividing element R23, a positive phase input terminal of the second operational amplifier a4 is used as a second input terminal vbf _ n of the gain amplifying unit 30, and the other terminal of the third voltage dividing element R23 is connected to an output terminal of the second operational amplifier a4, the output terminal of the first operational amplifier A3 is used as the first output terminal vop of the gain amplifying unit 30, and the output terminal of the second operational amplifier a4 is used as the second output terminal von of the gain amplifying unit 30.

In this embodiment, the gain of the gain amplifying unit 30 is:

the buffer analog-to-digital converter with the gain is suitable for occasions with small input signals, and the input signals are small and need to be amplified to be within the range of the measuring range of the analog-to-digital converter, so that good performance is achieved.

Referring to fig. 12, in one embodiment, the gain amplifying unit 30 includes an operational amplifier a5, a first voltage dividing element R31, a second voltage dividing element R32, a third voltage dividing element R33 and a fourth voltage dividing element R34, wherein one end of the first voltage dividing element R31 is used as a first input end vbf _ p of the gain amplifying unit 30, the other end of the first voltage dividing element R31 is connected to a positive phase input end of the operational amplifier a5, one end of the second voltage dividing element R32 is used as a second input end vbf _ n of the gain amplifying unit 30, the other end of the second voltage dividing element R32 is connected to an inverting input end of the operational amplifier a5, the third voltage dividing element R33 is connected between the positive phase input end and the inverting output end of the operational amplifier a5, the fourth voltage dividing element R34 is connected between the inverting input end and the positive phase output end of the operational amplifier a5, the inverting output end and the non-phase output end of the operational amplifier a5 are respectively used as a first output, A second output terminal vop.

In this embodiment, the gain amplifying unit 30 is an inverting proportional amplifier with a differential structure, and has a gain of

It should be noted that, although the two input buffer units 10 of the differential buffer adc shown in fig. 10 to 12 are illustrated as 2-stage PMOS serial structure, in fact, a differential circuit may be formed for all structures including, but not limited to, embodiments one to six, which all fall within the scope of the present application. The voltage dividing element may be a circuit including at least one of a resistor, a capacitor, an inductor, and a transistor.

The application also provides an integrated circuit comprising the buffer type analog-to-digital converter. The buffer type analog-to-digital converter adopts the input buffer structure, so that the linearity and the gain precision are greatly improved, and the performance of the whole circuit is not limited. Design and simulation results on a typical CMOS process show that components of 2 th harmonic and 3 rd harmonic of a source follower structure input buffer formed by a traditional single PMOS tube are hardly lower than < -80dBc, and the variation of gain with temperature is up to +/-1%, which is far from enough for high-precision application. By adopting the input buffer structure in the application, the components of the 2 nd harmonic and the 3 rd harmonic can be < -120dBc, the gain changes with the temperature as low as +/-0.01 percent, and the input buffer structure is enough for most high-precision systems. The circuit is simple, and the method is realized on a pure CMOS process without any special device or expensive BiCMOS process support. In addition, the sensor also has a level shift function, an input signal does not need to provide extra bias voltage, and the sensor can directly take the ground as a common-mode signal; the input of the circuit is high impedance, the output of the circuit is low impedance, and the input stage impedance isolation is realized.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A buffer type analog-to-digital converter is characterized by an input buffer unit and an analog-to-digital conversion unit, wherein:

the input of the analog-to-digital conversion unit is connected with the output of the input buffer unit, and the analog-to-digital conversion unit is used for converting the analog signal output and buffered by the input buffer unit into a digital signal and outputting the digital signal.

2. The buffer-type analog-to-digital converter according to claim 1, wherein the input buffer unit further comprises a level shift module for increasing an output level shift, wherein:

the level shifting module is connected between the first current source and the first main source follower, and a common joint point between the level shifting module and the first current source is used as the output of the input buffer unit; and/or

The level shift module is connected between the first main source follower and the first auxiliary source follower.

3. The buffer type analog-to-digital converter according to claim 1, wherein the first transistor and the second transistor are PMOS transistors, the source electrode of the first transistor is connected with a power supply through the first current source, and at least one of the second transistors is connected between the drain electrode of the first transistor and a common potential after being connected in series in the same direction; or

The first transistor and the second transistor are NMOS transistors, the source electrode of the first transistor is connected with a common potential through the first current source, and at least one second transistor is connected in series in the same direction and then connected between the drain electrode of the first transistor and a power supply.

4. The buffer type analog-to-digital converter according to any one of claims 1 to 3, wherein the first transistor and the second transistor are operated in a saturation region; the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor.

5. The buffer type analog-to-digital converter according to claim 4, wherein the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor in a relationship of: | Vth1| - | Vth0| ≧ Vod0| + margin;

wherein Vth1 is a threshold voltage of the first transistor, Vth0 is a threshold voltage of the second transistor, Vod0 is an overdrive voltage of the second transistor, and margin is a voltage margin.

6. The buffer-type analog-to-digital converter according to claim 1, wherein the analog-to-digital conversion unit includes a sample-and-hold circuit and a signal processing circuit connected to each other, an input terminal of the sample-and-hold circuit is used as an input of the analog-to-digital conversion unit, the sample-and-hold circuit is used for sampling an analog signal output from the input buffer unit according to a preset rule and storing the analog signal as a voltage signal, an output terminal of the signal processing circuit is used as an output of the analog-to-digital conversion unit, and the signal processing circuit is used for converting the voltage signal stored in the sample-and-hold circuit into a digital signal for output.

7. The buffer type analog-to-digital converter according to claim 6, wherein the sample-and-hold circuit includes a first switch, a second switch, a third switch, and an energy storage capacitor, wherein:

the first end of the first switch is used as the input end of the sample-hold circuit, the second end of the first switch, the first end of the second switch and the first end of the energy-storage capacitor are connected in common, the second end of the energy-storage capacitor and the first end of the third switch are connected in common and used as the output end of the sample-hold circuit to be connected with the signal processing circuit, and the second end of the second switch and the second end of the third switch are connected with the working voltage.

8. The buffer type analog-to-digital converter according to claim 1, wherein the number of the input buffer units is two, the inputs of the two input buffer units are used for accessing a pair of differential analog signals, and the outputs of the two input buffer units buffer the differential analog signals; the input of the analog-to-digital conversion unit comprises a first input and a second input, the first input and the second input of the analog-to-digital conversion unit are respectively connected with the outputs of the two input buffer units, and the analog-to-digital conversion unit is further used for respectively converting the differential analog signals output by the input buffer units into digital signals to be output.

9. The buffer analog-to-digital converter according to claim 8, further comprising a gain amplifying unit, wherein a first input end and a second input end of the gain amplifying unit are respectively connected to the outputs of the two input buffer units, a first output end and a second output end of the gain amplifying unit are respectively connected to the first input and the second input of the analog-to-digital converting unit, and the gain amplifying unit is configured to gain-amplify the signal output by the input buffer unit and output the signal.

10. The buffer type analog-to-digital converter according to claim 9, wherein the gain amplifying unit includes a first operational amplifier, a second operational amplifier, a first voltage dividing element, a second voltage dividing element, and a third voltage dividing element, a positive phase input terminal of the first operational amplifier is used as a first input terminal of the gain amplifying unit, one end of the first voltage dividing element is connected to an output terminal of the first operational amplifier, the other end of the first voltage dividing element is connected to an inverting input terminal of the first operational amplifier and one end of the second voltage dividing element, the other end of the second voltage dividing element is connected to an inverting input terminal of the second operational amplifier and one end of the third voltage dividing element, a positive phase input terminal of the second operational amplifier is used as a second input terminal of the gain amplifying unit, and the other end of the third voltage dividing element is connected to an output terminal of the second operational amplifier, the output end of the first operational amplifier is used as the first output end of the gain amplification unit, and the output end of the second operational amplifier is used as the second output end of the gain amplification unit.

11. The buffer type analog-to-digital converter according to claim 9, wherein the gain amplifying unit includes a first operational amplifier, a first voltage dividing element, a second voltage dividing element, a third voltage dividing element, and a fourth voltage dividing element, one end of the first voltage dividing element is used as a first input terminal of the gain amplifying unit, the other end of the first voltage dividing element is connected to a non-inverting input terminal of the first operational amplifier, one end of the second voltage dividing element is used as a second input terminal of the gain amplifying unit, the other end of the second voltage dividing element is connected to an inverting input terminal of the first operational amplifier, the third voltage dividing element is connected between the non-inverting input terminal and an inverting output terminal of the first operational amplifier, and the fourth voltage dividing element is connected between the inverting input terminal and the non-inverting output terminal of the first operational amplifier, and the inverting output end and the non-inverting output end of the first operational amplifier are respectively used as a first output end and a second output end of the gain amplification unit.

12. An integrated circuit comprising a buffered analog-to-digital converter as claimed in any of claims 1 to 11.