JP3500544B2 - Amplifier circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit using a semiconductor device by a CMOS process, and more particularly to an optical communication L circuit.
Wide band characteristics and wide dynamic range characteristics were made possible while securing the desired gain applied to SI etc.,
It relates to an amplifier.

In an optical communication LSI or the like, it is extremely important for an optical communication system to be able to design an amplifier circuit having high gain, wide band and wide dynamic range characteristics.

[0003]

2. Description of the Related Art FIG. 17 shows a configuration (1) of a typical conventional amplifier circuit. In the figure, Nch represents an N-channel transistor, R _D is a load resistance connected between its drain terminal and the power supply V _DD, and
_{With the} drain current I _D flowing from _DD , input voltage V _IN
To produce an output voltage V _OUT .

The drain voltage gain G _D of the amplifier circuit shown in FIG. 17 is expressed as follows: G _D = dV _OUT / dV _IN = d (V _DD −R _D · I _D ) / dV _IN = −R _D · d I _D / dV _IN = −R _D / r _s (1) Here, r _S is the internal resistance of the N-channel transistor. The amplifier circuit shown in FIG. 17 generally has a high gain but a narrow bandwidth.

FIG. 18 shows a configuration (2) of a typical conventional amplifier circuit, which corresponds to the N-channel transistor Nch11 corresponding to the N-channel transistor Nch in the circuit shown in FIG. , A diode-connected N-channel transistor Nch21 is connected in parallel, and is connected to a power supply V _DD via a constant current source I _D composed of a resistor or a P-channel transistor.

The amplifying circuit shown in FIG. 18 has a wide band by suppressing the gain by adding a diode-connected N-channel transistor Nch21. N-channel transistors Nch11, Nch21
When the internal resistance of the a r _S1, r _s2 respectively, input - the gain G between the output is as follows.

[Equation 1] here

[Equation 2]

Since k = (1/2) μ _n CoxW / L, g _m in the equation (2) is g _m = μ _n Cox (W / L)  (V _GS -V _TH ) Where μ _n is the electron mobility [cm ² / V · se
c] and Cox are the capacitance [F] of the gate oxide film, W is the effective gate width, and L is the effective gate length. Transistor Nch
If the gate widths of 11 and Nch ₂₁ are W _{11 and} W ₂₁ , respectively, and the gate lengths are L _{11 and} L _{21 ,} respectively, the equation (2) is

[Equation 3] Becomes

Therefore, the N-channel transistor Nch1
1, Nch21 gate length L₁₁= L _{twenty one}And gate saw
Voltage V_GS11= V_GS21Then, equation (3) becomes     G = W₁₁/ W_{twenty one}                                              … (4) And the gain G is the ratio of the gate width of each transistor.
Determined.

In order to widen the dynamic range of the circuit shown in FIG. 18, it can be considered to use it as a current-voltage conversion circuit by applying negative feedback.

FIG. 19 shows the configuration of the current-voltage conversion circuit, where -A is an amplifier and R _F is a negative feedback resistor. Further, PD represents a photo diode, and a current I _IN is caused to flow from the power source V _DD by the optical input. The output amplitude of the circuit of FIG. 19 is given by ΔV _OUT = I _IN × R _F (5)

FIG. 20 shows the DC input current-output voltage characteristics of the current-voltage conversion circuit shown in FIG. 19, where the horizontal axis is the input current I _IN [μA] and the vertical axis is the output voltage V.
_OUT [V]. In the DC input current-output voltage characteristic A, the linear range from the input current I _IN = 0 to the inflection point
(1) is the dynamic range of this circuit.

[0012] Figure 21 is a shows a static characteristic (V _D -I _D characteristic) of the amplifier circuit shown in FIG. 18, the horizontal axis represents the drain voltage V _OUT [V], the vertical axis represents the drain current I
_D [mA] and the N-channel transistor Nch1
1 shows changes in the drain voltage V _out with respect to changes in the input voltage V _IN of the 1, Nch 21 for A when the output current of the current source I _D is small and B when it is large.

In the DC input current-output voltage characteristic shown in FIG. 20, in order to secure a wider dynamic range, the operating point is set high in advance by increasing the current of the current source _ID. However, as shown in FIG. 21, the output voltage V _OUT
Since the fluctuation range of is narrow as in (1) → (2), it is difficult to widen the dynamic range.

[0014]

SUMMARY OF THE INVENTION The present invention is intended to solve the problems of the prior art as described above, and
It is possible to obtain a wide band characteristic and a wide dynamic range characteristic in an amplifier circuit using a semiconductor element by an OS process and to enhance a power supply noise rejection ratio (SVRR) in the amplifier circuit. It is intended to provide a circuit format.

[0015]

[Means for Solving the Problems]

(1) The drain terminal of each of the first N-channel transistor having the gate terminal as the input terminal and the diode-connected second N-channel transistor is connected to the output terminal, and the output terminal is connected via the constant current source. In the amplifier circuit connected to the power supply, the source terminals are sequentially connected to the next N
A plurality of diode-connected N-channel transistors connected to the drain terminals of the channel transistors are connected between the source terminals of the first N-channel transistor and the second N-channel transistor and the ground.

(2) In the case of (1), the third N-channel transistor is connected between the first N-channel transistor and the output terminal, and the diode-connected first N-channel transistor is connected between the second N-channel transistor and the output terminal. 4 N-channel transistors are connected, and the gates of the third N-channel transistor and the fourth N-channel transistor are common.

(3) In the case of (1), the third N-channel transistor is connected between the first N-channel transistor and the output terminal, and the diode-connected first N-channel transistor is connected between the second N-channel transistor and the output terminal. The fourth N-channel transistor is connected, and the bias circuit supplies a bias voltage to the gate of the third N-channel transistor.

(4) First P having a gate terminal as an input terminal
In the amplifier circuit in which the drain terminals of the channel transistor and the diode-connected second P-channel transistor are connected to the output terminal, and the output terminal is connected to the ground via the constant current source, the source terminals are sequentially connected. A transistor string including a plurality of diode-connected P-channel transistors connected to the drain terminal of the next P-channel transistor is connected between the source terminals of the first P-channel transistor and the second P-channel transistor and the power supply, respectively. Connecting.

(5) In the case of (4), a third P-channel transistor is connected between the first P-channel transistor and the output terminal, and a diode-connected first P-channel transistor is connected between the second P-channel transistor and the output terminal. The fourth P-channel transistor is connected, and the gates of the third P-channel transistor and the fourth P-channel transistor are common.

(6) In the case of (4), the third P-channel transistor is connected between the first P-channel transistor and the output terminal, and the diode-connected first P-channel transistor is connected between the second P-channel transistor and the output terminal. The fourth P-channel transistor is connected, and the bias circuit supplies a bias voltage to the gate of the third P-channel transistor.

(7) In the cases of (1) to (6), a source follower consisting of a P-channel transistor, which is supplied with power via a constant current source, is connected to the output of the amplifier circuit, and the output terminal of the source follower and the amplifier are amplified. Connect a negative feedback resistor between the input terminals of the circuit.

(8) In the cases of (1) to (6), the output of the amplifier circuit is connected to the source follower composed of an N-channel transistor grounded via a constant current source, and the output terminal of the source follower and the amplifier circuit are connected. Connect a negative feedback resistor between the input terminals.

[0023]

[Action]

(1) A first N-channel transistor Nch11 having a gate terminal as an input terminal and a second N-channel diode-connected N
In the amplifier circuit in which the drain terminal of each of the channel transistors Nch21 is connected to the output terminal and the output terminal is connected to the power supply via the constant current source, it is possible to achieve a wider band.

In this case, a plurality of diode-connected N-channel transistors Nc are formed by sequentially connecting the source terminal to the drain terminal of the next N-channel transistor.
A transistor array composed of h12 to Nch1n and Nch22 to Nch2n is referred to as a first N-channel transistor Nc.
It is connected between h11 and the source terminal of the second N-channel transistor Nch21 and the ground.

As a result, the operating point of the N-channel transistor forming the amplifier can be apparently increased, and therefore the dynamic range of the amplifier can be widened.

(2) In the case of (1), the third N-channel transistor is connected between the first N-channel transistor and the output terminal, and the diode-connected first N-channel transistor is connected between the second N-channel transistor and the output terminal. 4 N-channel transistors are connected, and the gates of the third N-channel transistor and the fourth N-channel transistor are made common.

In this case, since the third N-channel transistor acts as a resistor, even if the gate width of the first N-channel transistor is widened to have a high gain, the parasitic capacitance thereof increases the capacitance of the output terminal. Therefore, both high gain characteristics and wide band characteristics can be achieved.

(3) In the case of (1), a third N-channel transistor is connected between the first N-channel transistor and the output terminal, and a diode-connected first N-channel transistor is connected between the second N-channel transistor and the output terminal. No. 4 N-channel transistor is connected, and a bias voltage is supplied from the bias circuit to the gate of the third N-channel transistor.

In this case, as in the case of (2), the third N-channel transistor acts as a resistor, so that the first N-channel transistor can achieve both high gain characteristics and wide band characteristics. .

(4) First P using the gate terminal as an input terminal
In the amplifier circuit in which the drain terminals of the channel transistor Pc11 and the diode-connected second P-channel transistor Pch21 are connected to the output terminals, and the output terminals are connected to the ground via the constant current source, Can be achieved.

In this case, a plurality of diode-connected P-channel transistors Pc whose source terminal is sequentially connected to the drain terminal of the next P-channel transistor are connected.
A transistor array including h12 to Pch1n and Pch22 to Pch2n is referred to as a first P-channel transistor Pc.
11 and the source terminals of the second P-channel transistor Pch21 and the power supply, respectively.

As a result, the operating point of the P-channel transistor forming the amplifier can be apparently increased, and therefore the dynamic range of the amplifier can be widened.

(5) In the case of (4), the third P-channel transistor is connected between the first P-channel transistor and the output terminal, and the diode-connected first P-channel transistor is connected between the second P-channel transistor and the output terminal. The fourth P-channel transistor is connected, and the gates of the third P-channel transistor and the fourth P-channel transistor are common.

In this case, since the third P-channel transistor acts as a resistor, even if the gate width of the first P-channel transistor is widened to have a high gain, the parasitic capacitance of the third P-channel transistor increases the capacitance of the output terminal. Therefore, both high gain characteristics and wide band characteristics can be achieved.

(6) In the case of (4), the third P-channel transistor is connected between the first P-channel transistor and the output terminal, and the diode-connected first P-channel transistor is connected between the second P-channel transistor and the output terminal. The fourth P-channel transistor is connected, and the bias circuit supplies a bias voltage to the gate of the third P-channel transistor.

In this case, as in the case of (5), the third P-channel transistor acts as a resistor, so that the first P-channel transistor can achieve both high gain characteristics and wide band characteristics. .

(7) In the cases of (1) to (6), a source follower composed of a P-channel transistor Pch, which is supplied with power via a constant current source, is connected to the output of the amplifier circuit, and the output terminal of the source follower is connected. A negative feedback resistor R _F is connected between the input terminals of the amplifier circuit.

As a result, the potential of the output point of the amplifier circuit is raised, and a resistor R _F is connected between the output of the source follower and the input of the amplifier circuit to provide negative feedback, thereby reducing the power supply noise rejection ratio (SVRR). Can be enhanced.

(8) In the cases of (1) to (6), the output of the amplifier circuit is connected to the source follower composed of the N-channel transistor Nch grounded via the constant current source, and the output terminal of the source follower and the amplifier circuit. A negative feedback resistor R _F is connected between the input terminals of the.

As a result, the potential at the output point of the amplifier circuit is leveled down, and a resistor R _F is connected between the output of the source follower and the input of the amplifier circuit to provide negative feedback, thereby reducing the power supply noise rejection ratio (SVRR). Can be enhanced.

[0041]

EXAMPLE FIG. 1 shows an example (1) of the present invention, in which the same elements as in FIG.
Nch12, Nch22 are each an N-channel transistor, and having respective gate width W _12, W _22, the gate length L _12, L _22.

The circuit of FIG. 1 differs from that of the circuit shown in FIG. 18 in that N-channel transistor Nch11 is connected to ground, and
A diode-connected N channel transistor Nch1 is connected between the channel transistor Nch21 and the ground.
2, N-channel transistor Nch22 is connected. The input-output gain G ₁ in the circuit of FIG.
The internal resistance of each transistor is set to r _s11, r _s12, r
_{Assuming s21 and} r _s22 , the result is as follows.

[Equation 4]

Here, for simplification, each transistor is
The gate length of L₁₁= L₁₂= L_{twenty one}= L_{twenty two}= L, gate width
To W₁₁= W₁₂, W_{twenty one}= W_{twenty two}, Gate-source voltage
To V _GS11= V_GS12= V_GS21= V_GS22Then, the formula
(6) is

[Equation 5] Given in.

FIG. 2 shows a modification of the embodiment (1).
The diode-connected transistor in the embodiment of FIG.
, The N-channel transistor Nch12, ...,
Nch1n and N-channel transistor Nch22,
..., Nch2n cascode connection at each (n-1) stage
It is a continuation. Input-output gain G in this case _n
Becomes as follows from the equation (6).

[Equation 6]

Here, for simplification, the gate length of each transistor is L ₁₁ = L ₁₂ = ... = L _1n = L ₂₁ = L ₂₂ = ... =
L _2n , gate-source voltage, V _GS11 = V _GS12 = ... =
_{Assuming that} V _{GS 1n} = V _GS21 = V _GS22 = ... = V _GS2n , the equation (8) is: G _n = (W ₁₁ + W ₁₂ + ... + W _1n ) / (W ₂₁ + W ₂₂ + ... + W _2n ) ... (9) ).

FIG. 3 shows the DC input current-output voltage characteristics of the current-voltage conversion circuit using the amplifier circuit of the embodiment (1), where the horizontal axis represents the input current I _IN [μA] and the vertical axis. The axis is the output voltage V _OUT [V]. In FIG. 3, A is FIG.
Shows characteristics corresponding to the conventional example shown in FIG.
This is the characteristic corresponding to (1). Compared with the linear range (1) corresponding to the conventional example shown in FIG. 20, the linear range according to the present invention is
(2) is wider, so that the present invention can widen the dynamic range of the current-voltage conversion circuit.

FIG. 4 shows an embodiment (2) of the present invention.
In the modification of the embodiment (1) shown in FIG.
Each N-channel transistor to P-channel transistor
Power supply V_DDAnd ground (GND)
Replace with the constant current source I _DAs resistance or N
A channel transistor was used to reverse the current.
Have a configuration.

The embodiment (2) shown in FIG. 4 shows a case where the gain securing section is constituted by a P-channel transistor, and its operation is the case of the modification of the embodiment (1) shown in FIG. Is the same as.

FIG. 5 shows an embodiment (3) of the present invention. In the circuit of the embodiment shown in FIG. 2, the N-channel transistor Nch11 and the N-channel transistor Nch21 have a common gate structure. The difference is that the gate terminal of the N-channel transistor Nch12 is connected to the input terminal.

In order to obtain a high gain in the circuit shown in FIG. 2, the gate widths W ₁₁ and W ₂₁ , N ₂₁ , N _{21 of} the N-channel transistors Nch11 and Nch21 are obtained from the relation of the equation (9).
It is sufficient to increase the gate width ratio in each corresponding N-channel transistor such as the gate widths W _1n and W _{2n of} the channel transistors Nch1n and Nch2n.
The minimum value of the gate width is at most about 10 μm in order to suppress the fluctuation of the threshold value V _TH of the transistor, and it is difficult to make it smaller than that from the viewpoint of process accuracy.

Therefore, since the gate width of the N-channel transistor on the Nch 21 side is restricted, the N-channel on the Nch 11 side is
Although it is conceivable to increase the gate width of the channel transistor, doing so makes it difficult to realize a wide-band amplifier circuit because the capacitance of the output terminal increases due to the effect of parasitic capacitance added to the transistor. Become.

Therefore, in the embodiment (3), the N-channel transistor Nch11 and the N-channel transistor Nch are used.
The channel is commonly used for ch21 so that the N-channel transistor Nch11 functions as a resistor. This eliminates the influence of the parasitic capacitance of the N-channel transistor Nch12, so that the N-channel transistor Nc12
The gate width of h12 may be increased, so that it is possible to achieve both high gain characteristics and wide band characteristics.

FIG. 6 shows an embodiment (4) of the present invention. In the embodiment shown in FIG. 5, each N-channel transistor is replaced with a P-channel transistor and a power supply V _DD is _supplied . It has a configuration in which the ground (GND) is replaced and the current of the constant current source I _D is reversed.

The embodiment (4) shown in FIG. 6 shows a case where the gain securing section is constituted by a P-channel transistor, and its operation is the same as that of the embodiment (3) shown in FIG. is there.

FIG. 7 shows an embodiment (5) of the present invention, in which the gate of the N-channel transistor Nch11 is controlled by the bias circuit 11 in the embodiment shown in FIG. Is.

In the embodiment (5) shown in FIG. 7, N
By controlling the gate of the channel transistor Nch11 from the bias circuit 11, it can be operated as a resistance. Therefore, even if the gate width of the N-channel transistor Nch12 is increased, as in the embodiment shown in FIG. There is no influence of the parasitic capacitance, so that it is possible to achieve both high gain characteristics and wide band characteristics.

FIG. 8 shows an embodiment (6) of the present invention. In the embodiment shown in FIG. 7, each N-channel transistor is replaced with a P-channel transistor and a power supply V _DD is _supplied . It has a configuration in which the ground (GND) is replaced and the current of the constant current source I _D is reversed.

The embodiment (6) shown in FIG. 8 shows a case where the gain securing section is constituted by a P-channel transistor, and its operation is the same as that of the embodiment (5) shown in FIG. is there.

FIG. 9 shows an embodiment (7) of the present invention. The circuit of the embodiment (7) is the embodiment (1) to the embodiment (6).
1 by the amplifier circuit (-A) shown in FIG.
When the current-voltage conversion circuit shown in FIG. 9 is configured, a source follower composed of a P-channel transistor Pch is connected to the output, power is supplied from the power supply V _DD through the current source I _D, and the output of the source follower is supplied. A negative feedback resistor R _F is connected between the inputs of the amplifier circuit (-A).

In the embodiment (7) shown in FIG. 9, the output of the amplifier circuit (-A) is connected to the P-channel transistor Pc.
By connecting the source follower composed of h, the potential of the output point A of the amplifier circuit (-A) is increased and the output of the source follower and the amplifier circuit (-
By connecting the resistor R _F between the inputs of A) and performing negative feedback, the power supply noise rejection ratio (SVRR) can be enhanced.

FIG. 10 shows an embodiment (8) of the present invention. The circuit of the embodiment (8) is the same as the embodiment (1) to the embodiment.
At the output of the amplifier circuit (-A) shown in any of (6),
A source follower composed of an N-channel transistor Nch is connected to connect a constant current source _ID between the source and the ground (GND), and a negative feedback resistor R is provided between the output of the source follower and the input of the amplifier circuit (-A). _It is a connection of _F.

In the embodiment (8) shown in FIG. 10,
The N-channel transistor N is connected to the output of the amplifier circuit (-A).
By connecting a source follower composed of ch, the potential of the output point of the amplifier circuit (-A) is leveled down, and the output of the source follower and the amplifier circuit (-A) are reduced.
By connecting a resistor R _F between the inputs of and to perform negative feedback, the power supply noise rejection ratio (SVRR) can be enhanced.

11 to 16 show comparisons of various performances between the circuit of the present invention and the conventional circuit. Figure 11
Shows an example of DC input / output characteristics in a conventional circuit, "TYPICAL" shows characteristics in a typical case, and others show characteristics when manufacturing process changes.

FIG. 12 shows an example of the frequency characteristic of the transformer impedance in the conventional circuit.
It corresponds to the current-voltage conversion circuit shown in FIG.
“TYPICAL” shows the characteristics in a typical case, and the others show the characteristics when the manufacturing process changes.

FIG. 13 shows an example of DC input / output characteristics in the amplifier circuit of the present invention, and shows only a typical case. A shows the characteristic at the input terminal of the source follower shown in FIG. 10, and B shows the characteristic at the output terminal of the source follower.

FIG. 14 shows an example of the frequency characteristic of the transformer impedance in the amplifier circuit of the present invention, and shows only a typical case. A shows the characteristic at the input terminal of the source follower shown in FIG. 10, and B shows the characteristic at the output terminal of the source follower.

FIG. 15 shows an example of power supply noise rejection ratio characteristics in a conventional circuit, which is "TYPICAL".
Shows characteristics in a typical case, and others show characteristics when the manufacturing process changes.

FIG. 16 shows an example of power supply noise rejection ratio characteristics in the amplifier circuit of the present invention, and shows the case where the negative feedback resistance R _F = 4 KΩ. A shows the characteristic at the input terminal of the source follower shown in FIG. 10, and B shows the characteristic at the output terminal of the source follower.

[0069]

As described above, according to the present invention, C
In an amplifier circuit using a semiconductor element by the MOS process, by connecting an N-channel transistor (or P-channel transistor) amplifier to a diode-connected N-channel transistor (or P-channel transistor) in parallel, a wider bandwidth is possible. And the ground side (or power supply side) of such an amplifier circuit
In addition, by connecting a plurality of diode-connected N-channel transistors (or P-channel transistors) in multiple stages to raise (or lower) the operating point of the amplifier circuit, a wide dynamic range characteristic can be realized. Further, by connecting a source follower to the output of the amplifier circuit and performing negative feedback from the output to the input side, the power supply noise rejection ratio (SVRR) can be increased.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment (1) of the present invention.

FIG. 2 is a diagram showing a modification of the embodiment (1).

FIG. 3 is a diagram showing a DC input current-output voltage characteristic of a current-voltage conversion circuit using the amplifier circuit of the embodiment (1).

FIG. 4 is a diagram showing an embodiment (2) of the present invention.

FIG. 5 is a diagram showing an embodiment (3) of the present invention.

FIG. 6 is a diagram showing an embodiment (4) of the present invention.

FIG. 7 is a diagram showing an embodiment (5) of the present invention.

FIG. 8 is a diagram showing an embodiment (6) of the present invention.

FIG. 9 is a diagram showing an embodiment (7) of the present invention.

FIG. 10 is a diagram showing an embodiment (8) of the present invention.

FIG. 11 is a diagram showing an example of DC input / output characteristics in a conventional circuit.

FIG. 12 is a diagram showing an example of frequency characteristics of transformer impedance in a conventional circuit.

FIG. 13 is a diagram showing an example of DC input / output characteristics in the amplifier circuit of the present invention.

FIG. 14 is a diagram showing an example of frequency characteristics of a transformer impedance in the amplifier circuit of the present invention.

FIG. 15 is a diagram showing an example of power supply noise rejection ratio characteristics in a conventional circuit.

FIG. 16 is a diagram showing an example of power supply noise rejection ratio characteristics in the amplifier circuit of the present invention.

FIG. 17 is a diagram showing a configuration (1) of a typical conventional amplifier circuit.

FIG. 18 is a diagram showing a configuration (2) of a conventional typical amplifier circuit.

FIG. 19 is a diagram showing a configuration of a current-voltage conversion circuit.

20 is a diagram showing a DC input current-output voltage characteristic of the current-voltage conversion circuit shown in FIG.

FIG. 21 is a static characteristic of the amplifier circuit shown in FIG. 18 (V _D −
It is a figure which shows I _D characteristics).

[Explanation of symbols]

Nch, Nch11, Nch12, ..., Nch1n, N
ch21, Nch22, ..., Nch2n N-channel transistors Pch, Pch11, Pch12, ..., Pch1n, P
ch21, Pch22, ..., Pch2n P-channel transistor PD Photodiode 11 Bias circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Satoshi Yamamoto Satoshi Yamamoto 3-28-1, Joto, Oyama City, Tochigi Prefecture Fujitsu Digital Technology Limited (56) References JP-A-4-292006 (JP, A) Special Features Kaihei 2-60312 (JP, A) JP-A-6-13817 (JP, A) JP-A-6-90121 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03F 1 / 00-3/72

Claims (4)

(57) [Claims] 1. A drain terminal of a first N-channel transistor having a gate terminal as an input terminal and a diode-connected second N-channel transistor is connected to an output terminal, and the output terminal is connected to a constant current source. In the amplifier circuit connected to the power supply via the power source, a transistor array including a plurality of diode-connected N-channel transistors whose source terminal is sequentially connected to the drain terminal of the next N-channel transistor
Connected between the N-channel transistor and the source terminal of the second N-channel transistor and the ground, the first
Between the N-channel transistor of the
Of the second N-channel transistor
A diode is connected between the channel transistor and the output terminal.
Connecting the connected fourth N-channel transistor,
Third N-channel transistor and the fourth N-channel
An amplifier circuit having a structure in which a gate of a transistor and a gate of the transistor are commonly connected . 2. A first P-channel device having a gate terminal as an input terminal.
The second P-channel diode-connected to the channel transistor
Output terminal of each drain transistor
The output terminal via a constant current source.
In the amplifier circuit connected to the source , the source terminal is sequentially connected to the drain of the next P-channel transistor.
P-channel diode connected to multiple terminals
A transistor array composed of a channel transistor,
P-channel transistor and the second P-channel transistor
Connected between the source terminal of the transistor and the power supply,
Between the P-channel transistor and the output terminal of
Of the second P-channel transistor
A diode is connected between the channel transistor and the output terminal.
Connecting the connected fourth P-channel transistor,
Third P-channel transistor and the fourth P-channel
An amplifier circuit having a configuration in which a gate of a transistor and a gate of the transistor are commonly connected . 3. The amplifier circuit according to claim 1 or 2.
The power supply to the output terminal of the amplifier circuit via a constant current source.
Source comprising a P-channel transistor connected to
Connect the follower to the output terminal of the source follower
An amplifier circuit characterized in that a negative feedback resistor is connected between the input terminal of the width circuit and the input terminal . 4. The amplifier circuit according to claim 1 or 2.
The output terminal of the amplifier circuit is grounded via a constant current source.
Source follower consisting of an integrated N-channel transistor
And an output terminal of the source follower and the amplifier circuit.
An amplifier circuit characterized by connecting a negative feedback resistor to the input terminal of the .