CN101567387A - 双扩散金属氧化物半导体晶体管 - Google Patents

双扩散金属氧化物半导体晶体管 Download PDF

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CN101567387A
CN101567387A CNA2009101321475A CN200910132147A CN101567387A CN 101567387 A CN101567387 A CN 101567387A CN A2009101321475 A CNA2009101321475 A CN A2009101321475A CN 200910132147 A CN200910132147 A CN 200910132147A CN 101567387 A CN101567387 A CN 101567387A
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大竹诚治
菊地修一
武田安弘
牧贤一
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Sanyo Electric Co Ltd
System Solutions Co Ltd
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Abstract

一种DMOS晶体管。减少DMOS晶体管的导通电阻，而且防止静电破坏强度的恶化。把DMOS晶体管的源极层(5)端部配置成从栅极电极(7)内侧的角部(7A)后退。不把源极层(5)上的硅化物层(11)从源极层(5)的端部向外延伸。即虽然在源极层(5)的表面形成硅化物层(11)，但在源极层(5)与栅极电极(7)内侧的角部(7A)之间露出的体层(4)表面并没形成硅化物层(11)。由此，没有电流集中，由于电流在DMOS晶体管整体大致均匀流动，所以能够提高静电破坏强度。

Description

双扩散金属氧化物半导体晶体管
技术领域
本发明涉及DMOS晶体管。
背景技术
DMOS晶体管(Double-diffused MOS transistor：双扩散金属氧化物半导体晶体管)是通过杂质双重扩散而形成有源极层和成为沟道的体层的MOS场效应晶体管，作为电源电路和驱动电路等电源用半导体元件被使用。
近年来，要求手机等电子机器小型化、低消耗电力化，所以就要求降低DMOS晶体管的导通电阻(DMOS晶体管被导通时的电阻)。
专利文献1～6公开了有关降低DMOS晶体管的导通电阻和提高耐压等的技术。
专利文献1：(日本)特开平10-233508号公报
专利文献2：(日本)特开2004-39773号公报
专利文献3：(日本)特开2004-79800号公报
专利文献4：(日本)特开2007-128978号公报
专利文献5：(日本)特表2007-535813号公报
专利文献6：(日本)特开2008-34737号公报
为了降低DMOS晶体管的导通电阻，在源极层等的表面形成钴或钛等过渡性金属与硅的反应生成物即硅化物层是有效的。但由于硅化物层是低电阻，所以在晶体管内容易引起电场、电流的集中，有DMOS晶体管的静电破坏强度恶化的问题。
发明内容
本发明的DMOS晶体管具备：半导体层、形成于所述半导体层表面的第一导电型体层、形成于所述体层表面的第二导电型源极层、形成于所述源极层表面的硅化物层、把所述体层和所述源极层包围而形成为环状的栅极电极，其中，把所述源极层的端部配置成从所述栅极电极内侧的角部后退，在所述源极层与所述栅极电极内侧的角部之间露出的所述体层表面不形成所述硅化物层。
根据上述结构，由于设置在源极层的表面形成的硅化物层，所以能够降低DMOS晶体管的导通电阻。
由于采用把源极层的端部配置成从栅极电极内侧的角部后退，且在源极层与栅极电极内侧的角部之间露出的体层表面不形成硅化物层的结构，所以从DMOS晶体管的外部有伴随浪涌电流等的电荷进入时，源极端部的电场被缓和，由于在该部分也难于引起电流集中，所以能够防止静电破坏强度的恶化。
根据本发明的DMOS晶体管，能够降低DMOS晶体管的导通电阻，而且能够防止其静电破坏强度的恶化。
附图说明
图1是本发明实施例DMOS晶体管的俯视图；
图2是图1的X-X线剖视图；
图3是图1的Y-Y线剖视图。
符号说明
1硅基板    2硅层   3埋入层      4体层    5源极层
6主体电位设定层    7栅极电极    8栅极绝缘膜
9电场缓和绝缘膜    10漏极层     11硅化物层
12硅化物阻止膜     13电场缓和层 14耗尽层
15层间绝缘膜       16、20接触孔 17、21金属端子
18、22势垒层       19源极配线层 23漏极配线层
具体实施方式
本发明实施例的DMOS晶体管作为电源电路或驱动电路等的电源用半导体元件而能够内藏在IC中，特别是使用硅化物技术而实现非常低的导通电阻(例如100mΩ)，且通过形成硅化物层以使电场、电流不集中，而能够防止静电破坏强度的恶化。
以下参照附图说明该DMOS晶体管的结构。图1是本发明实施例DMOS晶体管的俯视图，图2是图1的X-X线剖视图，图3是图1的Y-Y线剖视图。
如图所示，在P型硅基板1上利用外延生长而形成N-型的硅层2。优选在硅基板1与硅层2的边界形成比硅层2浓度高的N+型埋入层3。这是为了减少DMOS晶体管的漏极电阻而设置，通过在所述外延生长时使向硅基板1导入的锑(Sb)等N型杂质在硅层2中向上方扩散而形成。
在硅层2的表面利用P型杂质的扩散而形成P+型的体层4。在体层4的表面形成N++型的源极层5。且优选在体层4的表面形成用于把体层4的电位设定成源极电位的P++型主体电位设定层6。该主体电位设定层6被源极层5包围。
且形成包围体层4和源极层5的环状栅极电极7。栅极电极7在环的内侧具有四个角部7A(图1中被虚线包围的部分)。且N+型是比N-型浓度高的扩散层，N++型表示是比N+型浓度高的N型扩散层。同样地，P++型表示是比P+型浓度高的P型扩散层。
栅极电极7被形成在硅层2表面形成的栅极绝缘膜8上。栅极电极7的左右两端部在包围从栅极绝缘膜8向把DMOS晶体管的周围而形成的电场缓和绝缘膜9上延伸。电场缓和绝缘膜9例如是利用LOCOS(LocalOxidation Of Silicom：硅的局部氧化)法形成的比栅极绝缘膜8厚的绝缘膜，具有缓和DMOS晶体管的栅极电场的作用(参照图1、图2)。
所述体层4是把栅极电极7作为掩模并利用离子注入法在栅极电极7内侧的边缘自己整合所形成。且体层4的端部横向延伸到栅极电极7端部下方的硅层2。在栅极电极7的下方与栅极电极7重叠的体层4部分则成为沟道区域CH(参照图3)。且与栅极电极7的外侧邻接而在硅层2的表面形成N++型的漏极层10。
在上述结构的DMOS晶体管中，当向栅极电极7施加界限值以上的电压，则沟道区域CH从P型向N型翻转，DMOS晶体管被导通。且在该状态下当向源极层5与漏极层10之间施加电压，则从源极层5通过硅层2而到达漏极层10地形成源极漏极之间的电流路径。
本实施例为了减少DMOS晶体管的导通电阻而在源极层5、主体电位设定层6、漏极层10的表面形成Ti(钛)硅化物、Co(钴)硅化物等的硅化物层11。
在上述结构的栅极电极7内侧的角部7A处当从DMOS晶体管外部有伴随浪涌电流等的电荷进入时，容易产生电场集中。于是把源极层5的端部配置成从栅极电极7内侧的角部7A后退。
在把源极层5上的硅化物层11从源极层5的端部沿体层4的表面向角部7A的方向延伸的情况下，则电流集中在该延伸的硅化物层11部分，DMOS晶体管容易产生破坏。这是由于硅化物层11是低电阻而在栅极电极7内侧的角部7A电场比较强的缘故。
于是本实施例不把源极层5上的硅化物层11从源极层5的端部向外延伸。即虽然在源极层5的表面形成硅化物层11，但在源极层5与栅极电极7内侧的角部7A之间露出的体层4表面并没形成硅化物层11。由此，没有电流集中，由于电流在DMOS晶体管整体大致均匀流动，所以能够提高DMOS晶体管的静电破坏强度。
作为用于使硅化物层11不向源极层5外延伸的方法之一，是在源极层5与栅极电极7内侧的角部7A之间露出的体层4表面形成由硅氧化膜构成的硅化物阻止膜12(参照图1、图2)。本实施例中由于在栅极电极7的侧壁形成有侧壁间隔部13，所以硅化物阻止膜12被形成为从露出的体层4的表面把侧壁间隔部13覆盖。
在硅化物工序中，向源极层5和硅化物阻止膜12上溅射Ti等过渡性金属，然后通过热处理使产生硅化物反应。这时，由于在硅化物阻止膜12上过渡性金属与硅不接触，所以不产生硅化物反应。把硅化物阻止膜12上未反应的留下来的过渡性金属膜利用蚀刻液有选择地除去。由此，能够仅在源极层5和主体电位设定层6上有选择地形成硅化物层11。对于栅极电极7，通过把其表面从硅化物阻止膜12露出而能够在栅极电极7的表面也同时形成硅化物层11。
作为用于把源极层5端部的电场进一步缓和的机构，优选形成P+型的电场缓和层13。该电场缓和层13与从栅极电极7内侧的角部7A后退的所述源极层5的端部邻接，通过向硅层2中导入硼等P+型杂质而形成。更优选把电场缓和层13形成在栅极电极7延伸的电场缓和绝缘膜9的下方(参照图1、图2)。
根据设置有上述电场缓和层13的结构，使体层4的耗尽层与电场缓和层13的耗尽层成为一体，利用该一体化的耗尽层14则把源极层5端部的电场缓和，能够更加提高静电破坏强度。
最后说明DMOS晶体管的电极取出结构。把DMOS晶体管的整个面用BPSG等层间绝缘膜15覆盖，分别在源极层5、主体电位设定层6上的层间绝缘膜15上形成接触孔16，向这些接触孔16埋入钨等金属端子17。于是，在层间绝缘膜15的表面经由势垒层18而形成由Al-Si-Cu合金等构成的源极配线层19。由此，源极层5和主体电位设定层6被与源极配线层19电连接。其结果是体层4的电位与源极层5的电位一起被设定成从源极配线层19供给的源极电位(参照图2)。
同样地在漏极层10上的层间绝缘膜15形成接触孔20，向该接触孔20埋入钨等的金属端子21。于是，在层间绝缘膜15的表面经由势垒层22而形成由Al-Si-Cu合金等构成的漏极配线层23。由此，漏极层10被与漏极配线层23电连接(参照图3)。
本发明并不限定于上述实施例，当然在不脱离其要旨的范围能够进行变更。例如在上述实施例中以N沟道型的DMOS晶体管为例进行了说明，但本发明也能够适用P沟道型的DMOS晶体管。

Claims (5)

1、一种DMOS晶体管，其特征在于，具备：
半导体层、
形成于所述半导体层表面的第一导电型体层、
形成于所述体层表面的第二导电型源极层、
形成于所述源极层表面的硅化物层、
把所述体层和所述源极层包围而形成为环状的栅极电极，
在所述源极层与所述栅极电极之间露出的所述体层表面不形成所述硅化物层。
2、一种DMOS晶体管，其特征在于，具备：
半导体层、
形成于所述半导体层表面的第一导电型体层、
形成于所述体层表面的第二导电型源极层、
形成于所述源极层表面的硅化物层、
把所述体层和所述源极层包围而形成为环状的栅极电极，
把所述源极层的端部配置成从所述栅极电极内侧的角部后退，在所述源极层与所述栅极电极内侧的角部之间露出的所述体层表面不形成所述硅化物层。
3、如权利要求1或2所述的DMOS晶体管，其特征在于，所述源极层与所述栅极电极内侧的角部之间露出的所述体层表面被阻止所述硅化物层形成的硅化物阻止膜所覆盖。
4、如权利要求1、2、3中任一项所述的DMOS晶体管，其特征在于，与从所述栅极电极内侧的角部后退的所述源极层的端部邻接地、在所述半导体层中设置第二导电型电场缓和半导体层。
5、如权利要求4所述的DMOS晶体管，其特征在于，所述栅极电极从栅极绝缘膜上向电场缓和绝缘膜上延伸，所述电场缓和半导体层被配置在所述电场缓和绝缘膜的下方。
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