CN101567357A - 具有配线基板的电子设备及用于这种电子设备的配线基板 - Google Patents

具有配线基板的电子设备及用于这种电子设备的配线基板 Download PDF

Info

Publication number
CN101567357A
CN101567357A CNA2009101379993A CN200910137999A CN101567357A CN 101567357 A CN101567357 A CN 101567357A CN A2009101379993 A CNA2009101379993 A CN A2009101379993A CN 200910137999 A CN200910137999 A CN 200910137999A CN 101567357 A CN101567357 A CN 101567357A
Authority
CN
China
Prior art keywords
resin bed
distribution
resin
semiconductor chip
wiring substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2009101379993A
Other languages
English (en)
Other versions
CN101567357B (zh
Inventor
渡边真司
山口幸雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lenovo Innovations Co ltd Hong Kong
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CN101567357A publication Critical patent/CN101567357A/zh
Application granted granted Critical
Publication of CN101567357B publication Critical patent/CN101567357B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/742Apparatus for manufacturing bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/90Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183Components mounted in and supported by recessed areas of the printed circuit board
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54426Marks applied to semiconductor devices or parts for alignment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/75251Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/75252Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312Aligning
    • H01L2224/83121Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83194Lateral distribution of the layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06582Housing for the assembly, e.g. chip scale package [CSP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/0665Epoxy resin
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0313Organic insulating material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0104Properties and characteristics in general
    • H05K2201/0129Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0104Properties and characteristics in general
    • H05K2201/0133Elastomeric or compliant polymer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/10515Stacked components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
    • H05K2201/10977Encapsulated connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189Pressing leads, bumps or a die through an insulating layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305Affixing by adhesive
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4688Composite multilayer circuits, i.e. comprising insulating layers having different properties

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Metallurgy (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明涉及具有配线基板的电子设备及用于这种电子设备的配线基板。一种电子设备(1),其提供有配线基板(2)和半导体芯片(5)。配线基板(2)提供有通过在其间具有配线(4)而相互叠置的第一树脂层(3a)和第二树脂层(3b)。半导体芯片(5)在其一侧上具有突起(6)并通过进入到第一树脂层(3a)中以使得突起(6)与配线(4)接触与配线(4)连接。第一树脂层(3a)包括热塑性树脂,和第二树脂层(3b)在第一树脂层(3a)的熔点下具有1GPa或更高的弹性。

Description

具有配线基板的电子设备及用于这种电子设备的配线基板
本申请是申请日为2006年3月14日、发明名称为“具有配线基板的电子设备、其制造方法以及用于这种电子设备的配线基板”且申请号为200680011442.X的中国发明专利申请的分案申请。
技术领域
本发明涉及一种电子设备、制造电子设备的方法以及用在电子设备中的配线基板,且特别涉及一种包括配线基板和通过倒装芯片安装装配于该配线基板上的半导体芯片的电子设备等。
背景技术
半导体芯片和配线基板的通过倒装芯片的连接结构所实现的一个重要任务是增加半导体芯片和配线基板之间连接部分的可靠性。至今,已知有一种使用树脂将半导体芯片和配线基板彼此固定起来以增加其连接部分可靠性的方法。
在JP-A-4-82241(专利文献1)中公开了用树脂相互固定半导体芯片和配线基板的方法的一个实例。根据专利文献1中公开的方法,在其上设置有配线的配线基板上涂覆可紫外线硬化的或热固性的粘性树脂,且将设置有突出电极的半导体芯片压向配线基板以使配线与突出电极接触。当保持配线与突出电极相接触这种状态时,使粘性树脂硬化,以将半导体芯片固定到配线基板上。
上述方法通常称作压接工艺。根据该压接工艺,通过气动式分配器提供树脂。半导体芯片的上表面贴附到安装设备并由安装设备保持,而且,该半导体芯片位置与配线基板对准。之后,将半导体芯片压向配线基板。在压接工艺中,在树脂处于液状的状态下,配线和突起电极相互接触,并在保持配线和突起电极相互接触的状态下硬化树脂。因此,在配线基板和半导体芯片之间的连接部分处产生的任何残余应力都很小,且该连接高度可靠。
近些年,日益需求在移动终端装置中的半导体设备更加薄型化。为了满足这种需求,半导体芯片的外形越来越小。然而,随着半导体芯片外形越来越小,出现了以下问题:当将贴附到安装设备并由安装设备保持的半导体芯片被压向配线基板时,液状树脂被半导体芯片挤压到半导体芯片边缘附近。由于表面张力,挤压出的树脂沿着半导体芯片的侧表面上涨。当上涨的树脂达到半导体芯片的上表面时,其接触到安装设备。由于在其与安装设备接触的状态下硬化了树脂,因此硬化的树脂被固着到安装设备上,结果不能进行随后的安装工艺。
为了防止树脂接触安装设备,相对于半导体芯片面积而言,与半导体芯片接触的安装设备表面的面积被充分降低,以使得安装设备仅仅被保持在半导体芯片的中心区域。然而,在该情形中,如果半导体芯片的厚度很薄,则当按压半导体芯片时,半导体芯片的中心区域承受局部应力,该局部应力易于损坏半导体芯片。
由于半导体芯片的厚度很薄,树脂容易达到半导体芯片的上表面,因此需要将所施加的树脂量的变化最小化。一般来讲,已知如果半导体芯片的厚度被降低到0.15mm或更小,则难于控制液状树脂的树脂量。
已经提出了膜状树脂材料,以避免由使用液体树脂导致的各种上述问题。然而,用作underfilled树脂的膜状树脂材料存在膜结构所特有的问题,例如膜与配线基板的粘附性,在配线基板和膜之间产生气泡,以及硬化树脂之后的连接可靠性。而且,如果使用膜状树脂材料,则不能使用现有的分配器,而必须安装新的制膜器。因此,使用膜状树脂材料就制造成本而言也存在大问题。
在JP-A No.2001-156110(专利文献2)中公开了用树脂相互固定半导体芯片和配线基板的另一种方法。根据专利文献2的方法,首先,在其上设置有配线的膜板上,以覆盖配线的方式形成热塑性树脂涂层。之后,将热塑性树脂涂层加热熔化,在该状态下将半导体芯片压向热塑性树脂涂层,同时向其施加超声波,从而使配线与半导体芯片上的突起电极接触。之后,在配线和突起电极相互接触的状态下,连续向其施加超声波,用超声波将配线和突起电极相互接合起来。通过冷却和硬化热塑性树脂涂层,将半导体芯片固定到配线基板上。专利文献2记载了根据该方法,能够将半导体芯片电性且机械地可靠连接到配线基板。
然而,已知根据专利文献2中公开的超声波接合方法,对于具有一边的长度超出10mm的尺寸的半导体芯片而言,难以稳定地连接其所有电极。可适用该超声波接合方法的芯片尺寸是受限的。而且,考虑到连接可靠性和电特性等方面,电子设备通常采用Cu配线。为了制作更可靠的连接,需要为配线使用电解镍电镀或电解金电镀。
因此,必须将用于电镀的导线连接到所有配线。随着连接到配线基板的半导体芯片的电极数目增加,用于电镀的导线数目也增加。很多半导体芯片都具有几百个电极,对于这样的半导体芯片,由于受限的配线空间,很难布置电镀的导线。由于这些导线起到噪声天线的作用,因此其在电特性方面存在缺陷。因此,超声波接合方法仅用于尺寸微小的且仅具有几个电极的半导体芯片,例如用于数据载体应用的那些。在使用了尺寸大且具有很多电极的半导体芯片的电子设备中采用超声波接合方法,还有很多问题要解决。
除了超声波接合方法之外,还考虑了在将热塑性树脂涂层加热溶化的状态下将半导体芯片压向配线基板以由此将半导体芯片连接到配线的方法。然而,根据该方法,由于当热塑性树脂涂层被加热时,在配线下方的树脂层也被过度软化,因此当按压半导体芯片时,配线陷入到下部树脂层中,这导致半导体芯片和配线基板不能充分地相互连接。
发明内容
本发明的目的是提供一种电子设备,其允许配线基板和芯片部件以高可靠性相互连接,即使安装在配线基板上的芯片部件尺寸大并具有很多电极也是如此,且其能适当地降低尺寸和厚度,并提供这种电子设备的制造方法。
为了实现上述目的,根据本发明的电子设备包括配线基板和安装在配线基板上的至少一个芯片。配线基板包括第一树脂层和第二树脂层,其相互叠置,其间插有配线。芯片部件包括设置在其一个表面上并被移动到第一树脂层中且连接到配线的突起电极,保持突起电极与配线接触。第一树脂层含有至少一种热塑性树脂,和第二树脂层在第一树脂层的熔点下具有1Gpa或更高的弹性率。
根据本发明具有安装于配线基板上的芯片部件的电子设备的制造方法包括步骤:制备具有设置于其一个表面上的突起电极的芯片部件和包括第一树脂层和第二树脂层的配线基板,第一树脂层和第二树脂层之间插有配线,第一树脂层含有至少一种热塑性树脂,和第二树脂层在第一树脂层的熔点下具有1Gpa或更高的弹性率;加热其中安装了芯片部件的第一树脂层的区域至等于或更与第一树脂层熔点的温度;将芯片部件按压到第一树脂层加热区域中的第一树脂层中,同时具有突起电极的表面面对第一树脂层;通过钻孔第一树脂层使得芯片部件的突起电极与配线接触;并保持突起电极和配线相互接触直到硬化第一树脂层。第一树脂层含有至少一种热塑性树脂,和第二树脂层在第一树脂层的熔点下具有1Gpa或更高的弹性率。
根据本发明的配线基板,用于在其上安装具有设置于其一个表面上的突起的至少一个芯片部件,其包括:第一树脂层和叠置在第一树脂层上的第二树脂层,其间插有配线,被移动到第一树脂层中的芯片部件突起电极保持与配线接触。第一树脂层含有至少一种热塑性树脂,和第二树脂层在第一树脂层的熔点下具有1Gpa或更高的弹性率。芯片部件移动到第一树脂层中,突起电极连接到配线。
根据本发明,将其中安装了芯片部件的第一树脂层的区域加热到等于或高于其熔点的温度,并之后将芯片部件移动到第一树脂层中,以使突起电极与配线接触。此时,由于第二树脂层的弹性率是1Gpa或更高,因此防止配线陷入到第二层中,同时芯片部件被移动到第一树脂层中。第二树脂层由此用作芯片部件连接辅助层,以允许容易地将芯片部件移动到第一树脂层中,同时防止配线陷入。
使用被移动到第一树脂层中的芯片部件,硬化第一树脂层同时保持突起电极和配线相互接触,从而保持芯片电极在配线基板中。在这时间期间,由于温度从等于或高于第一树脂层熔点的温度变为硬化第一树脂层的温度,因此保持与第一树脂层接触的芯片部件和第二树脂层尺寸变化。由于芯片部件和第二树脂层具有不同的热膨胀系数,因此其尺寸变化。然而,由于被熔化并软化的第一树脂层存在于芯片部件和第二树脂层之间,因此由芯片部件和第二树脂层的尺寸变化产生的应力由第一树脂层释放。第一树脂层由此用作芯片部件保持层,用于当被移动时保持芯片部件,和用作应力释放层,用于释放在芯片部件和第二树脂层之间产生的应力。芯片部件突起电极和配线由此保持相互接触,结果是芯片部件和配线基板之间的连接可靠性增加。
当将芯片部件移动到第一树脂层中时,第一树脂层出现在芯片部件周围。第一树脂层升高的高度取决于芯片部件移动的距离,或换句话说,取决于第一树脂层的厚度。总之,树脂层由膜形式的材料制成。由于膜厚度能通过膜制造装置实时控制,因此用作树脂层的膜材料厚度高度精确。因此,能以高精确度控制第一树脂层的厚度。即使芯片部件的厚度小,第一树脂层的厚度也能通过根据芯片部件的该厚度和尺寸以及由芯片部件向第一树脂层中的移动挤出去的树脂量选择最佳膜厚度来控制,以使第一树脂层不会到达移动到第一树脂层中的芯片部件表面。因此,通过控制第一树脂层厚度的非常简单的工艺,容易防止第一树脂层的树脂粘附到安装设备上。结果,安装设备的尺寸不需要小于芯片部件以防止树脂粘附到安装设备。由于能使用尺寸大于芯片部件的安装设备,因此安装设备不将局部应力施加到薄的芯片部件,且当将芯片部件移动到第一树脂层中时不容易损坏芯片部件。
根据本发明,如上所述,通过适当地设置配线基板的第一和第二树脂层的弹性率增加了芯片部件和配线基板之间连接的可靠性。由于芯片部件直接连接到了配线基板中的配线,因此能比现有技术电子设备的那些更简单地制作配线。由此降低了电子设备和结合了该电子设备的各种装置的尺寸和厚度。
附图说明
图1是根据本发明实施例的电子设备的截面图;
图2是图1中所示电子设备中使用的配线基板的截面图;
图3是图1中所示电子设备中使用的半导体芯片的截面图;
图4是示出在半导体芯片上形成突起的方法的图;
图5是示出在半导体芯片上形成突起的另一种方法的图;
图6是示出结晶树脂和非结晶树脂的温度和弹性率之间关系的图;
图7是将本发明应用至其的另一种电子设备的截面图;
图8是将本发明应用至其的再一种电子设备的截面图;
图9是将本发明应用至其的再一种电子设备的截面图;
图10是将本发明应用至其的再一种电子设备的截面图;
图11是将本发明应用至其的再一种电子设备的截面图;
图12是将本发明应用至其的再一种电子设备的截面图;
图13是将本发明应用至其的再一种电子设备的截面图;
图14是将本发明应用至其的再一种电子设备的截面图;
图15是将本发明应用至其的再一种电子设备的截面图;
图16是将本发明应用至其的再一种电子设备的截面图;
图17是将本发明应用至其的再一种电子设备的截面图;
图18是将本发明应用至其的再一种电子设备的截面图;
图19A是将本发明应用至其的再一种电子设备中使用的配线基板的平面图;
图19B是具有在图19A中所示配线基板上相互平行地安装的两个半导体芯片的电子设备的截面图;
图20是将本发明应用至其的再一种电子设备的截面图;
图21A是根据本发明再-配线基板的平面图;
图21B是具有于图21A中示出的配线基板上安装的两个叠置的半导体芯片的半导体封装的截面图;
图22是将本发明应用至其的功能模块的示意性截面图;
图23是将现有技术设置应用至其的功能模块的示意性截面图;和
图24是示出当第二树脂层不满足基于本发明的条件时所出现问题的截面图。
参考符号的描述
1电子设备
2配线基板
3a第一树脂层
3b第二树脂层
4、4a、4b配线
4g、7接地图案
5半导体芯片
6突起
8通孔
9焊料抗蚀剂
用于实施发明的最佳方式
图1示出了根据本发明实施例的包括配线基板2和半导体芯片5的电子设备1。
如图2中所示,配线基板2包括第一树脂层3a和第二树脂板3b。在第二树脂板3b上,形成了一定图案的配线4。第一树脂层3a在第二树脂板3b的形成有配线4的表面上叠层。配线4能通过相减工艺形成,该工艺通常用于在基板上形成配线。然而,配线4也可由其他工艺形成,如相加工艺或半相加工艺等。配线4通常由铜制成。然而,在与半导体芯片的外部端子(未示出)电气连接的区域中,配线4由Au等不易氧化的材料制成,以实现更高可靠性。
图3示出了在图1中所示电子设备1中使用的半导体芯片5。半导体芯片5的一面成为电路面。在电路面上,形成与半导体芯片5的内部电路连接的电极垫(图3中未示出)。在该电极垫上,形成作为外部端子的具有尖端的突起6。突起6可通过引线接合法或钻孔法形成。
以下将参考图4描述根据引线接合法形成突起6的方法。首先,在由毛细管16夹持的金引线17的末梢上形成金球18。通过毛细管16,将金球18压向半导体芯片5的电路面上形成的电极垫5a。在将金球18连接到电极垫5a之后,分开金引线17以形成具有尖端的突起6。金球18通过使金引线17从毛细管16的末梢突出、将高压施加到火焰和金引线17之间以在其间产生火花,从而熔化从毛细管16末梢突出的那部分金引线17,并使得能够在所熔化部分硬化时,金引线17的熔化部分在表面张力下变形为球状。
另一方面,图5中示出了通过钻孔法形成突起6,如下:通过具有圆锥形凹陷19a的打孔机19和管芯20,对带形材料21进行钻孔,并将该钻孔部分与在半导体芯片5的电路面上形成的焊垫5a相接合,从此形成具有尖端的突起6。
如图1中所示,通过将半导体芯片5压到(移动到)第一树脂层3a中时,突起6贯穿第一树脂层3a以与配线4接触。如稍后将详细描述的,当半导体芯片5被压到第一树脂层3a中时,由于第一树脂层3a的弹性率充分小,因此突起6的端部不必削尖。然而,优选的是突起6具有尖端,这是由于其容易穿孔第一树脂层3a,且其能实现连接可靠性。突起6可包括各种突起如高温焊料突起、铜突起、金突起等,突起6的材料并未受到特别限制。
返回参考图1,在半导体芯片5中,安装有突起6的侧面被移动到第一树脂层3a中,突起6贯穿第一树脂层3a并连接到配线4。而且,将半导体芯片5保持在第一树脂层3a中。为了制造该结构,如下构造配线基板2的树脂层3a、3b。首先,第一树脂层3a包括至少一种热塑性树脂。在第一树脂层3a的熔点下,第二树脂层3b具有1GPa或更高的弹性率。在将半导体芯片5安装到配线基板2之后,第一树脂层3a的厚度比安装到配线基板2之后的半导体芯片5的高度(在安装后挤压突起6的端部,使得半导体芯片5的高度小于将其安装到配线基板2上之前的高度)薄。半导体芯片5的表面从第一树脂层3a的表面突出。
以下将描述根据本发明在配线基板2上安装半导体芯片5的方法。
在将半导体芯片5安装到配线基板2上之前,希望通过等离子体处理或者紫外辐射来活化第一树脂层3a的表面,以增加配线基板2的第一树脂层3a与半导体芯片5的粘附。
为了将半导体芯片5安装到配线基板2上,将配线基板2和半导体芯片5位置对准。所述位置对准可通过使用如下技术来进行:吸附到安装装置的安装设备并由该安装设备保持的半导体芯片5与在配线基板2上设置的位置对准标记是通过图像处理技术来位置对准的。希望在与突起6连接的配线4上提供该位置对准标记,且该位置对准标记一般在与形成配线4相同的时间形成。如果第一树脂层3a不是透明的,则为了从配线基板2的表面上识别出位置对准标记,通过激光束机械加工或光蚀刻,在第一树脂层3a的与位置对准标记对应的部分中形成开口。替换地,如果第一树脂层3a和第二树脂层3b都贴合到配线基板2,则通过钻孔等在第一树脂层3a的与位置对准标记对应的部分中形成通孔。
之后,将贴附到安装设备并由安装设备保持的半导体芯片5移动到配线基板2的第一树脂层3a中。这时,安装设备具有能够加热且加压半导体芯片5的结构。当安装设备将所贴附并保持的半导体芯片5加热到等于或高于第一树脂层3a的熔点的温度时,安装设备将半导体芯片5压向已经位置对准后的配线基板2的第一树脂层3a。由于在加热的状态下将半导体芯片5压向第一树脂层3a,因此半导体芯片5的热量传送到第一树脂层3a,以使第一树脂层3a在与半导体芯片5接触的区域及其周围区域中熔化。由此,在半导体芯片5附近的第一树脂层3a被溶化的同时,半导体芯片5容易被移动到第一树脂层3a中。
当半导体芯片5进一步移动到第一树脂层3a中时,最终,突起6贯穿第一树脂层3a,且突起6与配线4连接。在突起6贯穿第一树脂层3a并与配线4连接这段过程期间,第二树脂层3b具有足够高的弹性率,而且,将半导体芯片5压向第一树脂层3a而产生的第二树脂层3b的变形基本不产生破坏。因此,配线4向第二树脂层3b中的任何沉陷都得到极大抑制,且实现了配线4和突起6的牢固紧密接触。
最终,在配线4和突起6被保持为相互紧密接触的状态下,配线基板2和半导体芯片5被冷却,直到硬化了第一树脂层3a。配线基板2和半导体芯片5可被自然冷却,或者被强制冷却。配线基板2和半导体芯片5被冷却至室温,这是由于仅需硬化第一树脂层3a。
在上面的一系列工艺中,为了将施加到半导体芯片5的热量有效地传输到配线基板2,当将半导体芯片5移动到第一树脂层3a中时,希望也对保持配线基板2的台进行加热。然而,如果第二树脂层3b也由热塑性树脂制成,则一旦过分软化第二树脂层3b,就无法足够地保持突起6和配线4的紧密接触压力。因此,优选的是,保持配线基板2的台的温度低于保持半导体芯片5的安装设备的温度。例如,安装设备的温度在200至350℃的范围内选择,台的温度在低于安装设备温度的从50℃到200℃的范围内选择。
由于突起6具有尖端,因此突起6移动到第一树脂层3a中,同时将第一树脂层3a推开,并且其尖端在压向配线4时变形。因此,具有尖端的突起6提供较高的连接可靠性。当半导体芯片5在第一树脂层3a中埋入到希望深度、且突起6至配线4的接合已完成时,安装设备的加热终止。通过在按压半导体芯片5时,测定自半导体芯片5向安装设备施加的负荷,能够测定突起6是否与配线4接合。由于该负荷与突起6的挤压量之间存在相关关系,因此根据施加到安装设备的负荷,可得知突起6的挤压量,即突起6和配线4的接合状态。之后,由于降低了半导体芯片5的温度,因此第一树脂层3a被充分硬化。在保持安装设备的加压、直到达到能够保持突起6和配线4相互接触的弹性率之后,升起安装设备。
由于与突起6连接的配线4的连接表面已经覆盖有第一树脂层3a,因此防止了其在制造工艺期间被氧化和污染。可通过金属扩散结合连接,或者通过由绝缘树脂保持相互接触,来保持突起6和配线4的连接。
如上所述,由于第一树脂层3a由包括热塑性树脂的树脂制成,而第二树脂层3b由在第一树脂层3a的熔点处具有1GPa或更高弹性率的树脂制成,因此通过在将第一树脂层3a加热融化的状态下将半导体芯片5移动到第一树脂层3a中、以及通过保持半导体芯片5的突起6与配线4紧密接触,配线基板4和半导体芯片5可容易地相互连接。
通过之后对第一树脂层3a进行硬化,半导体芯片5在被埋入到配线基板4的状态下得到保持。因此,配线基板4和半导体芯片5保持牢固相互连接。当半导体芯片5移动到第一树脂层3a中时,第二树脂层3b具有足够的弹性率。因此,当按压半导体芯片5时,配线4向第二树脂层3b中的任何沉陷得到极大地抑制,并且提高了配线4和突起6的紧密接触性。
配线基板的绝缘层由无机材料如玻璃、陶瓷等树脂之外的材料制成。使用这种无机材料代替第二树脂层3b以抑制配线4的沉陷。然而,由于这种无机材料易碎且容易破坏,因此在制造工艺中不能容易地控制。根据本实施例,由于任何绝缘层都主要由树脂制成,因此,没有降低可控制性。作为根据本实施例电子设备的一种利用形式,电子设备可构造为BGA设备,并将其安装到如母板等其他基板上。然而,如果在这种应用中,第二树脂层3b由无机材料制成,则由于其线性膨胀系数与其它基板的线性膨胀系数有极大不同,因此,不能确保连接可靠性。根据本发明,由于任何绝缘层都主要由树脂制成,因此其线性膨胀系数基本上与其它基板的线性膨胀系数相同,实现了连接可靠性。
上述特征与半导体芯片5的平面尺寸和电极数目没有关系。因此,上述结构和方法可适用于将一边长度从几mm到多于10mm的范围内的各种半导体芯片5安装到配线基板2上的场合。
图24是示出其中第二树脂层3b的弹性率不满足上述条件、即在第一树脂层3a的熔点处的弹性率小于1GPa的情况的截面图。如图24中所示,如果第二树脂层3b不满足上述条件,则当按压半导体芯片5时产生的力被施加到配线4,导致配线极大地沉陷到树脂中。结果,不能获得充分地压力以保持突起6和配线4相互接触,且连接到突起6的配线4和其下层的配线4a之间的距离变得非常小,易于导致配线4、4a之间绝缘不良或者导致其间的短路。而且,由于半导体芯片自身极大地陷入到配线基板2中,所以第一树脂层3a极大地升高,并很可能与安装设备接触。
以下将描述能用作第一树脂层3a和第二树脂层3b的树脂类型和特性。
第一树脂层3a需要含有热塑性树脂,以使当将半导体芯片5安装到配线基板2上能够熔化、并且在该状态下来按压半导体芯片5。第一树脂层3a也可含有热塑性树脂和其它添加物,只要其能发挥上述的作用。
第二树脂层3b需要具有在第一树脂层3a的熔点处的1GPa或更高的弹性率。只要第二树脂层3b满足该条件,就能够由热塑性树脂或热硬化树脂制成。而且,第二树脂层3b也可使用由热塑性树脂和热硬化树脂组合的复合材料制成。由于第二树脂层3b不仅可由热塑性树脂制成还可由热硬化树脂制成,因此材料选择的范围可以很广。
热塑性树脂大致分类成低于熔点的温度范围内的聚合物链规则正排列的结晶树脂,和即使熔点以下聚合物链也不是规则正排列的非结晶树脂。
图6是示出结晶树脂和非结晶树脂的温度(T)和弹性率(EM)之间关系的图。图6中,结晶树脂具有弹性率曲线100。弹性率曲线100上的Tg1和Tm1分别表示结晶树脂的玻变点和熔点。相似地,弹性率曲线200上的Tg2和Tm2表示非结晶树脂的玻变点和熔点。由于图6用于示出随温度变化的弹性率变化趋势,因此图6中的说明中省略了弹性率的具体值。
从图中可看出,当温度升高时,结晶树脂的弹性率逐步降低。另一方面,非结晶树脂的弹性率基本上恒定直到玻变点(Tg),并且在高于玻变点(Tg)的温度处急剧下降。
因此,在通过第一树脂层3a确保突起6和配线4的相互接触的本发明中,结晶树脂能用于在安装半导体芯片5的工艺中基本上没有热负荷的电子设备。然而,如果在安装半导体芯片5之后,电子设备由于例如流动而承受热负荷,则即使在回流温度范围内,弹性率低的小等级非结晶热塑性树脂也适用于这种电子设备。在如温度循环这样的环境负荷中,即使达到相对高温也能保持弹性率的非结晶树脂能实现连接可靠性。
此外,如果结晶树脂和非结晶树脂具有相同的热阻,则非结晶树脂的熔点低于结晶树脂的熔点。因此,由于能够降低在突起贯穿第一树脂层时的安装温度,因此即使从制造工艺的观点来看,非结晶树脂也是有利的。特别是,如果希望构成第一树脂层3a的树脂抵抗回流热量,则树脂优选是这样一种材料,其熔点在从240到300℃之间,而且具有能够在从190到220℃的回流温度范围内保持突起6和配线4的相互连接的硬度。如果不希望第一树脂层3a的树脂抵抗回流加热,则树脂优选是熔点在从100℃到250℃范围内的材料。
但是,如果结晶树脂和非结晶树脂合成为复合材料,则这种复合材料能显示出如下非结晶特性,即直到玻变点为止,弹性率的降低都很少。因此,复合材料能够克服上述结晶树脂的不足。
结晶树脂可包括PK(聚酮)、PEEK(聚醚醚酮)、LCP(液晶聚合物)、PPA(polyphthal amide)、PPS(聚苯硫化物)、PCT(聚二环己撑乙烯对钛酸盐)、PBT(聚丁烯对钛酸盐)、PET(聚乙烯对钛酸盐)、POM(聚缩醛)、PA(聚酰胺)、PE(聚乙烯)、PP(聚丙稀)等。非结晶树脂包括PBI(聚苯并咪唑)、PAI(聚酰胺酰亚胺)、PI(聚酰亚胺)、PES(聚醚砜)、PEI(聚醚酰亚胺)、PAR(聚芳酯)、PSF(聚砜)、PC(聚碳酸酯)、改变的PPE(聚分宁酯)、PPO(聚苯氧化物)、ABS(聚丙腈丁二烯苯乙烯)、PMMA(聚甲基丙酸甲酯丙烯酸酯)、PVC(聚氯乙烯)、PS(聚苯乙烯)AS(丙烯腈苯乙烯)等。
当选择第一树脂层3a和第二树脂层3b的材料时的一个重要因素除了结晶树脂/非结晶树脂之外,还有线性膨胀系数。关于安装半导体芯片5之后其可靠性,尤其是相对于如温度循环等环境负荷,如果Z方向(厚度方向)上其线性膨胀系数大,则这不利于保持突起6和配线4的相互接触。作为调整线性膨胀系数的手段,一种方法是在树脂中混入具有低线性膨胀系数的填料(精细颗粒)。根据该方法,不仅能在Z方向上调整线性膨胀系数,还能在XY方向(平面方向)上调整线性膨胀系数,因而比较容易而且能获得很好的效果。一些树脂如LCP能通过控制晶体方位,将其线性膨胀系数设置为希望值。然而,LCP的不足在于尽管能在XY方向上容易地调整线性膨胀系数,但是难以在Z方向上调整。然而,如果仅仅在XY方向上的线性膨胀系数的调整就足够了,则LCP可用于本发明。
第一树脂层3a优选的是其热膨胀系数在半导体芯片5的线性膨胀系数和第二树脂层3b的线性膨胀系数之间的范围内,以便保持半导体芯片5和突起6之间的相对于温度变化的可靠连接。尤其是,与半导体芯片5的线性膨胀系数和第二树脂层3b的线性膨胀系数之间的中间值相比,第一树脂层3a的线性膨胀系数更接近半导体芯片5的线性膨胀系数。因此,通过在第一树脂层3a中包括如硅石填料等的具有低线性膨胀系数的材料,优选的是将线性膨胀系数降低至5ppm/℃到60ppm/℃。
然而,通过在将半导体芯片5移动到第一树脂层3a中时施加压力,对突起6和配线4之间的连接进行压缩保持,同时还通过将突起6的高度,例如半导体芯片5和配线4之间的距离减小至约50μm或更少,以减少Z方向上第一树脂层3a的温度所引起的半导体芯片5和配线4之间的尺寸变化的绝对值,由此能够降低Z方向上线性膨胀系数的影响。因此根据本发明,第一树脂层3a的线性膨胀系数不必局限于小于第二树脂层3b的线性膨胀系数。相反,即使第一树脂层3a的线性膨胀系数高于第二树脂层3b的线性膨胀系数,即使第二树脂层3b也可由高硬度、低膨胀材料制成,如在玻璃布中浸渍树脂的一般玻璃环氧树脂材料,以便抑制第一树脂层3a的膨胀,仍能够防止发生由于线性膨胀系数之间的差别导致的连接可靠性的降低。第一树脂层3a的线性膨胀系数由于安装于其上的半导体芯片5的芯片尺寸、突起间隔、突起数目和配线基板2的厚度,其最佳值会发生变化。然而,如果半导体芯片5例如具有10mm×10mm的芯片尺寸,则第一树脂层3a的线性膨胀系数在XY方向上大致表示为60ppm/℃或更小,和在Z方向上大致表示为80ppm/℃或更小。
添加到第一树脂层3a的热固性树脂、以及作为第二树脂层3b的至少一部分的热固性树脂是双酚A环氧树脂、双戊环氧树脂、甲酚酚醛清漆环氧树脂、联二苯环氧树脂、萘环氧树脂、酚醛苯酚树脂、酚醛清漆苯酚树脂等,或者一些这些树脂的复合树脂材料。
以下将描述通过组合上述树脂作为第一树脂层3a和第二树脂层3b的材料而制造的电子设备的具体实例。
(组合实例1)
根据本实例,第一树脂层3a由PEI制成,该PEI是具有250℃熔点的非结晶热塑性树脂,和第二树脂层3b由LCP制成,该LCP是具有350℃熔点的结晶热塑性树脂。半导体芯片5安装到配线基板2上,该配线基板2根据上述工序由该第一树脂层3a和第二树脂层3b构造。构成第二树脂层3b的LCP具有两种类型,在作为PEI熔点附近温度的250℃处,一种类型具有0.7GPa的弹性率,而另一种类型具有1.0GPa的弹性率。
此处使用的配线基板2和半导体芯片5具有以下主要尺寸。配线基板2中,第一树脂层3a和第二树脂层3b中的每一个都具有50μm厚度图案的形式。第二树脂层3b是六层结构,在它上面是单层形式的第一树脂层3a,以使第一和第二树脂层3a、3b结合为七层结构。配线4通过在铜图案上电镀具有厚度在从3到5μm范围内的Ni层和厚度在从0.5到1.0μm范围内的金层来制造。配线4的总厚度约为20μm。配线4被设置在树脂层3a、3b之间、并在配线基板的两个表面上,使得整个配线基板成为八层。包括树脂层3a、3b和配线4的最终配线基板2的总厚度为400μm。由于当挤压组件时树脂层3a、3b被部分地埋入到配线4之间,因此最终配线基板2的总厚度根据配线的密度而不同。半导体芯片5具有10mm×10mm的平面尺寸,0.3mm的厚度,且每一个都具有约57μm高度的480个突起6。
当将半导体芯片5压进配线基板2中时,用于将半导体芯片5安装到配线基板2上的安装设备具有300℃的温度。半导体芯片5的突起6与配线4接触之后,停止对安装设备加热。在安装设备的温度达到200℃时,将安装设备从半导体芯片5上升起。
在上述温度条件下将半导体芯片5安装到配线基板2上,固定确认在突起6和配线4之间的连接状态。如果第二树脂层3b由在250℃处具有0.7GPa弹性率的LCP制成,则由于保持突起6和配线相互接触的压力不足,会出现很多传导故障。而且,当在显微镜下观察突起6和配线4之间的接触部分的截面时,确认配线4在突起6和配线4之间接触的区域中极大地沉陷了。另一方面,如果第二树脂层3b由在250℃下具有1.0GPa弹性率的LCP制成,则较小程度地陷入到树脂层中,则得到配线4的下陷很少、突起6和配线4之间接触压力升高这样的连接性,而且也不会发生由于配线4的沉陷导致的突起6和配线4之间的传导故障。通过测量突起6和配线4之间的传导电阻,可以确定突起6和配线4之间的接触压力是高还是低。压力接触越高,传导电阻就越低,和压力接触越低,传导电阻就越高。
(组合实例2)
根据本实例,第一树脂层3a由在组合实例1中使用的PEI制成,和第二树脂层3b由通过三菱树脂株式会社制造的PEEK系热塑性铜覆层的“IBUKI”制成。“IBUKI”采用结晶PEEK材料作为基板,与非结晶树脂组合以提供非结晶树脂特性,从而即使在高温下弹性率也不容易降低。而且,“IBUKI”由于包含填料,因此防止了线性膨胀系数的降低。用作基板的PEEK材料由于其熔点超出300℃而具有高热阻。用于第一树脂层3a的PEI的熔点比“IBUKI”的熔点低了约50℃。所以在PEI熔点下,“IBUKI”的弹性率高于1GPa。
配线基板2和半导体芯片5的主要尺寸与组合实例1的那些相同。安装设备的温度条件也与组合实例1的那些相同。
根据本实例,配线4的沉陷小,由此保持配线4和突起6牢固地相互结合,且不会发生由于配线4沉陷导致的突起6和配线4之间的传导故障。
(组合实例3)
根据本实例,第一树脂层3a由住友Bakelite株式会社制造的“IBF-3021”制成,其是包括热塑性树脂作为主要成分、并添加了微量热固性树脂的树脂材料,而第二树脂层3b由LCP制成。在作为“IBF-3021”的安装温度范围的200℃到250℃的温度范围内,“IBF-3021”熔化,而且在该温度范围内,LCP的弹性率高于1GPa。
配线基板2和半导体芯片5具有与组合实例1的那些相同的主要尺寸。当将半导体芯片5压向配线基板2时,安装设备具有250℃的温度。在半导体芯片5的突起6与配线4接触时,停止对安装设备加热。在安装设备的温度达到150℃时,从半导体芯片5上升起安装设备。
根据本实例,配线4的沉陷小,由此保持配线4和突起6牢固地相互结合,而且不会发生由于配线4沉陷导致的突起6和配线4之间的传导故障。
(组合实例4)
根据本实例,第一树脂层3a由在组合实例3中使用的“IBF-3021”制成,而第二树脂层3b由聚酰亚胺制成,聚酰亚胺广泛地用作柔性配线基板的材料。聚酰亚胺是非结晶热塑性树脂。在作为“IBF-3021”的安装温度范围的200℃到250℃的温度范围内,“IBF-3021”熔化,且该温度范围内聚酰亚胺的弹性率高于1GPa。
配线基板2和半导体芯片5具有如下主要尺寸:第一树脂层3a具有50μm的厚度,第二树脂层3b具有25μm的厚度,和配线基板2具有75μm的总厚度。配线4通过在铜图案上电镀厚度在从3到5μm范围内的Ni层和厚度在从0.5至1.0μm范围内的金层来制造。配线4具有约20μm的总厚度。半导体芯片5具有6mm×8mm的平面尺寸,0.1mm的厚度,和64个突起6。
当将半导体芯片5压到配线基板2中时,用于在配线基板2上安装半导体芯片5的安装设备具有250℃的温度。半导体芯片5的突起6与配线4接触之后,停止加热安装设备。在安装设备温度达到150℃时,从半导体芯片5上升起安装设备。
根据本实例,配线4仅小程度地沉陷到树脂层中,由此确保配线4和突起6牢固地相互结合,而且不会发生由于配线4的沉陷导致的突起6和配线4之间的传导故障。
第二树脂层3b优选的是在安装半导体芯片5时的温度范围内、即在第一树脂层3a的熔点附近具有尽可能高的弹性率。如果第二树脂层3b由热塑性树脂制成,则其优选为直到熔点附近为止都具有高弹性率的非结晶树脂。例如,可限制为在250℃的非常高的温度下确保弹性率为1GPa或更高的结晶树脂。另一方面,对于非结晶树脂,如在本实例中使用的聚酰亚胺,可从很多类型的更多材料中选择。
以下将描述本发明的进一步优点。
在将半导体芯片5移动到第一树脂层3a中时,通过加热,第一树脂层3a至少在与半导体芯片5接触的部分和其周围部分被熔化或软化,并随着温度的随后降低而硬化。在该温度降低时,半导体芯片5和第二树脂层3b收缩了。半导体芯片5的线性膨胀系数通常小于树脂的线性膨胀系数,使得半导体芯片5的收缩量和第二树脂层3b的收缩量相互不同。然而,由于当温度下降时,在半导体芯片5和第二树脂层3b之间存在的第一树脂层3a保持熔化或软化的状态,因此,由于半导体芯片5的收缩量和第二树脂层3b的收缩量之间的差别产生的应力被第一树脂层3a缓解。
当将半导体芯片5移动到第一树脂层3a中时,在半导体芯片5的周围,被半导体芯片5挤出的第一树脂层3a上升。随着第一树脂层3a上升到高层位,第一树脂层3a的一部分达到半导体芯片5的表面,且构成第一树脂层3a的树脂可能贴附到安装设备上,这易于使得安装设备不能使用。随着半导体芯片5越来越深地移动到第一树脂层3a中,更易于发生第一树脂层3a的升高。特别是,如果半导体芯片5例如具有0.15μm或更薄的薄厚度,则,即使第一树脂层3a稍微上升,第一树脂层3a的树脂也会贴附到安装设备。而另一方面,第一树脂层3a不仅构成部分的配线基板2,而且也用于将半导体芯片5保持在配线基板2上。因此,如果第一树脂层3a的厚度不够,则不能可靠地确保半导体芯片5位于适当位置。
具有数十μm的厚度的第一树脂层3a通常由膜形式的材料制成。由于膜厚度是通过膜制造装置实时控制的,因此膜形式的第一树脂层3a的厚度的精确度很高。因此,能高度精确地控制第一树脂层3a的厚度。即使半导体芯片5的厚度很薄,第一树脂层3a的厚度也能通过根据半导体芯片5的厚度和尺寸以及由半导体芯片5向第一树脂层3a中的移动挤出的树脂量,来选择最佳膜厚度来控制,以使第一树脂层3a无法移动到第一树脂层3a中的半导体芯片5的表面。因此,根据本实施例,通过控制第一树脂层3a厚度的极其简单工艺,能容易地防止保持半导体芯片5的树脂贴附到安装设备上。结果,未来防止树脂贴附到安装设备上,安装设备的尺寸不需要小于半导体芯片5。而且由于能使用尺寸大于半导体芯片5的安装设备,因此安装设备不将局部应力施加到薄的半导体芯片5,且当将半导体芯片5移动到第一树脂层3a中时,该半导体芯片5不易于被损坏。而且由于能够在与第二树脂层3b之间来确定对于第一树脂层3a而言的必要性质,因此可构成第一树脂层3a的树脂的种类选择范围很广。
在上面描述中,已经公开了构成配线基板2的第一树脂层3a和第二树脂层3b的特性,其使得第二树脂层3b在第一树脂层3a熔点处的弹性率为1GPa或更高。然而,在实际的制造工艺中,在将半导体芯片5移动到第一树脂层3a中时,为了可靠地熔化第一树脂层3a的在其上安装有半导体芯片5的区域,考虑到来自于配线基板2自身和半导体芯片5的热辐射、以及加热设备温度控制变化,第一树脂层3a的温度也可以高于第一树脂层3a的熔点。在该情况下,如果第二树脂层3b由热塑性树脂制成,则第一树脂层3a的温度T℃优选被控制在TM℃≤T≤TM+10℃,其中TM℃表示第一树脂层3a的熔点,以使第二树脂层3b不被第一树脂层3a的热量软化。由此希望在第一树脂层3a和第二树脂层3b之间建立关系,以在TM℃≤T≤TM+10℃的温度范围内,第二树脂层3b的弹性率比第一树脂层3a的弹性率高1GPa或更多。因此,能更有效地防止由于安装半导体芯片5时由半导体芯片5导致的配线4的任何沉陷。
上面已经描述了在加热熔化第一树脂层3a的状态下将半导体芯片5移动到第一树脂层3a中。然而,如果第一树脂层3a由即使在低于其熔点的温度下也会软化到让突起6贯穿第一树脂层3a的程度的材料制成,则半导体芯片5也能够在低于熔点的温度下被移动到第一树脂层3a中。此时,当半导体芯片5被压向配线基板2时,需要第一树脂层3a的弹性率为1GPa或更大。
为了进一步增加可靠性,优选的是应该增加配线自身的硬度,以使配线4不大容易沉陷到第二树脂层3b中,或者应该降低按压半导体芯片5的负荷,由此降低第二树脂层3b的任何变形。增加配线自身硬度的具体手段是向配线4的材料中添加Ni等高硬度金属、或者增加配线4的厚度等。通过增加配线自身的硬度,能够有效增加突起6和配线4之间的接触压力。重要的是,降低按压半导体芯片5的负荷,而不降低突起6和配线4之间的接触压力。为了实现相同负荷下的较高接触压力,可降低突起6的直径,或者突起6可由低硬度材料制成,以便半导体芯片5的压入能容易地导致突起变形。
本实施例不仅可用于一般的半导体芯片5的安装,而且只要在其一个表面上具有突出电极,本实施例也可用于在电路面上安装二次级配线连接的半导体芯片、晶片和CSP等封装电子部件、或无源电子部件的安装。
以下将描述根据本发明其他实施例的结合了上述基本结构的各种电子设备。在以下描述的实例中,第一树脂层3a和第二树脂层3b特性的相互关系、可采用材料、以及可适用的电子部件等都与关于上述实施例的上述那些相同,除非另有说明。
图7示出了使用配线基板2的电子设备,该配线基板2是通过在形成有配线4的第二树脂层3b上推叠第一树脂层3a来制成的,该第一树脂层3a上形成了作为导电图案的第二配线4a。与上述相同,当将半导体芯片5移动到第一树脂层3a中时,通过由突起6贯穿第一树脂层3a并与配线4接触,半导体芯片5和配线基板2接合起来。配线基板2的制造方法可以使用如下方法:在第二树脂层3b上图案化配线4,之后叠置在其一个表面上形成有铜箔的铜覆绝缘树脂层,并图案化该铜箔以形成设置有配线4a的第一树脂层3a。配线4的图案化可通过在制造配线基板时通常使用的相减工艺、相加工艺或半相加工艺来执行。在此,尽管使用了连续叠置各层的构造工艺,但是一般制造工艺也可使用,比如在各树脂层3a、3b上单个地形成配线4、4a之后、再一起叠层的工艺方法。
图8示出了BGA型半导体封装,其中将第一树脂层3a上的导电图案形成为接地图案(ground pattern)7,和该接地图案7通过通孔8连接到作为配线基板内层的地7a。在配线基板的两个表面上形成焊料抗蚀剂9。在第二树脂层3b的下表面(与第一树脂层3a相反侧的表面)上设置多个焊垫,且其通过通孔8a连接到在第二树脂层3b上的配线4和地7a。在焊垫上设置焊料球31。由于在表面侧上的导电图案被形成为接地图案7,因此其提供了噪声屏蔽的效果。
图9是示出其中图7中示出的配线基板被应用到具有多个配线层的基板中的实例的截面图。在该实例中,配线4和绝缘层交替地叠置到核心层23的两个表面上,以提供多层配线基板。各绝缘层包括被构造为由热塑性树脂制成的第一树脂层3a的表面层,和被构造为第二树脂层3b的其他绝缘层。第一树脂层3a具有在从30到100μm范围内的厚度。
核心层23可包括玻璃环氧树脂基板,且第二树脂层3b中的每一个都可由构造绝缘树脂制成。核心层23和第二树脂层3b中的树脂是热固性树脂。如果第一树脂层3a由热塑性树脂制成,则其它层由热固性树脂构成,特别是,选择第一树脂层3a和第二树脂层3b的材料,使得在第一树脂层3a的熔点下,第二树脂层3b的弹性率为1GPa,则尽管由于将半导体芯片5移动到第一树脂层3a中时的热量导致第一树脂层3a被足够软化且变形程度很大,但是第二树脂层3b和核心层23虽被软化,但变形非常小。因此,可以采用与上述相同的顺序,将半导体芯片5安装到本实施例中的多层配线基板上。
在所示实例中,除了被半导体芯片5的突起贯穿的第一树脂层3a之外的层都由热固性树脂制成。然而,所有绝缘层可以都由热塑性树脂制成。这种情况下,第一树脂层3a由熔点低于第二树脂层3b熔点的材料制成,以使得在第一树脂层3a的熔点下,第二树脂层3b的弹性率为1GPa或更高。因此,如果对配线基板进行加热,以使得当半导体芯片5进入第一树脂层3a中时,在第二树脂层3b能够维持1GPa或更高的弹性率的范围内达到第一树脂层3a的熔点以上的程度,则能够在仅仅是第一树脂层3a溶化的状态下,半导体芯片5进入到第一树脂层3a。而且,如果所有绝缘层都由热塑性树脂制成,则配线基板被构造为成本有利的整体叠层基板。
图10是采用配线基板的电子设备的截面图,该配线基板包括由热塑性树脂制成的第一树脂层3a作为核心层。在此,配线基板使用铜覆基板制造,该铜覆基板包括在第一树脂层3a的两个表面上形成铜箔。通过一般制造工艺制造的配线基板包括通过根据相减工艺图案化铜箔形成的配线4、4a和施加到这两个表面层的焊料抗蚀剂9。如上所述,通过在第一树脂层3a软化或者溶化的状态下将半导体芯片5移动进入第一树脂层3a,突起6贯穿第一树脂层3a而与配线4接触,将半导体芯片5安装到配线基板上。在第一树脂层3a的下层的焊料抗蚀剂9需要在第一树脂层3a的熔点处具有1GPa或更高的弹性率。除非另有说明,在本实例中,根据本发明的第二树脂层起到焊料抗蚀剂9的作用。
图11是采用配线基板的电子设备的截面图,该配线基板包括在其内外两个表面上形成有配线4、4a的第二树脂层3b作为核心层。在第二树脂层3b的内表面上形成焊料抗蚀剂9,而在其外表面侧上形成由热塑性树脂制成的第一树脂层3a来用作焊料抗蚀剂。根据与上述相同的工序,通过使得突起6与配线4接触,将半导体芯片5安装到配线基板上。根据本实例,第一树脂层3a兼有焊料抗蚀剂的功能和半导体芯片5的密封树脂的功能。由于第一树脂层3a用作焊料抗蚀剂,因此配线4可保持与电子设备的外部绝缘。如果在配线基板的内表面侧的焊料抗蚀剂9中,在与配线4a对应的位置处形成开口,且如果在该开口处设置用于与外部连接的端子,则该电子设备能用作半导体封装。
图12示出采用了多层结构的配线基板的电子设备,该多层结构包括第一树脂层3a、第二树脂层3b和第三树脂层3c。在图12中示出的实例中,配线基板具有五个绝缘层。在内表面侧的三个层形成为第二树脂层3b,与外表面的第二树脂层3b相邻地叠置第一树脂层3a。第三树脂层3c叠置成与第一树脂层3a相邻。在各树脂层3a至3c之间分别设置配线4,半导体芯片4a和5b分别被保持在第一树脂层3a和第三树脂层3c中。第一树脂层3a和第三树脂层3c由热塑性树脂或半硬化片等制成。
根据本实施例的电子设备能根据以下工序制造。首先,在第二树脂层3b上形成第一树脂层3a,之后根据上述工艺将半导体芯片5a压到第一树脂层3a中,在该状态下硬化第一树脂层3a。现在完成了半导体芯片5a的安装。之后,在半导体芯片5a上形成第三树脂层3c,并根据上述工艺将半导体芯片5b按压到第三树脂层3c中,在该状态下硬化第三树脂层3c。
需要在第一树脂层3a、第二树脂层3b和第三树脂层3c之间建立如下关系。关于在叠置方向上设置成相互相邻的第一树脂层3a和第二树脂层3c之间的关系,如上所述,在第一树脂层3a的熔点下,第二树脂层3b的弹性率为1GPa或更高。关于第一树脂层3a和第三树脂层3c之间的关系,在第三树脂层3c的熔点下,第一树脂层3a的弹性率是1GPa或更高。如果选择第一树脂层3a、第二树脂层3b以及第三树脂层3c的材料、以满足上述关系,则可根据图12中所示的装置制造能防止发生配线4沉陷到树脂层中、并且配线基板和半导体5a、5b相互可靠连接的电子设备。
在本实例中,将单层的第三树脂层3c叠置到第一树脂层3a上。不过也可采用两层或更多层的树脂层3c,并且半导体芯片可分别移动到各第三树脂层3c中。这种情况下,在叠置方向上相互相邻的这些第三树脂层3c的关系同样是,选择各第三树脂层3c的材料,使得在上侧的层的熔点处,下侧的层具有为1GPa或更高的弹性率。
图13是其中半导体芯片5安装到多层配线基板的电子设备的截面图。根据本实例的配线基板包括核心层23,在其两个表面上叠置了多个绝缘层,其间分别插入配线4、4a、4b。在核心层23的外表面上,这些绝缘层包括设置于核心层23上的第二树脂层3b和设置于第二树脂层3b上的两个第一树脂层3a。在核心层23的内表面上,这些绝缘层包括两个第二树脂层3b。在配线基板的该外表面和内表面上形成了焊料抗蚀剂9。半导体芯片5具有贯穿两个第一树脂层3a并连接到配线4的突起6。由于半导体芯片5移动到多个第一树脂层3a中,因此配线4b添加到这些层之间。因此,提高了电子设备的结构细节和配线方面的自由度。
根据本实例,与图12中示出的实例不同,如果在各第一树脂层3a的熔点处,第二树脂层3b都具有1GPa或更高的弹性率,则各第一树脂层3a既可以由相同材料制成,也可以由不同材料制成。第一树脂层3a的数目不限于两个,而是可以为三个或更多。
可在第一树脂层3a之间形成配线4b以接地。例如,如果在图13中示出的半导体芯片5上还安装了其他半导体芯片(未示出),并且配线4a被用作信号线,那么其下部的层中的配线4b接地,从而提供半导体芯片之间的相互噪声屏蔽效果,由此能够防止电子设备出现误操作,并允许电子设备以高速度操作。
图14示出采用配线基板的电子设备,在该配线基板中,第二树脂层4b叠置于核心层23的内外两个表面上,其间插入配线4a,而且第一树脂层3a叠置于第二树脂层4b的表面上,其间插入配线4。两个半导体芯片5移动到并安装到外表面和内表面上的相应第一树脂层3a中,使得其突起6贯穿第一树脂层3a并连接到配线4。各半导体芯片5彼此逆向安装,其突起6相互面对。如果第一树脂层3a设置于配线基板的内外两个表面上,则可以制造如此在其两个表面上安装半导体芯片5的设备。在各第一树脂层3a表面上的配线4b覆盖有焊料抗蚀剂9。
例如,可如下制造根据本实例的电子设备。首先,以上述方式将一侧的半导体芯片5安装于配线基板上。之后,将在一侧安装有半导体芯片5的配线基板翻转,并将另一个半导体芯片5安装到已配线基板的相对表面上,该相对表面是与其上已经安装半导体芯片5的上述表面相对的表面。在本实例中,在配线基板的两个第一树脂层3a之间插入两个第二树脂层3b和核心层23,以使热量不会在各第一树脂层3a之间传送。结果,当为了安装两个半导体芯片5而对半导体芯片5所进入的第一树脂层3a进行加热时,其上已经安装有半导体芯片5的第一树脂层3a未被软化或熔化,并且依旧保持已经安装的半导体芯片5与配线4之间连接状态。
图15示出了如下实例,其中在图1中所示的通过将半导体芯片5移动到在第二树脂层3b上设置的第一树脂层3a(其间插入配线4)中、将配线4和突起6相互连接而构成的外表面和内表面上,还叠置了附加绝缘层24,其间插入配线4a。附加绝缘层24可仅仅设置于外表面侧,或仅仅设置于内表面侧。附加绝缘层24的数目可根据电子设备所需的特性等来任意选择。如果附加绝缘层24设置在外表面侧,则半导体芯片5完全埋入到配线基板中。附加绝缘层24可由热塑性树脂、半硬化片等树脂制成。各附加绝缘层24的厚度在从30到100μm的范围内。如图15中所示,可在外表面和内表面上设置配线和焊料抗蚀剂9。为了制造具有图15中所示结构的设备,在形成第一树脂层3a之后和在第一树脂层3a上形成附加绝缘层24之前,将半导体芯片5安装于第一树脂层3a上。
由于根据本实例的设备能如上所述地以低成本制造,因此最终产品的成本低于将半导体芯片5安装到一般配线基板上的情况,而且,由于在其中内置了半导体芯片5,因此可以高密度地安装芯片部件,结果能降低安装本设备的产品的尺寸。由于在电子设备中内置了半导体芯片5,因此,配线4、4a被形成为内层,结果,将用于在内层中缠绕配线的通孔以及其上附加的结构也被小型化。因此,缩短了配线的整体长度。
通过采用上述结构,当设备由于掉落冲击、震动或者温度循环等而承受外部应力时,能够防止外部应力集中到半导体芯片5的端面上。因此,半导体芯片5和配线基板之间的连接可靠性增加了,而且能扩展电子设备的应用范围。即使在图12中所示结构中,也同样能够整合在配线基板中的两个半导体芯片5a、5b之中的半导体芯片5a。
图16示出了一种设备,其中在图10中所示结构中,暴露出半导体芯片5的区域被作为附加绝缘层的涂覆树脂25密封。它的其它结构细节与图10中所示结构的那些相同,即将第一树脂层3a用作核心层,在其两个表面上具有配线4、4a,并且两面的配线4、4a分别被相应额焊料抗蚀剂9涂覆,并且各焊料抗蚀剂9之中的、在经由与突起6相连的配线4而被叠置的一侧的焊料抗蚀剂9用作第二树脂层,且其中半导体芯片5被保持在第一树脂层3a中,并通过由贯穿第一树脂层3a的突起6a与配线连接,而被安装在适当位置。通过分配器或丝网印刷工艺等形成涂覆树脂25。涂覆树脂25加强了半导体芯片5的上表面,并使得设备表面平坦。由于内置了半导体芯片5,因此本实例提供与图15中所示实例相同的优点。
图17示出了一种设备,其具有图16中示出的通过涂覆树脂25密封半导体芯片5的结构,而且叠置安装了其他半导体芯片26。其他半导体芯片26在与由涂覆树脂25密封的半导体芯片5的位置重合的位置处,被安装到第一树脂层3a上,并连接到配线基板第一树脂层3a上的配线4a。用未充满树脂27填充其它半导体芯片26和配线基板之间的间隙。根据上述工艺,将半导体芯片5安装到配线基板上。在安装其它半导体芯片26时,可使用根据现有技术的倒装芯片的压接工艺。在该情形中,优选的是,未充满树脂27是在低于第一树脂层3a熔点的温度下硬化的树脂。替换地,也可使用能以低负荷安装半导体芯片的焊料熔化工艺。然而,经常是使用一般的回流焊接将其它半导体芯片27安装到适当位置。为了防止当将半导体芯片26安装到适当位置时的热量导致半导体芯片5的连接部分被破坏,将非结晶树脂、或非结晶树脂和结晶树脂的复合材料用作第一树脂层3a的材料是有效的,该非结晶树脂能够确保在相对较高温度220℃下是坚硬的,该温度是无铅焊料的熔点。
在安装其它半导体芯片26的工艺中,在半导体芯片26下方的凹凸影响未充满树脂27的可流动性并导致产生孔隙。覆盖半导体芯片5的涂覆树脂25对于减少两个半导体芯片5、26之间的凹凸是有效的,由此能够用未充满树脂27有效地填充间隙。
图18是采用基于图8中所示结构的配线基板的实例的截面图,其中两个附加绝缘层24叠置于第一树脂层3a上,该第一树脂层3a具有在安装半导体芯片5的区域附近插入其间的配线4a。配线基板包括第二树脂层3b,在第二树脂层3b上设置的、之间插入配线4的第一树脂层3a,以及在第一树脂层3a上设置的、之间插入配线4、例如由树脂材料制成的附加绝缘层24。附加绝缘层24具有在安装半导体芯片5的区域中形成的开口。例如在可通过构造工艺制成配线基板的情形中,附加绝缘层24中的开口是在希望的绝缘层(此处是每个绝缘层24)中执行冲孔等钻孔工艺来执行的。半导体芯片5被插入到附加绝缘层24中的开口中,并以与上述相同的方式安装到第一树脂层3a上。
在制造配线基板时,能够使用如下相加工艺:在第二树脂层3b上图案化配线4,之后在其一个表面上叠置形成有的第一树脂层3a,图案化第一树脂层3a上的铜箔以形成配线4a,之后在其一个表面上叠置形成有铜箔的附加绝缘层24,以及图案化在附加绝缘层24上的铜箔以形成配线4a。替换地,也可以根据制造多层配线基板的一般工艺来制造配线基板,该一般工艺例如是在树脂层3a、3b和附加绝缘层24上形成配线4、4a、并将它们一起叠置的工艺。然而,在第一树脂层3a和附加绝缘层24上,并不是必须要形成配线4、4a的。树脂层3a、3b和附加绝缘层24的数目可根据设备所需的特性、性能等来选择。例如,可如图18中所示提供多个附加绝缘层24。本实例具有实质上与其中将半导体芯片5内置到配线基板中的设备相同的机械特性。然而,由于半导体芯片5具有通过配线基板中的开口暴露出的表面,因此将散热器(未示出)贴附到半导体芯片5的表面上,以增加半导体芯片5的散热性。
在本实例中,使用具有开口的配线基板,在其开口中安装半导体芯片5。因此,与图15中所示的芯片内置型设备的制造工艺相比,实际上具有与芯片内置型设备相同的效果,而且由于能够在完成了配线基板的一系列制造工艺之后再安装半导体芯片5,所以能够使得制造工艺简单。在图18中示出的实例中,在配线基板的内表面上形成用于与外部连接的端子相连接的焊垫。通过在该焊垫上提供端子,设备可用作半导体封装。
图19A和19B示出其中在单个第一树脂层3a上安装多个半导体芯片5的电子设备。图19A是在未安装半导体芯片5状态下的配线基板的平面图,和图19B是电子设备的截面图。在图19A中,用点划线表示半导体芯片5的安装位置。
根据本实例的设备采用了图8中所示结构。在第一树脂层3a上形成的表面层导电图案被构造为接地图案4g。在配线基板上安装两个半导体芯片5。在分别安装了半导体心片5的两个区域的整个外部,形成接地图案4g。在第一树脂层3a下方叠置两个第二树脂层3b,其间插入配线4、4a。层间配线通过通孔8相互连接。在最下层中的接地图案4g和配线4a被焊料抗蚀剂9覆盖。
半导体芯片5的突起连接到在第一树脂层3a和第二树脂层3b之间的配线4的顶端上设置的焊垫30。与半导体芯片5的突起连接的配线4通过通孔8连接到下层中的配线4a。
在本实例中,在表面层上的导电图案被构造为接地图案4g的配线基板中,半导体芯片5的突起连接到内层中的配线4。由于与半导体芯片5的突起连接的配线4不需要通过通孔8连接到其它层,因此可以减少通孔8的数目,并且能实现高密度的安装。
以下将具体描述上述特征。将在基板上安装的两个或多个半导体芯片连线,并且在基板的全部表面层上设置用于噪声屏蔽的接地图案。以下将分析从一个半导体芯片到其他半导体芯片的信号线路径。在半导体芯片中,通常,信号线是全部端子数的1/2至1/3,其它的端子是电源或接地端子。如果假设半导体芯片具有100个外部端子且50个端子连接到信号线,则在其中半导体芯片安装于基板表面层上的现有技术结构中,所有信号线都需要通过通孔连接到内层,并经过表面层上的接地图案下方的层,以提供噪声屏蔽,而且之后需要通过其他通孔,从内层连接到表面层上的半导体芯片。由于需要50个端子从表面层连接到内层,并需要50个端子从从内层连接到表面层,因此,需要为信号线数目两倍的总共100个通孔。在根据本发明的装置中,其中芯片部件连接到内层中的配线,能够通过一层中的直接配线来连接多个芯片部件。因此,在表面层和内层之间不需要通孔,且无需表面层和内层之间的全部100个通孔。
根据本实例,由于在配线基板的表面层中,半导体芯片5附近不需要形成通孔,因此可以将未被接地图案4g覆盖的区域最小化,从而增加屏蔽效果。例如,尽管理想的是在半导体芯片5附近的整个区域中提供接地图案4g,但是实际上,当半导体芯片5移动到第一树脂层3a中时,树脂材料上升到半导体芯片5附近。因此,考虑到树脂材料的上升,将半导体芯片5的边缘和接地图案4g之间的间隙设置为约0.5mm。
图20是一个实例的截面图,其中封装的电子部件35是在埋入到配线基板中上覆半导体芯片5的位置中的第一树脂层3a上安装的。配线基板与图10中的相同,且包括在两个表面上都有配线4a、4b的第一树脂层3a的两个表面上形成的焊料抗蚀剂9。如上所述,半导体芯片5被安装在适当位置处,其突起贯穿第一树脂层3并连接到配线4。通过印刷工艺在第一树脂层3a上设置的配线4端部上形成的焊垫上提供焊糊。通过在焊垫上确定导线端子的位置并进行回流焊接,对电子部件35进行表面安装。
在本实例中,如果第一树脂层3a由热塑性树脂制成,则希望其是在无铅焊料熔点220℃的相对高温下保持因此的非结晶树脂、或者是非结晶树脂和结晶树脂的复合材料,以便在回流温度下不会破坏半导体芯片5的连接部位。
图21A和21B示出了一个实例,其中将图28A和28B中示出的BGA应用于本发明。图21A是其上没有安装半导体芯片5、36的配线基板的平面图,图21B是半导体封装的截面图,在所述半导体封装中,在图21A中示出的配线基板上安装了两个半导体芯片5、36。在图21A中,安装半导体芯片5的位置由点划线表示。
在本实例中,半导体芯片5的突起与第二树脂层3b上的配线4端部处的内层中的焊垫30相连接,其他半导体芯片36被表面安装到处于其电路朝上的面朝上状态中的半导体芯片5上。在第一树脂层3a上,用于连接至其他半导体芯片36的焊垫33被设置于焊垫30附近,且通过接合引线34连接到其他半导体芯片36的电极(未示出)。焊料球21被设置在配线基板相反表面上的不覆盖有焊料抗蚀剂9的区域中。在本实例中,半导体芯片5的突起被连接到内层中的配线,以提供以下优点:在配线基板的表面层上,不需要在半导体芯片5附近提供用于将连接到半导体芯片5的配线连接到配线基板的内层的通孔。因此,降低了通孔的数目。由于用于连接到其他半导体芯片36的焊垫33被设置在半导体芯片5附近,因此缩短了接合引线34。而且,根据本实施例,封装具有高密度芯片的半导体封装,且降低了配线层的数目。
图22是应用了本发明的功能模块50的示意图,其中半导体芯片52至55被安装到配线基板51的两个表面上,图23是用于与图22中所示功能模块50相比较的现有技术功能模块70的示意图。
图23中所示功能模块70是一般结构,其中半导体封装72至75被安装在配线基板71的两个表面上。为了在如移动电话的功能模块上使用,半导体封装主要具有在四个方向中的每一方向上都具有从5到15mm范围内的平面尺寸和从1.0至1.4mm范围内的安装高度。安装于配线基板71上的半导体封装72至75具有以下尺寸:半导体封装74具有7mm×7mm的平面尺寸和1.2mm的安装高度。半导体封装75具有15mm×15mm的平面尺寸和1.5mm的安装高度。半导体封装72具有10mm×10mm的平面尺寸和1.4mm的安装高度。半导体封装73具有7mm×7mm的平面尺寸和1.2mm的安装高度。配线基板71具有6个配线层,厚度为0.8mm,和当需要每个半导体封装都需要封装尺寸+3mm的安装面积时,平面尺寸28mm×28mm。因此,容易总结出,具有安装于其上的半导体封装72至75的现有技术的功能模块70具有28mm×28mm的平面尺寸和约3.6mm的厚度。
假设图22中示出的功能模块包括电子设备,其中在图23中示出的半导体封装72至75中密封的半导体芯片根据上述工艺直接安装在至少具有第一树脂层3a和第二树脂层3b的配线基板51上。还假设半导体芯片52至55的尺寸是图23中所示半导体封装72至75的尺寸的百分之70。结果,半导体封装52至55具有以下平面尺寸:半导体芯片54具有4.9mm×4.9mm的平面尺寸。半导体芯片55具有10.5mm×10.5mm的平面尺寸。半导体芯片52具有7mm×7mm的平面尺寸。半导体芯片53具有4.9mm×4.9mm的平面尺寸。还假设半导体芯片52至55中的每一个都具有0.1mm的厚度并埋入到配线基板51中达该厚度一半的深度。半导体芯片52至55中的每一个都具有0.05mm的安装高度。希望配线基板51具有减少数目的四个配线层,这是由于根据本发明配线直接连接到内层。这种情况下,如果每个半导体芯片的安装面积都是芯片尺寸+1mm,则配线基板51具有0.6mm的厚度和17.4mm×17.4mm的平面尺寸。
基于上述分析,具有17.4mm×17.4mm平面尺寸和0.7mm厚度的于图50中示出的功能模块50能实施与现有技术功能模块70相同的功能,功能模块70包括半导体封装72至75。根据本实例,根据本发明的原理,希望模块的面积降低62%,且其厚度降低81%,导致尺寸和厚度的明显降低。
现在将使用其上安装有半导体封装的功能模块和其上直接安装有半导体芯片的功能模块,对现有技术的结构和根据本发明的结构进行相互比较。
这样比较的原因如下。根据现有技术,配线基板中,通孔的焊接区(land)的直径接近200μm,通孔布局间距接近300μm。如果半导体芯片、特别是具有多于300个管脚的多管脚半导体芯片直接安装到配线基板上,则需要多个通孔。因此,必需将来自于半导体芯片的配线延伸到设置通孔的范围,从而对在其上安装了半导体封装的功能模块的尺寸降低的效果产生了限制。至今,为了更好的可控制性,一般实践是构造具有安装于其上的半导体封装的功能模块,而不是具有直接安装于其上的半导体芯片的功能模块。
根据本发明,由于半导体芯片的突起直接连接到配线基板内层中的配线,因此,通孔数目极大地降低。因此,具有半导体芯片直接安装于配线基板上的电子设备的尺寸急剧地降低了。由于通孔数目极大地降低了,因此配线较半导体芯片安装于配线基板表面上的现有技术情况被制作得更短。较短的配线对于减少由于电信号衰减和自配线拾取的噪音导致的信号质量变差是有效的。
本发明可以实现小尺寸、高密度半导体封装或具有卓越电性能的功能模块,以降低电子设备的尺寸和厚度,并提供便宜且有吸引力的产品。
功能模块可以是各种模块形式,以用在移动装置如移动电话机中,例如照相机模块、液晶模块和RF模块、无限LAN模块、蓝牙(注册商标)模块、包括组装到一个封装中的多个芯片的系统内封装模块等。
根据本发明的电子设备不限于任何特性类型,而是可以为所有类型的电子设备,例如包括CPU、逻辑电路、存储器等的半导体芯片。如果单个半导体芯片被构造为根据本发明的半导体封装,则将其实现为小尺寸、薄型封装,其能以较高产量制造,具有较高可靠性,并和成本比现有技术半导体封装的低。
如果根据本发明的电子设备、功能模块或半导体封装结合到电子装置中,则包括移动电话机、数字静止照相机、PDA(个人数字助理)、笔记本个人电脑等的移动设备可进一步降低尺寸和厚度,并使其添加值增加。而且,如果本发明用于终端产品如计算机、服务器等,则由于其具有卓越的特性并能用高密度芯片封装,因此希望其具有增加的性能。

Claims (28)

1.一种电子设备,包括
配线基板,其包括相互叠置的第一树脂层和第二树脂层,其间插入配线;
至少一个芯片部件,在其一个表面上设置有突起电极;
通过将所述芯片部件移动到所述第一树脂层中,所述突起电极与所述配线接触,所述芯片部件连接到所述配线;
所述第一树脂层含有至少一种热塑性树脂,所述第二树脂层在所述第一树脂层熔点处的弹性率为1Gpa或更高;
所述电子设备还包括至少一个绝缘层,其被设置在所述第一树脂层上、并在安装有所述芯片部件的区域中具有开口。
2.如权利要求1的电子设备,其中所述第一树脂层含有非结晶树脂、或结晶树脂与非结晶树脂的复合材料。
3.如权利要求1的电子设备,其中所述第一树脂层的线性膨胀系数在所述芯片部件的线性膨胀系数和所述第二树脂层的线性膨胀系数之间。
4.如权利要求1的电子设备,其中与所述芯片部件的线性膨胀系数和所述第二树脂层的线性膨胀系数之间的中间值相比,所述第一树脂层的线性膨胀系数更接近所述芯片部件的线性膨胀系数。
5.如权利要求1的电子设备,其中所述第一树脂层含有填料。
6.如权利要求1的电子设备,还包括导体图案,该导体图案是在所述第一树脂层中的与所述突起电极所接触的配线所在的表面相对的表面上形成的。
7.如权利要求6的电子设备,其中所述导体图案包括除了所述配线之外的配线。
8.如权利要求6的电子设备,其中所述导体图案包括接地图案。
9.如权利要求1的电子设备,其中所述配线基板包括在所述第一树脂层上叠置的第三树脂层,其间插入除了所述配线之外的配线,所述第三树脂层含有热塑性树脂;
所述第一树脂层在所述第二树脂层的熔点下具有1GPa或更高的弹性率;和
其中除了所述芯片部件之外的、并在其一个表面上形成有突起电极的芯片部件被移动到所述第三树脂层内,所述突起电极与所述其它配线接触,从而所述除了所述芯片部件之外的芯片部件连接到所述除了所述配线之外的配线。
10.如权利要求1的电子设备,还包括覆盖所述芯片部件的附加绝缘层。
11.如权利要求10的电子设备,其中所述绝缘层包括设置在所述配线基板表面上的涂覆层。
12.如权利要求1的电子设备,其中具有所述开口的多个所述绝缘层被叠置,其间插入与所述配线不同的配线。
13.如权利要求1的电子设备,还包括在与所述第一树脂层保持的芯片部件重合的位置上安装的电子部件。
14.如权利要求13的电子设备,其中所述电子部件包括芯片部件或具有导线的部件,其被安装在所述第一树脂层上,并与所述第一树脂层上形成的配线相连接。
15.如权利要求13的电子设备,其中所述电子部件包括芯片部件和在其表面上设置的端子,所述表面面对与所述第一树脂层保持的芯片部件相反的一侧,所述端子通过接合引线与所述第一树脂层上设置的电极焊垫相连接。
16.如权利要求1的电子设备,其中所述第一树脂层保持多个所述芯片部件,并且多个所述芯片部件与所述第一树脂层和所述第二树脂层之间的所述配线的一部分直接连接。
17.一种包括如权利要求1的电子设备的功能模块。
18.一种包括如权利要求17中的功能模块的电子装置。
19.包括如权利要求1中所述电子设备的半导体封装,其中所述芯片部件包括半导体芯片,该半导体封装具有外部连接端子,用于与除了所述电子设备之外的设备电连接。
20.一种包括如权利要求19的半导体封装的电子装置。
21.一种配线基板,该配线基板上安装了在其一个表面上形成有突起电极的至少一个芯片部件,包括:
第一树脂层;
在所述第一树脂层上叠置、且其间插入配线的第二树脂层,该配线与移动到第一树脂层中的芯片部件的所述突起电极相接触;
所述第一树脂层含有至少一种热塑性树脂,并且所述第二树脂层在所述第一树脂层的熔点下具有1GPa或更高的弹性率;
所述配线基板还包括至少一个绝缘层,该绝缘层在所述第一树脂层上设置,并在安装有所述芯片部件的区域中具有开口。
22.如权利要求21的配线基板,其中所述第一树脂层含有非晶树脂、或者结晶树脂和非晶树脂的复合材料。
23.如权利要求21的配线基板,其中所述第一树脂层的线性膨胀系数在从所述芯片部件的线性膨胀系数和所述第二层树脂的线性膨胀系数之间的范围内。
24.如权利要求23的配线基板,其中与所述芯片部件的线性膨胀系数和所述第二树脂层的线性膨胀系数之间的中间值相比,所述第一树脂层的线性膨胀系数更接近所述芯片部件的线性膨胀系数。
25.如权利要求21的配线基板,其中所述第一树脂层含有填料。
26.如权利要求21的配线基板,还包括导体图案,该导体图案是在所述第一树脂层表面上的、与所述突起电极所接触的配线所在的表面相对的表面上形成的。
27.如权利要求26的配线基板,其中所述导体图案包括除了所述配线之外的配线。
28.如权利要求21的配线基板,其中具有所述开口的多个所述绝缘层中的每一个都被叠置,其间插入与所述配线不同的配线。
CN2009101379993A 2005-04-05 2006-03-14 具有配线基板的电子设备及用于这种电子设备的配线基板 Expired - Fee Related CN101567357B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2005108823 2005-04-05
JP2005-108823 2005-04-05
JP2005108823 2005-04-05

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN200680011442XA Division CN101156237B (zh) 2005-04-05 2006-03-14 具有配线基板的电子设备、其制造方法以及用于这种电子设备的配线基板

Publications (2)

Publication Number Publication Date
CN101567357A true CN101567357A (zh) 2009-10-28
CN101567357B CN101567357B (zh) 2011-05-11

Family

ID=37086676

Family Applications (2)

Application Number Title Priority Date Filing Date
CN200680011442XA Expired - Fee Related CN101156237B (zh) 2005-04-05 2006-03-14 具有配线基板的电子设备、其制造方法以及用于这种电子设备的配线基板
CN2009101379993A Expired - Fee Related CN101567357B (zh) 2005-04-05 2006-03-14 具有配线基板的电子设备及用于这种电子设备的配线基板

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN200680011442XA Expired - Fee Related CN101156237B (zh) 2005-04-05 2006-03-14 具有配线基板的电子设备、其制造方法以及用于这种电子设备的配线基板

Country Status (4)

Country Link
US (1) US20090020870A1 (zh)
JP (1) JPWO2006109383A1 (zh)
CN (2) CN101156237B (zh)
WO (1) WO2006109383A1 (zh)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9929080B2 (en) * 2004-11-15 2018-03-27 Intel Corporation Forming a stress compensation layer and structures formed thereby
DE112007003083B4 (de) * 2006-12-22 2019-05-09 Tdk Corp. Mikrofonbaugruppe mit Unterfüllmittel mit niedrigem Wärmeausdehnungskoeffizienten
TWI353661B (en) * 2007-04-09 2011-12-01 Unimicron Technology Corp Circuit board structure capable of embedding semic
US7800916B2 (en) * 2007-04-09 2010-09-21 Endicott Interconnect Technologies, Inc. Circuitized substrate with internal stacked semiconductor chips, method of making same, electrical assembly utilizing same and information handling system utilizing same
JP2009177122A (ja) * 2007-12-25 2009-08-06 Hitachi Chem Co Ltd 薄型接合体の製造方法及び薄型接合体
JP2009170753A (ja) * 2008-01-18 2009-07-30 Panasonic Corp 多層プリント配線板とこれを用いた実装体
JP5279355B2 (ja) * 2008-06-11 2013-09-04 キヤノン株式会社 液体吐出装置の製造方法
US8222739B2 (en) * 2009-12-19 2012-07-17 International Business Machines Corporation System to improve coreless package connections
JP2011222553A (ja) * 2010-04-02 2011-11-04 Denso Corp 半導体チップ内蔵配線基板及びその製造方法
KR101665302B1 (ko) 2010-05-20 2016-10-24 에베 그룹 에. 탈너 게엠베하 칩 스택 제조 방법, 및 본 방법을 실시하기 위한 캐리어
RU2563971C2 (ru) 2010-10-14 2015-09-27 Стора Энсо Ойй Способ и устройство для присоединения чипа к печатной проводящей поверхности
US10396611B2 (en) 2013-04-15 2019-08-27 Mitsubishi Electric Corporation Rotor of rotary machine
JP5842859B2 (ja) * 2013-04-15 2016-01-13 株式会社村田製作所 多層配線基板およびこれを備えるモジュール
GB2524791B (en) 2014-04-02 2018-10-03 At & S Austria Tech & Systemtechnik Ag Placement of component in circuit board intermediate product by flowable adhesive layer on carrier substrate
US10468363B2 (en) 2015-08-10 2019-11-05 X-Celeprint Limited Chiplets with connection posts
US10103069B2 (en) * 2016-04-01 2018-10-16 X-Celeprint Limited Pressure-activated electrical interconnection by micro-transfer printing
EP3474327A4 (en) * 2016-06-20 2019-06-19 Sony Corporation SEMICONDUCTOR CHIP HOUSING
US11064609B2 (en) 2016-08-04 2021-07-13 X Display Company Technology Limited Printable 3D electronic structure
WO2019167194A1 (ja) * 2018-02-28 2019-09-06 オリンパス株式会社 超音波プローブ及び超音波処置具
US11469152B2 (en) 2019-10-14 2022-10-11 Mediatek Inc. Semiconductor chip package and fabrication method thereof
KR20210146038A (ko) * 2020-05-26 2021-12-03 엘지이노텍 주식회사 패키지기판 및 이의 제조 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08236586A (ja) * 1994-12-29 1996-09-13 Nitto Denko Corp 半導体装置及びその製造方法
JP2000077457A (ja) * 1998-08-31 2000-03-14 Hitachi Chem Co Ltd 半導体装置、半導体実装用基板及び半導体装置の製造方法
KR20010090354A (ko) * 1999-03-26 2001-10-18 가나이 쓰토무 반도체 모듈 및 그 실장 방법
JP2000309105A (ja) * 1999-04-27 2000-11-07 Canon Inc 液体収納容器、液体供給システムおよび前記液体収納容器の製造方法
JP3451373B2 (ja) * 1999-11-24 2003-09-29 オムロン株式会社 電磁波読み取り可能なデータキャリアの製造方法
US7034386B2 (en) * 2001-03-26 2006-04-25 Nec Corporation Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same
JP3966786B2 (ja) * 2001-09-27 2007-08-29 大日本印刷株式会社 半導体装置の製造方法
JP2004228162A (ja) * 2003-01-20 2004-08-12 Denso Corp 電子制御装置
WO2005034231A1 (ja) * 2003-10-06 2005-04-14 Nec Corporation 電子デバイスおよびその製造方法

Also Published As

Publication number Publication date
US20090020870A1 (en) 2009-01-22
CN101567357B (zh) 2011-05-11
WO2006109383A1 (ja) 2006-10-19
CN101156237A (zh) 2008-04-02
JPWO2006109383A1 (ja) 2008-10-09
CN101156237B (zh) 2011-01-19

Similar Documents

Publication Publication Date Title
CN101567357B (zh) 具有配线基板的电子设备及用于这种电子设备的配线基板
JP5089880B2 (ja) 配線基板内蔵用キャパシタ、キャパシタ内蔵配線基板及びその製造方法
US10177130B2 (en) Semiconductor assembly having anti-warping controller and vertical connecting element in stiffener
US7376318B2 (en) Circuit board and its manufacturing method
CN102037797B (zh) 印刷电路板及其制造方法
EP1763295A2 (en) Electronic component embedded board and its manufacturing method
US20080303153A1 (en) Semiconductor device, manufacturing method thereof, and semiconductor device product
US20110314667A1 (en) Method of manufacturing printed circuit board including electronic component embedded therein
JP2009064966A (ja) 多層配線基板及びその製造方法ならびに半導体装置
US10062663B2 (en) Semiconductor assembly with built-in stiffener and integrated dual routing circuitries and method of making the same
CN103178043A (zh) 布线基板及其制造方法
JP2004343030A (ja) 配線回路基板とその製造方法とその配線回路基板を備えた回路モジュール
KR100257926B1 (ko) 회로기판형성용다층필름 및 이를 사용한 다층회로기판 및 반도체장치용패키지
JP4864810B2 (ja) チップ内蔵基板の製造方法
JP2005167244A (ja) 集積回路積層に用いられる薄いパッケージ
US20100059876A1 (en) Electronic component package and method of manufacturing the same
CN103794515A (zh) 芯片封装基板和结构及其制作方法
US8334590B1 (en) Semiconductor device having insulating and interconnection layers
WO2001008222A1 (en) Semiconductor device, method of manufacture thereof, circuit board, and electronic device
CN101241901A (zh) 内埋式芯片封装结构及其制作方法
JPH07106509A (ja) 多層構造半導体装置
JP2000261152A (ja) プリント配線組立体
TWI624924B (zh) 具有嵌埋式元件及加強層之線路板及其製法
KR101022922B1 (ko) 범프를 구비한 인쇄회로기판 및 그 제조방법
KR20110001167A (ko) 임베디드 반도체 패키지 및 이의 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: LENOVO INNOVATION CO., LTD. (HONGKONG)

Free format text: FORMER OWNER: NEC CORP.

Effective date: 20141128

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; TO: HONG KONG, CHINA

TR01 Transfer of patent right

Effective date of registration: 20141128

Address after: Hongkong, China

Patentee after: LENOVO INNOVATIONS Co.,Ltd.(HONG KONG)

Address before: Tokyo, Japan

Patentee before: NEC Corp.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110511

Termination date: 20180314

CF01 Termination of patent right due to non-payment of annual fee