CN101553918B - 半导体结构以及组装方法 - Google Patents
半导体结构以及组装方法 Download PDFInfo
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- CN101553918B CN101553918B CN2006800397429A CN200680039742A CN101553918B CN 101553918 B CN101553918 B CN 101553918B CN 2006800397429 A CN2006800397429 A CN 2006800397429A CN 200680039742 A CN200680039742 A CN 200680039742A CN 101553918 B CN101553918 B CN 101553918B
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Abstract
一种半导体结构(100,900)包括具有表面(111)的衬底(110),还包括位于所述衬底表面上的一个或多个半导体芯片(120)。所述半导体结构进一步包括位于所述衬底表面上的电隔离体结构(340),其中所述电隔离体结构包括一条或多条电引线(341,342)以及被模压到所述电引线的有机基质元件(343)。所述半导体结构还包括将所述电隔离体结构和所述衬底表面耦接在一起的焊料元件(350)。
Description
技术领域
本发明一般涉及半导体器件,尤其涉及半导体器件封装。
背景技术
半导体管芯或芯片被包封在半导体器件封装中,以防止外部应力和环境损坏芯片并且提供用于承载到达和来自芯片的电信号的系统。存在许多不同类型的半导体封装,包括双列直插式封装、针栅阵列(PGA)封装、卷带自动结合(TAB)封装、多芯片模块(MCM)和功率封装。一种类型的功率封装是射频(RF)功率封装,其典型地在半导体芯片中的半导体器件消耗大于近似十瓦特的功率并且以大于近似一百兆赫(MHz)的频率工作时使用。RF功率封装经常包括内部气隙,为了更低的功率损耗和更好的RF性能。
当前的高功率RF半导体封装使用陶瓷绝缘体,其因它们的形状而经常称作“窗框”或“框架”,并且被铜焊或焊接到金属源衬底。但是,陶瓷绝缘体昂贵并且具有较差的机械公差。
另一种高功率RF半导体封装在2003年1月28日颁发给Bregante等人的美国专利No.6,511,866中描述,并且使用聚合物绝缘体或基于聚合物的框架。但是,该封装因框架与金属源衬底的基于镍和/或金的表面之间的固有弱聚合物/金属界面而具有潜在的可靠性问题。较差的密封是因为难以在框架与金属源衬底之间产生机械坚固且一致的环氧树脂(epoxy)接合。另外,考虑到正强加于工业上的有害物质指令(RoHS)要求的新的无铅和其他限制,该封装也具有在该聚合物/金属界面处机械失效的高度可能。此外,该封装在最终安装条件下也具有可能较差的机械完整性。
再一种高功率RF半导体封装在2005年3月15日颁发给 Zimmerman的美国专利No.6,867,367中描述。但是,该封装将专卖的高温聚合物材料用于框架,其在将半导体芯片附接到衬底之前被模压(mold)到金属源衬底。在芯片附接步骤之前完成封装因将半导体芯片附接或安装到金属源衬底所需的高温而引起框架与金属源衬底之间的机械可靠性问题。在芯片附接步骤之前完成封装也可能限制芯片连接选择。例如,如果聚合物在400摄氏度熔化或降解,则不能使用在高于400摄氏度时发生的金硅芯片附接工艺。
因此,存在对于比基于陶瓷的封装便宜并且具有相对于当前基于聚合物的气腔封装的提高可靠性的新的高功率RF半导体封装的需求。
附图说明
将从下面结合附图而进行的详细描述的阅读中更好地理解本发明,在附图中:
图1示出根据本发明的实施方案的半导体结构的顶视图;
图2示出根据本发明的实施方案沿着图1中的剖面线2-2观看的图1中半导体结构的剖视图;
图3示出根据本发明的实施方案在组装过程的较晚步骤期间图1中半导体结构的分解顶视图;
图4示出根据本发明的实施方案沿着图3中的剖面线4-4观看的图3中半导体结构的剖视图;
图5示出根据本发明的实施方案在组装过程的较晚步骤期间图3中半导体结构的顶视图;
图6示出根据本发明的实施方案沿着图5中的剖面线6-6观看的图5中半导体结构的剖视图;
图7示出根据本发明的实施方案在组装过程的较晚步骤期间图5中半导体结构的顶视图;
图8示出根据本发明的实施方案沿着图7中的剖面线8-8观看的图7中半导体结构的剖视图;
图9示出根据本发明的实施方案的半导体封装系统的一部分的侧视 图;
图10和11示出根据本发明其他实施方案的电隔离体结构的一部分的剖视图;以及
图12示出根据本发明的实施方案的组装半导体结构或半导体封装系统的方法的流程图。
为了说明的简单和清晰,附图示出一般的构造方式,并且可省略众所周知的特征和技术的描述和细节以避免不必要地混淆本发明。另外,附图中的元件不一定按比例绘制。例如,附图中一些元件的尺寸可能相对于其他元件被夸大以帮助促进对本发明实施方案的理解。不同附图中的相同参考数字表示相同的元件。
说明书和权利要求书中的术语“第一”、“第二”、“第三”、“第四”等,如果存在的话,是用来区分类似的元件,而不一定用于描述特定的顺序或时间次序。应当理解,如此使用的术语在适当情况下是可互换的,使得这里描述的本发明的实施方案例如能够以除在这里示出或另外描述的那些之外的顺序操作。此外,术语“包括”、“包含”、“具有”及其任何变体意在覆盖非排他的包括,使得包括一系列元素的过程、方法、物品或装置并不一定局限于那些元素,而是可以包括没有明白地列出或者对于这种过程、方法、物品或装置固有的其他元素。
说明书和权利要求书中的术语“左”、“右”、“前”、“后”、“顶部”、“底部”、“上方”、“下方”等,如果存在的话,是用于描述目的而不一定用于描述永久的相对位置。应当理解,如此使用的术语在适当情况下是可互换的,使得这里描述的本发明的实施方案例如能够以除在这里示出或另外描述的那些之外的取向操作。这里使用的术语“耦接”被定义为以电、机械、化学或其他方式直接或间接连接,除非另外定义。
具体实施方式
本发明的各种实施方案包括射频组件的半导体结构或半导体封装系统,其中金属元件或层被模压或嵌入到塑料中以形成电隔离体结构的基底,以便于电隔离体结构到衬底或凸缘的焊料附接。输入/输出引线也 被模压或嵌入到电隔离体结构中,这可以减少零件成本,提高尺寸公差,并且允许多引线结构。在一些实施方案中,引线和/或金属元件具有锁模特征以增强塑料到金属的粘着。金属元件通过允许使用焊料代替环氧树脂以形成电隔离体结构与衬底之间的接合,而提供机械上更坚固的结构。金属元件也允许将较便宜的塑料材料用于电隔离体结构的塑料部分。
本发明的其他实施方案可以包括具有表面区域朝向衬底的表面的金属元件,并且也可以包括具有表面区域也朝向衬底的表面的电隔离体结构的塑料材料部分。在这些实施方案中,金属元件的表面面积小于塑料材料部分的表面面积。如下面所说明,表面面积的该差异可以减小焊料跑出或焊料进入的问题,因为焊料将粘着到金属元件,但是不会粘着到电隔离体结构的暴露塑料材料部分。本发明的一些实施方案包括这些特征的组合或者这些特征的一个或多个与这里描述的其他特征的组合。
另外,本发明的一些实施方案可以包括半导体结构或半导体封装系统的组装过程,其中:(1)半导体芯片被附接或耦接到衬底;(2)具有金属元件和引线的电隔离体结构被焊料附接到衬底;(3)半导体芯片被引线结合到引线;以及(4)盖子被结合到电隔离体结构的塑料材料部分以产生气密外壳或至少粗漏外壳(gross leak enclosure)。该组装过程允许半导体芯片在高温下在电隔离体结构中不存在温度敏感的塑料材料的情况下被附接到衬底,从而允许使用许多不同的较低成本的塑料材料并且也提高可靠性。
现在参考附图,图1示出半导体封装系统或半导体结构100的顶视图,以及图2示出沿着图1中的剖面线2-2观看的半导体结构100的剖视图。半导体结构100包括具有表面111以及与表面111相对的表面112的衬底110。在一些实施方案中,衬底110被称作凸缘(flange)。在相同或不同实施方案中,衬底110用作吸热器或散热器。在这些实施方案的每一种中,衬底110可以包括热和/或电传导材料,例如铜(Cu)、基于铜的合成物、基于铜的叠层体、碳化铝硅(AlSiC)、铜石墨和/或金刚石等。基于铜的合成物的实例包括铜钨(CuW)和铜钼 (CuMo),并且基于铜的叠层体的实例有铜钼铜(CuMoCu)。
衬底110的表面111可以包括在衬底110的导电材料之上的层113。层113可以是金属层或可焊金属层。当层113是可焊金属层时,层113提供衬底110的可焊表面。作为实例,层113可以是包含镍和金的可焊表面。在该特定实施方案中,层113可以包括一层金,以及位于该层金与衬底110的导电材料之间的一层镍。在另一种实施方案中,层113可以包括镍钴(NiCo)和金(Au)。作为实例,层113可以被电镀到衬底110上并且也可以位于衬底110的其他表面上,包括表面112。
衬底110也可以包括可选的安装孔或凹口114。图1描绘两个凹口,但是凹口的具体数量可以变化。凹口114可以位于衬底110的对端115和116。如随后所说明,凹口114可以用来将半导体结构100固定到另一个衬底,例如电路板。
半导体结构100也包括至少一个半导体芯片120。图1描绘四个半导体芯片,但是半导体芯片的具体数量可以变化。半导体芯片120位于衬底110的表面111上。在一种实施方案中,半导体芯片120包含适合于射频或其他高频器件的一种或多种材料。在不同或相同实施方案中,半导体芯片120包含适合于高功率器件的一种或多种材料。作为实例,半导体芯片120可以包括砷化镓(GaAs)、硅(Si)或氮化镓(GaN)等。在大多数实施方案中,半导体芯片120也可被称作半导体管芯。
半导体芯片120的每一个包括至少一个半导体器件121。因此,半导体器件121也位于衬底110的表面111上。在半导体芯片120包含硅的实施方案中,半导体器件121可以是横向扩散金属氧化物半导体(LDMOS)器件。半导体器件121中至少一个是有源器件(也就是晶体管),且不仅一个或多个无源器件(也就是电阻器、电容器、电感器等),但是半导体器件121的其他可以是匹配器件,例如集成无源器件(IPD)和金属氧化物半导体电容器(MOSCAP)。在不同实施方案中,半导体芯片120的一个或多个由作为匹配器件的一个或多个非半导体组件代替。这些非半导体组件的实例包括IPD和低温共烧陶瓷(LTCC)匹配砖。
半导体芯片120的每一个可以具有包含金(Au)、银(Ag)、镍钴金(NiCoAu)或镍金(NiAu)等的可焊表面122和223。表面122和223全部都可是可焊的,或者表面122和223的仅一部分可以是可焊的。在焊料互连不用于半导体结构100的另一种实施方案中,表面122都不可焊。
半导体结构100也包括位于半导体芯片120与衬底110的表面111之间并且将它们耦接在一起的粘合剂230。在一些实施方案中,粘合剂230可以是导电的。在这些实施方案中,粘合剂230可以将半导体芯片120电耦接到衬底110,其可以用作半导体芯片120中的半导体器件121的电引线。因此,在这些实施方案中,当衬底110是半导体器件121的源电极的电引线时,衬底110可以被称作源衬底或源凸缘。同样在这些实施方案中,粘合剂230包括几个离散的或个体的部分。
在一种实施方案中,粘合剂230可以是任何适当的芯片或管芯附接材料,例如基于铅或不基于铅的焊料。在该实施方案中,粘合剂230可以被称作焊料元件。作为实例,适当的不基于铅的焊料包括金锡(AuSn)或金硅(AuSi)等。在该实施方案中,粘合剂230将表面111处层113的一部分与表面223焊接在一起。当半导体芯片120包含硅时,粘合剂230可以包含热膨胀系数(CTE)低的材料例如金硅,以便更接近地匹配半导体芯片120的CTE。在其他实施方案中,粘合剂230可以是导电或不导电的环氧树脂或者热固或热塑聚合物。
粘合剂230可以使用包层、电镀、丝网印刷或焊球技术形成在半导体芯片120的可焊表面223上或者衬底110的表面111的层113上。粘合剂230也可以是操作(perform)。如下面所说明,粘合剂230也可以具有比在半导体结构100的制造或组装过程的较晚阶段期间所使用的其他粘合剂或焊料的熔化和回流温度高的熔化温度和回流温度。
图3示出组装过程的较晚步骤期间半导体结构100的分解顶视图,并且图4示出沿着图3中的剖面线4-4观看的半导体结构100的剖视图。半导体结构100另外包括位于衬底110的表面111上的电隔离体结构340。如图3和4中所说明,电隔离体结构340包括两个电引线341 和342。但是,通常,电隔离体结构340可以包括多于或少于两个电引线。电引线341和342用来传导到达和来自半导体芯片120中的半导体器件121以及进入和离开半导体结构100的电信号。在一种实施方案中,电引线341和342可以分别是半导体器件121的栅电极和漏电极的栅极引线和漏极引线。在该实施方案中,衬底110可以用作半导体器件121的源电极的源极引线。
作为实例,电引线341和342可以包括导电材料,包括例如铜、铜合金以及先前对于衬底110识别的其他导电材料。另外,电引线341和342可以包括具有镍的铁基合金,例如合金42,其组成包括42%的镍。电引线341和342也可以包括具有镍和钴的铁基合金,如由CRSHoldings公司,一家Delaware的公司以商标 所销售的。
电引线341和342也可以包括可焊表面,使得电引线341和342适合于半导体结构100内部的引线结合或其他互连方案以及使得电引线341和342适合于半导体结构100外部的引线结合或焊接。作为实例,电引线341和342的可焊表面可以包括对于衬底110的层113(图1和2)以及半导体芯片120的可焊表面122和223识别的相同可焊材料。
电隔离体结构340也包括模压到电引线341和342的有机基质(organic-based)元件343。在一些实施方案中,有机基质元件343可以具有窗框的形状,如图3中所示。在这些实施方案中,有机基质元件343可以被称作框架,并且电隔离体结构340可以被称作框架结构。有机基质元件包含电绝缘材料,例如聚合物、热塑和/或热固材料。因此,在一些实施方案中,有机基质元件343也可以被称作塑料绝缘体框架。
电隔离体结构340还包括金属元件444,其中有机基质元件343位于金属元件444与电引线341和342之间。金属元件444可以位于电隔离体结构340的底部或基底。在该实施方案中,金属元件444也可以被称作基底金属元件。有机基质元件343将金属元件444与电引线341和342彼此电隔离或绝缘。金属元件444可以具有与有机基质元件343相同的窗框形状和相同的基底面(footprint)。金属元件444提供电隔离 体结构340的可焊表面,使得电隔离体结构340可以被焊料附接到衬底110,如下面所说明。
金属元件444可以包括对于电引线341和342识别的相同材料,像电引线341和342一样,可以具有可焊表面。如果金属元件444具有单个可焊表面,则可焊表面面向衬底110的表面111。在一种实施方案中,金属元件444与电引线341和342包括相同或基本上类似的材料,并且由相同的引线框架或由两个独立的引线框架制成。金属元件444也可以是在有机基质元件343的模压过程之前置于模压板之间的个体组件。
有机基质元件343被模压到金属元件444,其可以包括模锁445以改善有机基质元件343到金属元件444的粘着。模锁445可以在形状、尺寸和技术方面变化。例如,代替图4中所示的模锁或除了图4中所示的模锁之外,模锁445可以包括金属元件444中的一个或多个通孔。模锁445也可以包括环绕技术。虽然图4中没有示出,但电引线341和342也可以包括相同或不同的锁模技术,以改善有机基质元件343到电引线341和342的粘着。
有机基质元件343可以通过使用注入、转印或其他模压过程来形成以将有机基质元件343同时模压到金属元件444以及电引线341和342。位于引线341和342上面的有机基质元件343的部分是可选的,并且在半导体结构100的一些实施方案中可以消除。
半导体结构100还包括位于衬底110的表面111上的焊料元件350。焊料元件350将电隔离体结构340与衬底110耦接在一起。更具体地说,焊料元件350将金属元件444的可焊表面与衬底110的表面111的层113的一部分焊接在一起。因此,焊料元件350位于金属元件444与衬底110之间。作为实例,焊料元件350可以包括对于粘合剂230(图2)识别的相同焊料材料,以及本领域中已知的其他焊料材料,并且可以类似的方式形成。焊料元件350可以具有比粘合剂230低的熔化温度和回流温度。
如图3和4中所示,焊料元件350可以具有与有机基质元件343的 窗框形状类似的形状。在回流之前,焊料元件350可以包含单件(piece),或者它可以包含分立的两件或多件。如果焊料元件350起源为分立的两件或多件,则回流步骤优选地组合所述件使得焊料元件350变成单个整体元件。焊料元件350可以是操作,或者在不同实施方案中,焊料元件350可以在将电隔离体结构340模压或附接到衬底110之前沉积到金属元件444上面。在该不同实施方案中,半导体结构100将不具有操作,这可能增强半导体结构100的可制造性。
在未说明的实施方案中,焊料元件350可以在将电隔离体结构340附接到衬底110之前沉积到金属元件444上面。在该实施方案中,作为实例,与层113类似的层可以在金属元件444上面形成或可以用来代替金属元件444,并且可以包括金(Au)和锡(Sn)的层。
图5示出在组装过程的甚至更晚步骤期间半导体结构100的顶视图,并且图6示出沿着图5中的剖面线6-6观看的半导体结构100的剖视图。如图5和6中所说明,电隔离体结构340被焊接到衬底110。半导体结构100另外包括将半导体芯片120中的半导体器件121与电引线341和342耦接在一起的引线结合560。作为实例,引线结合560包括导电材料,如在本领域中已知的,例如金、铝硅、铝锰或铜等。在其他实施方案中,引线结合560由其他电互连结构例如焊球、倒装芯片互连和卷带自动结合(TAB)等代替。
图7示出在组装过程的随后步骤期间半导体结构100的顶视图,并且图8示出沿着图7中的剖面线8-8观看的半导体结构100的剖视图。半导体结构100包括位于衬底110、半导体芯片120和电隔离体结构340上的盖子770。盖子770保护半导体芯片120和引线结合560免受物理和环境损坏。盖子770可以附接到有机基质元件343和/或电引线341和342。作为实例,盖子770可以包含液晶聚合物(LCP)、陶瓷或其他非导电材料。盖子770可以具有许多不同构造,包括凹口以容纳更高的引线结合。
衬底110、电隔离结构340的有机基质元件343、电隔离结构340的电引线341和342、电隔离结构340的金属元件444、焊料元件350 以及盖子770形成具有气隙880的至少粗漏密封封装,半导体芯片120和引线结合560位于所述气隙880中。在不同实施方案中,半导体结构100是气密密封的封装。
在一种实施方案中,半导体芯片120中的半导体器件121是高功率射频器件,所以封装是高功率射频封装。在相同或不同实施方案中,气隙880可以包含其他材料,例如氮或另一种惰性气体。
图9示出半导体结构或半导体封装系统900的一部分的侧视图。半导体封装系统900包括可以与图1-8中描述的高功率射频封装类似的封装910。半导体封装系统900也包括电路板920。作为实例,电路板920可以是底板、吸热器或印刷电路板(PC板)。半导体封装系统900还包括可以用来将封装910耦接到电路板920的一个或多个紧固件930。例如,紧固件930可以是安装在衬底110的凹口114(图1)中的螺丝。
半导体封装系统900也包括粘合剂940。在一种实施方案中,粘合剂940可以是将引线341和342(图3和4)电耦接到电路板920的焊料。作为实例,粘合剂940可以是包括锡银铜、锡银、锡锑、锡铋、锡铜、金锡或金锗等的无铅焊料。作为另一个实例,粘合剂940可以是基于铅的焊料例如铅锡银。在一些实施方案中,粘合剂940具有比焊料元件350(图6)和粘合剂230(图2)低的熔化温度和回流温度。虽然图9中没有说明示出,但粘合剂940或另一种导电粘合剂也可以位于电路板920与封装910的衬底110(图1)之间,从而将衬底110电耦接到电路板920。在该实施方案中,该粘合剂优选地也具有比焊料元件350(图6)低的熔化温度和回流温度。
图10示出电隔离体结构1040的一部分的剖视图,其是电隔离体结构340(图3和4)的不同实施方案。电隔离体结构1040包括金属元件1044,代替电隔离体结构340中的金属元件444(图4)。金属元件1044与金属元件444类似,除了金属元件1044具有比金属元件444更小的基底面。因此,面向衬底110(图4)的金属元件1044表面具有比也面向衬底110的有机基质元件343表面的表面面积小的表面面积。(在图4中,金属元件444具有与有机基质元件343基本上相同的内围和外围, 使得面向衬底110的金属元件444表面具有与也面向衬底110的有机基质元件343表面的表面面积基本上相同的表面面积。)在该实施方案中,有机基质元件343的一部分1041没有被金属元件1044覆盖,并且用作焊堤(solder dam)以禁止焊料元件350(图3和4)朝向半导体芯片120(图4)的焊料跑出或进入。
图10中的金属元件1044与图4中的金属元件444之间的另一个差异在于,金属元件1044在金属元件1044的两个不同表面上具有模锁1045。特别地,如图10中所示,金属元件1044在金属元件1044的两个相邻表面上具有模锁1045。金属元件1044的侧表面上的另外模锁可以改善有机基质元件343到金属元件1044的粘着。
图11示出电隔离体结构1140的一部分的剖视图,其是电隔离体结构340(图3和4)的另一种实施方案。电隔离体结构1140包括金属元件1144,代替电隔离体结构340中的金属元件444(图4)。金属元件1144与金属元件444类似,除了金属元件1044具有比金属元件444更小的基底面。(金属元件1144也具有比图10中的金属元件1044更小的基底面。)在该实施方案中,有机基质元件343的一部分1141没有被金属元件1144覆盖,并且用作焊堤以禁止焊料元件350(图3和4)朝向半导体芯片120(图4)的焊料跑出或进入。此外,有机基质元件343的一部分1142也没有被金属元件1144覆盖,并且用作另一个焊堤以禁止焊料元件350(图3和4)到封装外部的焊料跑出或“出去”。同样在该实施方案中,金属元件1144在封装的外表面没有暴露,除了在引线框架修整位置。
图11中的金属元件1144与图4中的金属元件444之间的另一个差异在于,金属元件1144在金属元件1144的三个不同表面上具有模锁1145。特别地,如图11中所示,金属元件1144在金属元件1144的三个相邻表面上具有模锁1145。金属元件1144的侧表面上的另外模锁可以改善有机基质元件343到金属元件1144的粘着。
图12示出组装半导体结构的方法的流程图1200。作为实例,流程图1200的半导体结构可以与图1-8的半导体结构100、图9的半导体封 装系统900以及所有它们的各种实施方案类似。
流程图1200包括提供具有表面的衬底的步骤1201。作为实例,步骤1201的衬底可以与图1和2中的衬底110类似,并且步骤1201中衬底的表面可以与图1和2中衬底110的表面111类似。
流程图1200也包括将半导体芯片安装到衬底表面或其上的步骤1202。作为实例,步骤1202的半导体芯片可以与图1和2中的半导体芯片120类似,并且可以包括一个或多个半导体器件。与用来将半导体芯片120安装到衬底110的粘合剂类似,焊料元件或其他粘合剂可以用于安装步骤。步骤1202也可以被称作管芯附接步骤。在一种实施方案中,步骤1202在大约370摄氏度的焊料或环氧树脂熔化温度之上发生。在相同或不同实施方案中,步骤1202在大约410摄氏度的焊料或环氧树脂回流温度发生。
在半导体结构中使用一个或多个匹配元件的实施方案中,步骤1202可以包括将匹配元件安装到衬底表面或其上。在该实施方案中,匹配元件可以在半导体芯片之前、与其同时或者在其之后安装。
流程图1200使用将电隔离体结构焊接在衬底表面上的步骤1203来继续。作为实例,步骤1203的电隔离体结构可以与图3和4中的电隔离体结构340和/或它的各种实施方案类似,并且焊料元件可以用来将电隔离体结构安装到衬底表面。在一种实施方案中,步骤1203在大约280摄氏度的焊料熔化温度之上发生。在相同或不同实施方案中,步骤1203在大约320摄氏度的焊料回流温度发生。
在优选实施方案中,步骤1203在比步骤1202低的温度发生,并且步骤1203在步骤1202之后发生。在该实施方案中,步骤1202的较高温度不会熔化步骤1203中用于电隔离体结构的焊料或者更改电隔离体结构相对于衬底和半导体芯片的位置,其可能有害地影响半导体结构的可靠性和电性能。同样在优选实施方案中,步骤1202和1203串行发生,而不是并行发生,为了电隔离体结构和半导体芯片在衬底表面上的更精确相对定位,这引起半导体结构的改进的电性能。
在优选实施方案中,在步骤1203之后,流程图1200使用将半导体 芯片电耦接到电隔离体结构的步骤1204来继续。作为实例,参考图5和6描述的引线结合560以及其他互连结构可以在步骤1204期间使用,以将半导体芯片的半导体器件电耦接到电隔离体结构的电引线。
流程图1200也包括将盖子附接到电隔离体结构的步骤1205。作为实例,步骤1205的盖子可以与图7和8中的盖子770类似。在一种实施方案中,盖子将半导体芯片气密地或至少粗漏地密封在半导体结构内。在相同或不同实施方案中,步骤1205可以使用环氧树脂或其他粘合剂以将盖子附接到电隔离体结构,或者步骤1205可以使用声波、超声波、热或其他焊接技术来实现这一点。在一种备选实施方案中,步骤1205可以将盖子附接到衬底表面。在另一种备选实施方案中,步骤1205可以与步骤1203同时执行,或者步骤1205可以在步骤1203之前执行。
流程图1200另外包括将半导体结构附接到电路板的步骤1206。作为实例,步骤1206的电路板可以与图9的电路板920类似。如图12中所示,步骤1206可以在步骤1201-1205之后发生。
在一种实施方案中,紧固件例如图9中的紧固件930可以用来将半导体结构附接到电路板。在相同或不同实施方案中,粘合剂例如图9中的粘合剂940可以用来将半导体结构的一个或多个电引线附接到电路板。当在步骤1206期间使用粘合剂时,步骤1206可以在大约215-220摄氏度的焊料熔化温度之上发生。在相同或不同实施方案中,步骤1206可以在大约240-260摄氏度的焊料回流温度发生。在优选实施方案中,步骤1206在比步骤1202-1205低的温度发生,并且步骤1206在步骤1201-1205之后发生,使得步骤1202-1205的较高温度不会熔化用来将半导体结构附接到电路板的焊料或其他粘合剂。
考虑到上面全部,描述了一种新的高功率射频或其他高频半导体结构和半导体封装系统,其更便宜且具有改进的可靠性。机械上和热学上更坚固的结构和封装系统提供相对于其他封装设计的较低成本和改进的可靠性的优点。
虽然已经参考具体实施方案描述了本发明,但是本领域技术人员应 当理解,可以进行各种改变而不背离本发明的精神或范围。这些改变的各种实例已经在前述描述中给出。因此,本发明实施方案的公开意在说明本发明的范围而不意在限制。本发明的范围意在仅限于随附权利要求所要求的范围。例如,本领域技术人员将容易明白,图3和4中电隔离体结构340的构造、几何、形状和尺寸以及图4、10和11中的模锁445、1045和1145分别可以变化,并且对这些实施方案中的某些方案的前述讨论不一定代表所有可能实施方案的完整描述。类似地,半导体结构100和半导体封装系统900的各种元件的材料组成可以从上述细节中变化。
任何特定权利要求中所要求保护的所有要素对于该特定权利要求中所要求保护的发明是本质的。因此,一个或多个所要求保护的要素的替换构成重建而不是修正。另外,已经关于具体实施方案描述了益处、其他优点和问题的解决方法。但是,可能引起任何益处、优点或解决方法发生或变得更加显著的益处、优点、问题的解决方法以及任何一个或多个要素不应解释为任何或全部权利要求的关键、必需或本质特征或要素。
而且,这里公开的实施方案和限制在贡献原则下并不贡献于公众,如果实施方案和/或限制:(1)没有在权利要求书中被明确地要求保护;以及(2)或者在等同原则下是权利要求书中显式要素和/或限制的潜在等同物。
Claims (10)
1.一种半导体结构,包括:
具有第一表面的衬底;
位于所述衬底的第一表面上的半导体芯片;
位于所述衬底的第一表面上的电隔离体结构,其中所述电隔离体结构包括电引线和被模压到所述电引线的有机基质元件;以及
将所述电隔离体结构与所述衬底的第一表面耦接在一起的焊料元件,
其中,所述电隔离体结构还包括金属元件;
所述有机基质元件被模压到所述金属元件;以及
所述有机基质元件位于所述金属元件与所述电引线之间。
2.根据权利要求1的半导体结构,其中:
所述衬底包含导电材料并且被电耦接到所述半导体芯片。
3.根据权利要求1的半导体结构,还包括:
位于所述半导体芯片与所述衬底的第一表面之间并且将所述半导体芯片与所述衬底的第一表面耦接在一起的粘合剂,
其中,所述焊料元件具有第一熔化温度;以及
所述粘合剂具有高于所述第一熔化温度的第二熔化温度。
4.一种半导体封装系统,包括:
包含导电材料且具有第一表面的凸缘;
至少一个半导体芯片,其具有位于所述凸缘的第一表面之上且电耦接到所述凸缘的第一表面的至少一个半导体器件,其中所述至少一个半导体器件是有源器件;
位于所述凸缘的第一表面上的至少一个匹配元件;
将所述至少一个半导体器件耦接到所述凸缘的第一表面的第一焊料 元件,其中所述第一焊料元件包含无铅焊料;
位于所述凸缘的第一表面上的框架结构,其中所述框架结构包括至少两条电引线、位于所述至少两条电引线下面的基底金属元件、以及位于所述至少两条电引线与所述基底金属元件之间并且被模压到所述至少两条电引线与所述基底金属元件的有机基质电绝缘元件;
将所述基底金属元件耦接到所述凸缘的第一表面的第二焊料元件;
将所述至少一个半导体器件和所述至少一个匹配元件电耦接到所述至少两条电引线的电互连结构;以及
位于所述凸缘和所述框架结构上面的盖子,以至少粗漏密封所述至少一个半导体芯片、所述至少一个匹配元件以及所述电互连结构于其中。
5.根据权利要求4的半导体封装系统,其中:
所述有机基质电绝缘元件面向所述凸缘的表面具有第一表面面积;以及
所述基底金属元件面向所述凸缘的表面具有小于所述第一表面面积的第二表面面积。
6.一种半导体结构,包括:
具有第一表面的衬底;
位于所述衬底的第一表面上的半导体芯片;
位于所述衬底的第一表面上的电隔离体结构,其中所述电隔离体结构包括电引线和有机基质元件;以及
将所述电隔离体结构与所述衬底的第一表面耦接在一起的焊料元件,
其中,所述有机基质元件包括塑料;以及
所述电隔离体结构还包括金属元件。
7.根据权利要求6的半导体结构,其中:
所述衬底包含导电材料并且被电耦接到所述半导体芯片。
8.根据权利要求6的半导体结构,其中:
所述有机基质元件位于所述金属元件和所述电引线之间。
9.根据权利要求6的半导体结构,其中:
所述金属元件包括模锁;以及
所述有机基质元件被模压到所述金属元件的模锁和所述电引线。
10.一种半导体结构,包括:
具有第一表面的衬底;
位于所述衬底的第一表面上的半导体芯片;
位于所述衬底的第一表面上的电隔离体结构,其中所述电隔离体结构包括电引线和有机基质元件;以及
将所述电隔离体结构与所述衬底的第一表面耦接在一起的焊料元件;
位于所述半导体芯片与所述衬底的第一表面之间并且将所述半导体芯片与所述衬底的第一表面耦接在一起的粘合剂,
其中,所述焊料元件具有第一熔化温度;
所述粘合剂具有高于所述第一熔化温度的第二熔化温度;
所述有机基质元件包括塑料;以及
所述电隔离体结构还包括金属元件。
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US11/257,784 US7446411B2 (en) | 2005-10-24 | 2005-10-24 | Semiconductor structure and method of assembly |
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TWI489602B (zh) | 2015-06-21 |
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US7446411B2 (en) | 2008-11-04 |
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US20070090515A1 (en) | 2007-04-26 |
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