TW200423304A - Twice semi-etching processing and packaging structure for single-layer lead frame of image sensor - Google Patents

Twice semi-etching processing and packaging structure for single-layer lead frame of image sensor Download PDF

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Publication number
TW200423304A
TW200423304A TW92109167A TW92109167A TW200423304A TW 200423304 A TW200423304 A TW 200423304A TW 92109167 A TW92109167 A TW 92109167A TW 92109167 A TW92109167 A TW 92109167A TW 200423304 A TW200423304 A TW 200423304A
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Taiwan
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lead frame
mold
chip
image sensor
top surface
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TW92109167A
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Chinese (zh)
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Hong-Ren Wang
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Hong-Ren Wang
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Priority to TW92109167A priority Critical patent/TW200423304A/en
Publication of TW200423304A publication Critical patent/TW200423304A/en

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Abstract

The present invention relates to a twice semi-etching processing and packaging structure for single-layer lead frame of image sensor. The structure of the image sensor includes: a sensing chip, a single-layer lead frame, and a glass cover; the lead frame is done with the upper and lower twice semi-etching processing to produce the 3D structure of the die pad and the leads. The precision can be achieved to the micrometer level of integrated circuit, so that the soldering for the signal contacts of sensing chip may have better precision matching, which can reach excellent reliability and quality for current high density and high pixels of image sensing chip packaging.

Description

200423304 五、發明說明(1) 【發明所屬之技術領域】 本發明係有關一種影像感測器之 刻製程與封裝結構,尤指一種利 二v、、泉采一次半蝕 作晶片座與弓丨腳立體結構之方式。下兩。人半蝕刻製程製 【先前技術】 請參閱第6圖至第9圖所示,其俜傳站^ ^ μ ^ (Image sensor)封表技術。如第6圖、第9圖所示, 統的導線架(Lead f ram)製作方法係為衝壓式或堆疊 。其中,衝壓式製法係先於平板狀導體基材蝕刻 且' (Etching)出晶片座(Die pad) 7 !與各引腳(Lead) 7 2之位置與形狀,再由底部衝壓晶片座7 1使其浮出於 引腳7 2平面。另一方面,衝壓式製法亦有直接衝壓導體 平板,直接衝出晶片座7 1與各引腳7 2之立體結構,唯 此兩種方式皆需經機械衝壓加工,不易達到細密之尺寸精 度’因此並不適合現代影像感測晶片普遍小面積大量引腳 之封裝。而且,衝壓過程通常不易控制引腳7 2之平整度 ’通常需配合引腳7 2導正程序,對於現今高密度、高晝 素之影像感測晶片封裝,著實力有未逮,不易達到良好品 質。 另一種堆i式製法如第7圖所示,係以兩道手續分別 製作上下兩層之導線架樣板8 1 、8 2 ,上層樣板8 1含 晶片座8 3與各引腳8 4 ,下層樣板8 2僅含各引腳8 5 ;上下樣板8 1 、8 2堆疊後,晶片座8 3底部相對於弓丨 腳8 5底面凹入,俾利塑膠封裝與電性隔離,其整體封骏200423304 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to the engraving process and packaging structure of an image sensor, especially a kind of wafer holder and bow that are used for semi-etching once and for all. Way of three-dimensional structure of feet. Next two. Human semi-etching process [Prior technology] Please refer to Fig. 6 to Fig. 9 for its image transmission technology ^ ^ μ ^ (Image sensor). As shown in FIG. 6 and FIG. 9, the manufacturing method of the conventional lead frame (lead f ram) is stamped or stacked. Among them, the stamping method is to etch the flat substrate substrate and die (Etching) the die pad 7! And the positions and shapes of the leads 7 2 before punching the wafer holder 7 1 from the bottom. Let it float out of the pin 7 2 plane. On the other hand, the stamping method also directly punches the conductor flat plate, and directly punches out the three-dimensional structure of the wafer holder 7 1 and each pin 7 2. However, both of these methods require mechanical punching, and it is not easy to achieve fine dimensional accuracy. Therefore, it is not suitable for the packaging of a large number of pins in a small area in modern image sensing chips. Moreover, it is usually difficult to control the flatness of the lead 72 during the stamping process. It is usually necessary to cooperate with the lead 7 2 alignment process. For today's high-density, high-day image sensor chip packages, the strength is not captured, and it is not easy to achieve good results. quality. As shown in Fig. 7, another stack i-type manufacturing method uses two procedures to prepare the lead frame templates 8 1 and 8 2 of the upper and lower layers, respectively. The upper template 8 1 includes a wafer holder 8 3 and each pin 8 4. The lower layer The sample plate 8 2 contains only pins 8 5; after the upper and lower sample plates 8 1 and 8 2 are stacked, the bottom of the wafer holder 8 3 is recessed relative to the bottom of the bow 8 5, and the plastic package is electrically isolated from the entire package.

II 第5頁 i 200423304 五、發明說明 過程如第 兩樣板8 量引腳8 精度之要 好之品質 是一難題 感測信號 【發明内 本發 影像感測 發明係以 架之立體 電路之微 更好的精 片封裝, 再者 分子等級 可以有更 疊式製法 對後續的 面,兩次 送導線架 升產量, 為達 (2)8圖、第 1、8 2 4、8 5 求,使此 ;再者, ,不易良 傳遞之虞 容】 明之主要 器之單層 兩次半蝕 結構係以 米等級, 度配合, 著實為上 ,本發明 ,同時避 好的控制 接觸電阻 悍線封裝 半姑刻過 至他處衝 著實可謂 前述目的 9圖所示。然而,堆叠方式牵涉到上下 之尺寸精度配合問題,對於小面積、大 之影像感測晶片封裝5細腻之引腳’南 一製程遭遇同樣之困難,而不易達到良 兩導線架樣板8 1 、8 2之接觸電阻亦 好控制至一均勻水準,而恐有影響微細 ,著實有改良之必要。 目白勺, 導線架 刻過程 兩次半 因而與 對於當 上之選 兩次半 免掉機 ,完全 問題, 過程亦 程可完 在於解決上 二次半蝕刻 ,克服上述 蝕刻製程製 感測晶片信 今高密度、 ,容易達到 I虫刻過程係 械衝壓過程 不需配合引 製造精度速 可達到更好 述的問題而 製程與封裝 之難題。由 作,精度可 號接點之焊 局晝素之影 良好信賴品 化學加工, ,因而引腳 腳導正程序 度一次達成 的信賴品質 台完成,免 以節省加工 提供一種 結構,本 於,導線 達到積體 接可以有 像感測晶 質。 精度可達 之平整度 ,亦為堆 〇 而且 , 。另一方 去中途運 時間,提 全於同一機 壓的成本,同時可 一新穎進步之技術。 ,本發明之影像感測器之單層導線架二II Page 5 i 200423304 5. The process of description of the invention is as the second model 8 The measuring pin 8 The accuracy is better. The quality is a difficult problem. Fine-chip packaging, and the molecular level can have a more stacked manufacturing method for subsequent surfaces, twice the lead frame to increase the output, to achieve (2) 8 figure, the first 1, 8 2 4, 8 5 to make this; Moreover, the unsuccessful transfer of the Rong] The single-layer semi-etched structure of the main device of the Ming Dynasty is meter-level, and the degree of cooperation is true. The present invention avoids the control of the contact resistance and the semi-engraved packaging of the wire. Going to the other end can be described as shown in Figure 9 above. However, the stacking method involves the problem of dimensional accuracy matching up and down. For the small area and large image sensing chip package, the 5 delicate pins' Nanyi process encountered the same difficulties, and it is not easy to achieve a good two-lead frame template 8 1, The contact resistance of 8 2 is also well controlled to a uniform level, and it may have a small impact, and it is really necessary to improve it. For now, the lead frame engraving process is two and a half times. Therefore, it is completely a problem for the above two times to waive the machine. The process can also be completed by resolving the second half etch and overcoming the above-mentioned etching process. High-density, easy to achieve I insect engraving process, mechanical stamping process does not need to cooperate with the manufacturing precision speed can achieve better description of the problem and process and packaging problems. Made by, the precision of the number of contacts can be welded, and the quality of the product is well-relied on chemical processing. Therefore, the lead quality of the lead pin alignment procedure is achieved once, so as to save processing and provide a structure. Reach the integrated body can have image sensing crystal quality. The accuracy can reach the flatness, which is also the heap. And,. The other party's transit time is improved by the cost of the same machine, and at the same time, it can be a new and improved technology. The single-layer lead frame of the image sensor of the present invention

第6頁 200423304 五、發明說明 次半#刻 含:一感 具有 曰曰 該感測晶 内側頂面 測晶片之 要製作程 第一 於平 各引腳之 利後續塑 第二 於平 底部與各 嵌與電性 第三 將第 再以射出 周圍形成 感測晶片 頂面黏貼 (3) 製程 測晶 片座 片係 ,俾 上方 序如 步驟 板狀 位置 膠預 步驟 板狀 引腳 隔離 步驟 、 方式 凸牆 與各 玻璃 與封裝結構,其中,該影像感測器之結構包 片,一單層導線架與一玻璃蓋板;該導線架 與若干引腳,各引腳内側環繞晶片座周緣; 黏貼於晶片座之頂面’並以金線連接各引腳 利電信號之傳遞;而該玻璃蓋板係覆蓋於感 ,以上三者係以塑膠材料封裝為一體,其主 下: 導體基材之頂面以半蝕刻方式蝕出晶片座與 與形狀,並於適當位置银出若干貫穿孔,俾 模之鑲嵌固定; 導體基材之底面再以半蝕刻方式,於晶片座 内側底部蝕出凹入結構,俾利塑膠預模之鑲 第二步驟蝕刻完成之導線架進行電鍍處理, 鑲嵌於塑膠預模之中,該塑膠預模於晶片座 ,最後膠黏感測晶片於晶片座之頂面’並於 引腳内侧頂面間焊線,再於塑膠預模之凸牆 蓋板,俾以包覆該感測晶片,完成封裝程序 本發明之上述及其他目的與優點,不難從下述所選用 實施例之詳細說明與附圖中,獲得深入了解。Page 6 200423304 V. Description of the invention The second and half # engraving contains: a sense has to say that the sensing chip inside the top surface of the wafer to be measured to make the first process of the pins to flatten the benefit of the subsequent plastic second to the flat bottom and each The third step is to embed and electrically attach the sensor chip to form the top surface of the sensor chip. (3) Process the chip holder chip system. Follow the steps above, such as step-like position, glue pre-step, and step-like pin isolation. And various glass and packaging structures, in which, the structural package of the image sensor, a single-layer lead frame and a glass cover plate; the lead frame and a plurality of pins, the inside of each pin surrounds the periphery of the chip holder; and is adhered to the chip The top surface of the seat is connected with gold pins to transmit electrical signals; and the glass cover is covered with the sense, the above three are packaged with plastic material as a whole, and the main part is: the top surface of the conductor substrate The substrate and shape of the wafer seat are etched by semi-etching, and a number of through holes are silvered in place, and the mold is fixed. The bottom surface of the conductor substrate is etched into the concave junction at the bottom of the inside of the wafer seat by semi-etching. The lead frame that has been etched in the second step of the plastic pre-mold is plated and embedded in the plastic pre-mold. The plastic pre-mold is in the wafer holder. Finally, the sensing chip is glued on the top surface of the wafer holder. Welding wires between the top surfaces of the pins, and then covering the sensing chip with a plastic pre-molded convex wall cover to complete the packaging process. The above and other objects and advantages of the present invention are not difficult to choose from the following. The detailed descriptions of the embodiments and the accompanying drawings have gained in-depth understanding.

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第7頁 200423304 五、發明說明(4) 當然,本發明在某些另件上,或另件之安排上容許有 所不同,但所選用之實施例,則於本說明書中,予以詳細 說明,並於附圖中展示其構造。 【實施方式】 請參閱第1圖至第5圖所示,圖中所示者為本發明所 選用之實施例,此僅供說明之用,在專利申請上並不受此 種結構之限制。Page 7 200423304 V. Description of the invention (4) Of course, the present invention allows some differences in the arrangement of other parts, or the arrangement of other parts, but the selected embodiment is explained in detail in this specification. The structure is shown in the drawings. [Embodiment] Please refer to FIG. 1 to FIG. 5 for illustration, which is the selected embodiment of the present invention. This is for illustration purpose only, and it is not limited by this structure in patent application.

本發明係有關一種影像感測器之單層導線架二次半蝕 刻製程與封裝結構,如第5圖所示,該影像感測器之結構 包含:一感測晶片1 ,一單層導線架2與一玻璃蓋板4。 該導線架具有一晶片座2 1與若干引腳2 2 ,各引腳2 2 内側環繞晶片座2 1周緣俗稱内引腳2 2 1 ,其係用以連 接感測晶片1之信號接點;而各引腳2 2外側延伸至封裝 體之外俗稱外引腳2 2 2 ,其係用以焊接外部印刷電路版 之SMT接腳,俾利電信號之傳遞。 該感測晶片1係黏貼於晶片座2 1之頂面’並以金線 1 1連接各内引腳2 2 1頂面,而將感測晶片1之各信號 接點連接至外界信號接腳,俾利感測晶片1與外界之通訊 〇The invention relates to a second-layer half-etching process and packaging structure of a single-layer lead frame of an image sensor. As shown in FIG. 5, the structure of the image sensor includes: a sensing chip 1, and a single-layer lead frame. 2 与 1 Glass cover 4. The lead frame has a chip holder 2 1 and a plurality of pins 2 2, and each pin 2 2 surrounds the periphery of the chip holder 2 1 and is commonly called an inner pin 2 2 1, which is used to connect the signal contacts of the sensing chip 1; Each pin 2 2 extends outside the package body and is commonly called an outer pin 2 2 2, which is used to solder the SMT pins of an external printed circuit board to facilitate the transmission of electrical signals. The sensing chip 1 is adhered to the top surface of the chip holder 2 1 and is connected to the top surface of each inner pin 2 2 1 with a gold wire 1 1, and each signal contact of the sensing chip 1 is connected to an external signal pin. The communication between the sensor chip 1 and the outside world.

該玻璃蓋板4係覆蓋於感測晶片1之上方,用以保護 該感測晶片1 ,並利於光線穿透至感測晶片1 。 以上三者係以塑膠材料封裝為一體,其主要製作程序 如下: 第一步驟:The glass cover 4 covers the sensing chip 1 to protect the sensing chip 1 and facilitates light to penetrate to the sensing chip 1. The above three are packaged with plastic material as a whole. The main production process is as follows: First step:

第8頁 200423304 五、發明說明(5) 如第1圖所示,於平板狀導體基材之頂面以半蝕刻方 式蝕出晶片座2 1與各引腳2 2之位置與形狀,並於適當 位置蝕出若干貫穿孔2 3 、錨孔2 4。其中,貫穿孔2 3 於後續塑膠預模3射出之過程,將於晶片座2 1頂面形成 若干凸粒3 1 ,俾以控制感測晶片1黏貼至晶片座2 1時 之水平角度,防止感測晶片1傾斜,影響後續焊線的品質 ,另一方面,其亦強化塑膠預模3與晶片座2 1之接合。 而位於各引腳2 2位置錨孔2 4 ,於塑膠預模3射出之過 程,將作為塑膠預模3固定於導線架2之基礎,強化塑膠 預模3與各引腳2 2之接合,增加整體封裝之信賴性品質 〇 第二步驛: 如第2圖所示,於平板狀導體基材之底面再以半蝕刻 方式,於晶片座2 1底部與各内引腳2 2底部蝕出凹入結 構2 5 ,俾利塑膠預模3之鑲嵌與電性隔離。經過兩次半 蝕刻過程,如第2圖、第4圖所示,整體導線架2之立體 結構已成型。 第三步驟: 如第3圖所示,將第一、第二步驟蝕刻完成之導線架 2進行電鍍處理;再如第5圖所示,以射出方式將導線架 2鑲嵌於塑膠預模3之中,並且該塑膠預模3於晶片座2 1周圍形成凸牆3 2 。最後以銀膠膠黏感測晶片1於晶片 座2 1之頂面,並於感測晶片1與各内引腳2 2 1頂面間 焊接金線1 1 ,俾利電信號之傳導。再於塑膠預模3之凸Page 8 200423304 V. Description of the invention (5) As shown in Figure 1, the positions and shapes of the wafer holder 21 and the pins 22 are etched on the top surface of the flat conductor substrate by half etching, and A plurality of through holes 2 3 and anchor holes 24 are etched in place. Among them, in the process of injection of the through hole 2 3 in the subsequent plastic pre-mold 3, a plurality of bumps 3 1 will be formed on the top surface of the wafer holder 21 to control the horizontal angle when the sensing wafer 1 is stuck to the wafer holder 21 to prevent The tilt of the sensing chip 1 affects the quality of subsequent bonding wires. On the other hand, it also strengthens the bonding of the plastic pre-mold 3 and the chip holder 21. The anchor holes 2 4 located at the positions of the pins 22 and 22 will be used as the basis for fixing the plastic pre-mold 3 to the lead frame 2 during the injection of the plastic pre-mold 3 to strengthen the bonding of the plastic pre-mold 3 and the pins 22. Increase the reliability quality of the overall package. Second step: As shown in Figure 2, the bottom surface of the flat conductor substrate is etched on the bottom of the wafer holder 2 1 and the bottom of each inner pin 2 2 by semi-etching. The recessed structure 2 5, the inlay and electrical isolation of the 俾 利 preform 3 are isolated. After two half-etching processes, as shown in Figs. 2 and 4, the three-dimensional structure of the entire lead frame 2 has been formed. Third step: As shown in FIG. 3, the lead frame 2 that has been etched in the first and second steps is electroplated; and as shown in FIG. 5, the lead frame 2 is embedded in the plastic pre-mold 3 by injection. And the plastic pre-mold 3 forms a convex wall 3 2 around the wafer holder 21. Finally, the silver chip 1 is used to bond the sensing chip 1 to the top surface of the wafer holder 21, and a gold wire 1 1 is welded between the sensing chip 1 and the top surface of each inner pin 2 2 1 to facilitate the transmission of electrical signals. Convex to the plastic preform 3

—丨一— 五、發明說明(6) 牆.3 2頂面已u ¥膠 -- :完成封裝程序破瑪蓋板3,俾以包覆該感測晶 、、、、示上所述,本發明可、 問題,而提供-ϊΐΐΪ統導線架機械衝壓製程 =、、、Q構。由於,導線架2 = V線架二次半蝕刻製程與 =衣作,精度可達到積 體結構係以兩次半蝕刻製 f1信號接點之焊接可‘::之微米等級,因而與感測晶 :f、高畫素之影像感測 :的精度配♦,對於當今高 易達到良好信賴品質。曰曰裝,著實為上上之選,容 再者,本發明兩次丰你Μ、 分子等級,同時避免只=過程係化學加工,精度可達 整度可以有更好的程,因而引腳22之平 ,亦為堆疊式製法接_ 70王不忑配合引腳2 2導正程序 。而且,對後;且产精度速 去中途運過程可完全於同-機台完成,免 工時;壓:成本,同時可以節省加 、 、、— 者貝可明一新穎進步之技術。 限牛I Γ上所述貝施例之揭示係用以說明本發明,並非用以 =本發明’故舉凡數值之變更或等效元件之置換仍應 ’本發明之範疇。 由以上詳細說明,可使熟知本項技藝者明瞭本發明的 可達成前述目的,實已符合專利法之規定,爰提出專利 T請。 第10頁 200423304 圖式簡單說明 【圖式簡單說明】 第1圖係本發明導體基材之頂面半蝕刻側視圖 第2圖係本發明導體基材之底面半蝕刻側視圖 第3圖係本發明導線架電鍍示意圖 第4圖係本發明導線架蝕刻完成上視圖 第5圖係本發明感測晶片封裝完成圖 第6圖係習用衝壓式導線架製法封裝完成圖 第7圖係習用堆疊式導線架側視圖 第8圖係習用堆疊式導線架塑膠預模鑲嵌圖 第9圖係習用堆疊式導線架製法封裝完成圖 【圖號說明】 (習用部分)— 丨 一 — V. Description of the invention (6) Wall. 3 2 The top surface has been glued:: Complete the packaging process to break the cover 3, and cover the sensor crystal, as shown above, The present invention can provide the mechanical stamping process of the conventional lead frame = ,,, and Q structure. Because the lead frame 2 = the second half-etching process of the V wire frame and the garment, the precision can reach the integrated structure. Welding of the f1 signal contact made by two half-etching is possible. Crystal: f, high-pixel image sensing: The accuracy is equipped with ♦, which can achieve good trust quality for today's high-easy. Dressing is really the best choice. Rather, the invention twice enriches your molecular and molecular grades, while avoiding only = process chemical processing. The accuracy can reach a better degree. 22 of the flat, also for the stacking method to connect _ 70 Wang does not match the lead 2 2 lead program. Moreover, the production accuracy can be completely completed on the same machine in the middle of the transportation process, free of man-hours; pressure: cost, and at the same time can save a new and improved technology. The disclosure of the above-mentioned examples of the limiting example I Γ is used to explain the present invention, and is not used to = the present invention, so that any change in numerical values or replacement of equivalent components should still be within the scope of the present invention. From the above detailed description, those skilled in the art can understand that the present invention can achieve the aforementioned purpose, and it has indeed complied with the provisions of the Patent Law. Page 10 200423304 Brief description of the drawings [Simplified description of the drawings] Figure 1 is a side view of the semi-etched top surface of the conductive substrate of the present invention. Figure 2 is a side view of the semi-etched bottom surface of the conductive substrate of the present invention. Schematic diagram of the plating of the lead frame of the invention. Figure 4 is the top view of the lead frame of the present invention after the etching is completed. Figure 5 is the completion of the sensing chip packaging of the present invention. Figure 6 is the packaging completed by the conventional stamping lead frame. Figure 7 is the conventional stacked lead. Side view of the frame. Figure 8 shows the plastic pre-moulded inlay of the conventional stacked lead frame. Figure 9 shows the package completed drawing of the conventional stacked lead frame. [Illustration of drawing number] (conventional part)

第11頁 晶 片 座 7 1 引 腳 7 2 樣 板 8 1 % 8 2 晶 片 座 8 3 引 腳 8 4 、 8 ( 本 發 明 部 分) 感 測 晶 片 1 金 線 1 1 導 線 架 2 晶 片 座 2 1 引 腳 2 2 内 引 腳 2 2 1 外 引 腳 2 2 2 貫 穿 孔 2 3 、 2 4 凹 入 結 構 2 5 塑 膠 預 模 3 凸 粒 3 1 凸 牆 3 2 玻 璃 蓋 版 4Page 11 Chip holder 7 1 Pin 7 2 Sample 8 1% 8 2 Chip holder 8 3 Pin 8 4, 8 (Part of the invention) Sensing wafer 1 Gold wire 1 1 Lead frame 2 Chip holder 2 1 Pin 2 2 Inner pin 2 2 1 Outer pin 2 2 2 Through hole 2 3 、 2 4 Recessed structure 2 5 Plastic pre-mold 3 Convex grain 3 1 Convex wall 3 2 Glass cover plate 4

Claims (1)

200423304 六、申請專利範圍 1 · 一種影像感測器之單層導線架二次半蝕刻(E t ch i ng )製程與封裝結構,該影像感測器之結構包含:一感 測晶片,一單層導線架與一玻璃蓋板;該導線架具有 一晶片座與若干引腳,各引腳内側環繞晶片座周緣; 該感測晶片係黏貼於晶片座之頂面^並以金線連接各 引腳内側頂面,俾利電信號之傳遞;而該玻璃蓋板係 覆蓋於感測晶片之上方,以上三者係以塑膠材料封裝 為一體,其主要製作程序如下: 第一步驟: 於平板狀導體基材之頂面以半蝕刻方式蝕出晶片 座與各引腳之位置與形狀,並於適當位置蝕出若干貫 穿孔; 第二步驟: 於平板狀導體基材之底面再以半蝕刻方式,於晶 片座底部與各引腳内側底部蝕出凹入結構,俾利塑膠 預模之鑲嵌與電性隔離; 第三步驟: 將第一、第二步驟蝕刻完成之導線架進行電鍍處 理,再以射出方式鑲嵌於塑膠預模之中,該塑膠預模 於晶片座周圍形成凸牆;最後膠黏感測晶片於晶片座 之頂面,並於感測晶片與各引腳内側頂面間焊線,再 於塑膠預模之凸牆頂面黏貼玻璃蓋板,俾以包覆該感 測晶片’完成封裝程序。 2 ·依申請專利範圍第1項所述之影像感測器單層導線架200423304 VI. Application Patent Scope 1 · A single layer lead frame secondary semi-etching (E t ch i ng) process and packaging structure of an image sensor, the structure of the image sensor includes: a sensing chip, a single Layer lead frame and a glass cover; the lead frame has a chip holder and a plurality of pins, and the inside of each pin surrounds the periphery of the chip holder; the sensing chip is adhered to the top surface of the chip holder and connected to each lead with gold wires The top surface of the inner side of the foot is used to transmit electrical signals; and the glass cover is covered above the sensing chip. The above three are packaged with plastic material as a whole. The main manufacturing process is as follows: First step: in the flat shape The top surface of the conductive substrate is etched to the position and shape of the wafer holder and each pin by a half-etching method, and a number of through holes are etched at an appropriate position. The second step is to etch the bottom surface of the flat-shaped conductive substrate by a half-etching method. A recessed structure is etched at the bottom of the chip holder and the inner bottom of each pin, and the plastic pre-mold is embedded and electrically isolated. The third step: the lead frame that has been etched in the first and second steps is plated. The plastic pre-mold is embedded in a plastic pre-mold by injection. The plastic pre-mold forms a convex wall around the wafer holder. Finally, the sensor chip is glued on the top surface of the wafer holder, and the sensor chip and the inner sides of the pins Welding wires between the surfaces, and then pasting the glass cover on the top surface of the convex wall of the plastic pre-mold to cover the sensor chip to complete the packaging process. 2 · Single-layer lead frame for image sensor as described in item 1 of the scope of patent application 第12頁 200423304 六、申請專利範圍 二次半蝕刻製程與封裝結構,其中,位於晶片座位置 之各貫穿孔,於塑膠預模射出之過程,將於晶片座頂 面形成若干凸粒,俾以控制感測晶片黏貼之水平角度 ,防止感測晶片傾斜,影響焊線之品質。 3 ·依申請專利範圍第1項所述之影像感測器單層導線架 , 二次半I虫刻製程與封裝結構,其中,位於各引腳位置 之貫穿孔,於塑膠預模射出之過程,將作為塑膠預模 ‘ 固定於導線架之基礎,強化塑膠預模與各引腳之接合 ,俾增加封裝之信賴性品質。Page 12 200423304 VI. Patent application scope Second half-etching process and packaging structure, in which the through holes located at the wafer base are ejected from the plastic pre-mold, a number of bumps will be formed on the top surface of the wafer base, Control the horizontal angle of the sensor chip to prevent the sensor chip from tilting and affect the quality of the bonding wire. 3 · According to the single-layer lead frame of the image sensor described in item 1 of the scope of the patent application, the second and half-I engraving process and packaging structure, in which the through holes at the positions of the pins are ejected in the plastic pre-mold It will be used as the basis for fixing the plastic pre-mold to the lead frame, strengthen the bonding of the plastic pre-mold to each pin, and increase the reliability quality of the package. 第13頁Page 13
TW92109167A 2003-04-16 2003-04-16 Twice semi-etching processing and packaging structure for single-layer lead frame of image sensor TW200423304A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI489602B (en) * 2005-10-24 2015-06-21 Freescale Semiconductor Inc Semiconductor structure and semiconductor packaging system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI489602B (en) * 2005-10-24 2015-06-21 Freescale Semiconductor Inc Semiconductor structure and semiconductor packaging system

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