CN101547007B - 延迟锁相环电路和显示装置 - Google Patents
延迟锁相环电路和显示装置 Download PDFInfo
- Publication number
- CN101547007B CN101547007B CN2009101298924A CN200910129892A CN101547007B CN 101547007 B CN101547007 B CN 101547007B CN 2009101298924 A CN2009101298924 A CN 2009101298924A CN 200910129892 A CN200910129892 A CN 200910129892A CN 101547007 B CN101547007 B CN 101547007B
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- CN
- China
- Prior art keywords
- delay
- output
- cell
- circuit
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- 238000010586 diagram Methods 0.000 description 29
- 230000010363 phase shift Effects 0.000 description 5
- 239000000872 buffer Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000005574 cross-species transmission Effects 0.000 description 2
- 230000001934 delay Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- HCUOEKSZWPGJIM-IYNMRSRQSA-N (e,2z)-2-hydroxyimino-6-methoxy-4-methyl-5-nitrohex-3-enamide Chemical compound COCC([N+]([O-])=O)\C(C)=C\C(=N\O)\C(N)=O HCUOEKSZWPGJIM-IYNMRSRQSA-N 0.000 description 1
- MZAGXDHQGXUDDX-JSRXJHBZSA-N (e,2z)-4-ethyl-2-hydroxyimino-5-nitrohex-3-enamide Chemical compound [O-][N+](=O)C(C)C(/CC)=C/C(=N/O)/C(N)=O MZAGXDHQGXUDDX-JSRXJHBZSA-N 0.000 description 1
- 101150070189 CIN3 gene Proteins 0.000 description 1
- 101150110971 CIN7 gene Proteins 0.000 description 1
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 1
- 101100508840 Daucus carota INV3 gene Proteins 0.000 description 1
- 101150110298 INV1 gene Proteins 0.000 description 1
- 102000008817 Trefoil Factor-1 Human genes 0.000 description 1
- 108010088412 Trefoil Factor-1 Proteins 0.000 description 1
- 102100029469 WD repeat and HMG-box DNA-binding protein 1 Human genes 0.000 description 1
- 101710097421 WD repeat and HMG-box DNA-binding protein 1 Proteins 0.000 description 1
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 1
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
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- KIWSYRHAAPLJFJ-DNZSEPECSA-N n-[(e,2z)-4-ethyl-2-hydroxyimino-5-nitrohex-3-enyl]pyridine-3-carboxamide Chemical compound [O-][N+](=O)C(C)C(/CC)=C/C(=N/O)/CNC(=O)C1=CC=CN=C1 KIWSYRHAAPLJFJ-DNZSEPECSA-N 0.000 description 1
- 230000001915 proofreading effect Effects 0.000 description 1
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- 230000009897 systematic effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Pulse Circuits (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Description
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008085665A JP4569656B2 (ja) | 2008-03-28 | 2008-03-28 | 遅延同期ループ回路および表示装置 |
JP085665/08 | 2008-03-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101547007A CN101547007A (zh) | 2009-09-30 |
CN101547007B true CN101547007B (zh) | 2012-05-30 |
Family
ID=41116169
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2009101298924A Expired - Fee Related CN101547007B (zh) | 2008-03-28 | 2009-03-30 | 延迟锁相环电路和显示装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8816733B2 (zh) |
JP (1) | JP4569656B2 (zh) |
KR (1) | KR101548745B1 (zh) |
CN (1) | CN101547007B (zh) |
TW (1) | TWI383592B (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101681782B1 (ko) * | 2010-09-02 | 2016-12-02 | 엘지디스플레이 주식회사 | 액정표시장치 |
CN104104361B (zh) * | 2013-04-08 | 2018-07-10 | 恩智浦美国有限公司 | 比较器和时钟信号生成电路 |
US9148157B2 (en) * | 2014-01-30 | 2015-09-29 | Sandisk Technologies Inc. | Auto-phase synchronization in delay locked loops |
US11874694B2 (en) * | 2020-01-10 | 2024-01-16 | Rohm Co., Ltd. | Semiconductor device and semiconductor device system |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1577622A (zh) * | 2003-07-18 | 2005-02-09 | 株式会社半导体能源研究所 | 存储器电路及包含其的显示装置和电子设备 |
US6950488B2 (en) * | 2000-09-05 | 2005-09-27 | Samsung Electronics Co., Ltd. | Delay locked-loop circuit for reducing load of variable delay unit at high-frequency operation and locking external clock signal stably |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2771464B2 (ja) * | 1994-09-29 | 1998-07-02 | 日本電気アイシーマイコンシステム株式会社 | ディジタルpll回路 |
JP3338744B2 (ja) * | 1994-12-20 | 2002-10-28 | 日本電気株式会社 | 遅延回路装置 |
US5687202A (en) * | 1995-04-24 | 1997-11-11 | Cyrix Corporation | Programmable phase shift clock generator |
JPH1079663A (ja) * | 1996-09-03 | 1998-03-24 | Mitsubishi Electric Corp | 内部クロック発生回路および信号発生回路 |
JP3530346B2 (ja) * | 1997-06-25 | 2004-05-24 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
JP3879709B2 (ja) | 2003-06-13 | 2007-02-14 | ソニー株式会社 | 遅延同期ループを用いた信号生成回路及び同信号生成回路を有する半導体装置 |
US7078950B2 (en) * | 2004-07-20 | 2006-07-18 | Micron Technology, Inc. | Delay-locked loop with feedback compensation |
US7541851B2 (en) * | 2006-12-11 | 2009-06-02 | Micron Technology, Inc. | Control of a variable delay line using line entry point to modify line power supply voltage |
-
2008
- 2008-03-28 JP JP2008085665A patent/JP4569656B2/ja not_active Expired - Fee Related
-
2009
- 2009-02-27 US US12/379,727 patent/US8816733B2/en not_active Expired - Fee Related
- 2009-03-05 TW TW098107162A patent/TWI383592B/zh not_active IP Right Cessation
- 2009-03-18 KR KR1020090022997A patent/KR101548745B1/ko not_active IP Right Cessation
- 2009-03-30 CN CN2009101298924A patent/CN101547007B/zh not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6950488B2 (en) * | 2000-09-05 | 2005-09-27 | Samsung Electronics Co., Ltd. | Delay locked-loop circuit for reducing load of variable delay unit at high-frequency operation and locking external clock signal stably |
CN1577622A (zh) * | 2003-07-18 | 2005-02-09 | 株式会社半导体能源研究所 | 存储器电路及包含其的显示装置和电子设备 |
Non-Patent Citations (1)
Title |
---|
JP特开平11-15555A 1999.01.22 |
Also Published As
Publication number | Publication date |
---|---|
JP4569656B2 (ja) | 2010-10-27 |
KR20090103735A (ko) | 2009-10-01 |
KR101548745B1 (ko) | 2015-08-31 |
US20090243678A1 (en) | 2009-10-01 |
TW201001923A (en) | 2010-01-01 |
US8816733B2 (en) | 2014-08-26 |
TWI383592B (zh) | 2013-01-21 |
CN101547007A (zh) | 2009-09-30 |
JP2009239807A (ja) | 2009-10-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: NIPPON DISPLAY CO., LTD. Free format text: FORMER OWNER: SONY CORPORATION Effective date: 20121119 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20121119 Address after: Aichi Patentee after: Japan display West Co.,Ltd. Address before: Tokyo, Japan Patentee before: Sony Corporation |
|
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120530 Termination date: 20190330 |