CN101533786A - 半导体封装的芯片粘着胶层气泡排除方法 - Google Patents

半导体封装的芯片粘着胶层气泡排除方法 Download PDF

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CN101533786A
CN101533786A CN200810083875A CN200810083875A CN101533786A CN 101533786 A CN101533786 A CN 101533786A CN 200810083875 A CN200810083875 A CN 200810083875A CN 200810083875 A CN200810083875 A CN 200810083875A CN 101533786 A CN101533786 A CN 101533786A
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洪淑慧
陈俞正
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YIN NENG TECHNOLOGY Co Ltd
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Abstract

本发明公开了一种半导体封装的芯片粘着胶层气泡排除方法，先将一个或多个制备好的半导体芯片以胶着材料粘着于载板或芯片与芯片彼此间，此载板可为衬底或导线架等各种可以承载芯片用以联系外部电子信号用的承载物。于胶着材料未老化或未完全老化前，将粘有半导体芯片的载板承置在一特定的处理槽中。处理槽为一具有一预定升温速率、预定温度及预定压力的槽室环境并能维持一预定时间，使胶着材料中及胶着材料与芯片或载板粘着界面间的气泡因温度、压力的施加而排出。

Description

半导体封装的芯片粘着胶层气泡排除方法
技术领域
本发明涉及一种半导体封装工艺设计技术领域，特别是关于一种半导体封装的芯片粘着胶层气泡排除方法。
背景技术
半导体芯片封装的功能主要有提供电能输入、信号沟通、散热功能与保护功能四大部分。若半导体芯片要有动作则需要有外来的电源來驱动，而外来的电源的供应必须藉由半导体芯片封装以分布于半导体芯片，提供稳定地电源的供应去驱动半导体芯片而运作。半导体芯片封装亦可提供信号沟通的联机。半导体芯片所产生的信号或由外界输入半导体芯片中的信号均需透过封装过程中所布设的线路来传送，而构成布设的线路最主要者即为载板。
半导体芯片无论是接受外界输入的信号或是在运作时都会产生大量的热能，藉由半导体芯片封装设计中的热传设计，将系统运作中所产生的热能有效率的去除使半导体芯片可在正常工作温度下运作。然而若是封装中存在气泡则系统运作中所产生的热将导致气泡中所蕴含的水气受热膨胀而直接影响产品的可靠性与质量，因此封装工艺中的气泡去除一直是重要的工作。
习知的半导体芯片封装过程中，必须先从晶圆切割出适当大小的芯片后再粘附于载板上。在粘附的过程中，胶着材料中、胶着材料与载板或芯片界面之间、或在胶着材料老化的过程中会产生许多气泡，造成老化后的胶着材料中会有空腔而影响产品的可靠度、质量甚至功能。
传统的方法有利用模压胶体成型过程中短暂的高温高压条件，使胶着材料的胶层气泡排出。或是藉由真空方式使气泡由胶着材料的胶层中排除。或是藉由调整上芯片机的工艺参数及制具使芯片与胶着材料界面间达到无气泡。
发明内容
(一)本发明所要解决的技术问题：
然以上所知的习用技术却仍各有其缺点，以模压胶体成型方式因乃是利用短暂的高温高压条件施予已经老化或相当程度老化的胶着材料，因此拥有较窄的工艺条件，且对较大面积芯片因其短暂的特性往往效果是有限的。
以真空方式使气泡由胶着材料的胶层中排除，通常仅限于胶着材料为胶状类(paste)而非胶膜类(film)其使用范围更为局限，而且效果相当程度为材料所影响，因此工艺条件相当窄小。
以调整上芯片机的工艺方法为达到粘着界面无空隙，上芯片机参数中的所施予的芯片温度、上片力量与力量停留时间为其经常施实的方法。但为达到上片时的胶着界面湿润度，温度提高、增加上片力量及增加上片力量停留时间都是经常施实的方向。
然而这些方向都不利于芯片质量或导致生产效率降低。此外对存在于胶着材料中的气泡此方法是无效的。另外当遇上愈大面积芯片其效果也就愈差。
因此，本发明的主要目的在于提供一种可提高排除胶层中气泡效果的方法，用以将气泡由胶着材料中及胶着材料与芯片或载板粘着界面之间排出。
本发明的另一目的在于提供一种提高产能的半导体封装工艺的方法。
(二)本发明解决问题所采用的技术手段：
本发明为解决习知技术的问题所采用的技术手段是先将半导体芯片的其中一面以胶着材料粘于载板，胶着材料可为具有热塑(Thermoplastic)或与具热固(Thermosetting)性质的合成树酯(Syntheticresin)如聚亚酰胺(Polyimide)、环氧树酯(Epoxy resin)与丙烯酸树酯(Acryl resin)等在材料未老化前加热具粘性特质的材料。
在胶着材料尚未老化或未完全老化前，将上芯片完成的载板承置于一特定的处理槽中。针对此一特定处理槽的环境条件可做一设定，且使承置于处理槽中的粘附有半导体芯片的载板可在一预定的时间内维持在一具有预定升温速度、预定温度及预定压力的槽室环境中。
利用处理槽所设定的环境条件，将存在于胶着材料中或与粘着物界面间的气泡经由气泡能量的激化(Antonie equation，描述饱和蒸汽压与温度的关系)、密闭空间里体积、温度、压力的变化的必然现象(理想气体方程式)、气泡膨胀压力与槽内所施加压力的平衡结果而自然排出。
本发明的较佳实施例中，经过排除胶层气泡的处理后可将自处理槽中取出的半导体第一芯片实施封装工艺中的打线作业。于半导体芯片表面上所设置的焊点处焊接金属线至载板表面上所预设的接触点，并继续完成半导体封装后续的步骤。
本发明的另一实施例中，已实施完打线作业的第一芯片半成品持续以另一第二芯片利用胶着材料粘着于原先第一芯片之上并反复上述工艺，置入处理槽中进行气泡的去除及老化、取出后进行打线作业。若有后续第三、第四等芯片皆可依序实施进行气泡移除的操作。
(三)本发明对照先前技术的有益效果：
经由本发明所采用的技术手段，于胶着材料未老化或未完全老化前利用一可在预定的时间内维持于一具有预定升温速率、预定温度及预定压力的处理槽环境中，用以将气泡由胶着材料中及胶着材料与芯片或载板粘着界面四周排出。
本发明的胶着材料气泡排除方法可无视于气泡的多寡、大小以及芯片的大小而适用于排除不同面积芯片的胶层气泡，以减少习知方法中利用增加芯片加压粘附于载板或上芯片的时间与力量去排除胶层中气泡的方法所需的时间。此外，即使于粘附过程中有气泡产生也可经由后续本发明的胶着材料气泡排除方法有效排除。
本发明半导体封装的芯片粘着胶层气泡排除方法能广泛配合具有一定要求的材料特质所产生的工艺条件且可无视于上芯片时气泡的存在，因此上芯片时所需要的温度、压力与时间均可有效缩短与降低使半导体封装的产能得以提高，更可以节省投资设备与成本。
本发明所采用的具体实施例，将藉由以下之实施例及附呈图式作进一步说明。
附图说明
图1是本发明半导体封装的芯片粘着胶层气泡排除方法的流程图；
图2是本发明第一实施例的载板与芯片固定区示意图；
图3是本发明第一实施例的半导体芯片粘附位置示意图；
图4是本发明第二实施例的半导体芯片粘附位置示意图；
图5是第一实施例的多个半导体芯片与载板的纵剖图；
图6是第一实施例的半导体芯片与载板承置于处理槽的纵剖图；
图7是第一实施例的胶层气泡、半导体芯片与载板的纵剖图；
图8是图7实施例中的胶层气泡8-8横剖图；
图9是第一实施例的单一打线处理的半导体芯片的纵剖图；
图10是第一实施例的单一芯片模封结构的纵剖图；
图11是第二实施例的单一打线处理的半导体芯片的纵剖图；
图12是第二实施例的单一芯片模封结构的纵剖图；
图13是第一实施例的迭置芯片模封结构的纵剖图；
图14是第二实施例的迭置芯片模封结构的纵剖图。
【主要组件符号说明】
1、1a                            载板
11                               芯片固定区
111                              金属线贯孔
12、13                           胶着材料
2、2a、2b、2c、                  半导体芯片
3、7、8、9
31、71、81、91                  芯片表面
321、322、721、722、            焊点
821、822、921、922
331、332、731、732、            金属线
831、832、931、932
341、342、741、742、            接触点
841、842、941、942
4                               处理槽
51、52、53                      气泡
6、6a、6b、6c                   封装胶体
具体实施方式
参阅图1所示，图1是本发明半导体封装的芯片粘着胶层气泡排除方法的流程图，用以说明本发明所设计的胶着材料其胶层中的气泡排除方法。
载板1可为衬底或导线架等各种可以承载芯片用以联系外部电子信号用的承载物，且于载板1表面上预设有多个芯片固定区11(如图2所示)。
首先，将制备好的半导体芯片2其中一面(如图3所示)藉由先涂布于芯片固定区11的胶着材料12以粘附于载板1表面的芯片固定区11中(步骤101)。
亦可于载板1a的芯片固定区11中设置有一贯穿载板1a的金属线贯孔111。胶着材料12可先涂布于芯片固定区11，再将半导体芯片2粘着于载板1a的芯片固定区11(如图4所示)。
于步骤101中，胶着材料12也可不必事先涂布于芯片固定区11而是以附着于半导体芯片2之上的方式连同半导体芯片2一并粘着于载板1其上。
从步骤102至105，以载板1为实例说明，而载板1a同样适用于步骤102至105。
载板1的表面上已粘附有多个上片完成的半导体芯片2、2a、2b、2c(如图5所示)，且于半导体芯片2、2a、2b、2c与载板1表面之间的胶着材料12未老化或未完全老化前，将粘附有半导体芯片2、2a、2b、2c的载板1承置在一处理槽4(如图6所示)中(步骤102)。
胶着材料12于粘着过程中，会在胶着材料12的胶层中、胶着材料12与载板1的交界面或是与半导体芯片2的交界面处会有例如图7中所示的胶层中气泡51或是交界面的气泡52、53的产生。气泡51、52、53会使得胶着材料12所形成的胶层为一不连续面如图8中所示。
为解决气泡51、52、53形成的问题，本发明的设计中的处理槽4可针对环境条件做一设定，且使承置于处理槽4中的粘附有半导体芯片2、2a、2b、2c之载板1在预定的时间中以一预定升温速率维持于一具有预定温度及预定压力的槽室环境中(步骤103)。
藉由处理槽4所设定的环境条件，将存在于胶着材料12中的气泡51、胶着材料12与载板1交界面的气泡52与胶着材料12与半导体芯片2交界面的气泡53由胶着材料12如图7中箭头所指示的方向往四周排出(步骤104)。
将经过本发明的胶层气泡排除方法处理后的载板1连同粘附于载板1表面的半导体芯片2一同移出处理槽4(步骤105)。
排除胶着材料12中的胶层气泡后，载板1所粘附的半导体芯片3(如图9所示)其芯片表面31上设置有一焊点(Bond Pad)321、322，且焊点321、322可焊接金属线331、332并经过打线(Bonding)处理连接于载板1表面上所预设的接触点341、342(步骤106)。
于执行完步骤106后，半导体芯片3继续完成半导体封装的后续步骤。于半导体芯片3的芯片表面31藉由一模具装置(未示)，以合模注胶方式去模压形成一封装胶体6(如图10中所示)于半导体芯片3外(步骤107)。
模压后所形成于半导体芯片3外的封装胶体6，需经过一烘烤处理(Post mold cure)造成封装胶体6开始老化。老化完全的封装胶体6即可模封该半导体芯片3(步骤108)，用以防止湿气由外部侵入半导体芯片3。
步骤106中，亦可于载板1a所粘附的半导体芯片7(如图11)排除胶着材料12中的胶层气泡后，半导体芯片7其芯片表面71上设置有一焊点721、722，且焊点721、722可焊接金属线731、732。金属线731、732藉由打线处理并通经过金属线贯孔111后，连接于载板1a所预设的接触点741、742。最后以合模注胶方式去模压形成一封装胶体6a(如图12中所示)于半导体芯片7外。
本发明半导体封装的芯片粘着胶层气泡排除方法亦可应用于多颗迭置芯片封装结构中。其工艺步骤参阅图1，当第一芯片例如半导体芯片3完成打线处理(步骤106)后，欲迭置多颗芯片则仅需重复半导体封装工艺步骤101至106即可。
于载板1表面上粘附的完成打线处理的半导体芯片3其芯片表面31处以另一粘附有胶着材料13的第二芯片例如半导体芯片8迭置于第一芯片的半导体芯片3上(如图13中所示)，再将此半成品置入处理槽4中进行排除胶层中的气泡。
进行完气泡排除后的半成品，于半导体芯片8其芯片表面81上设置的焊点821、822焊接一金属线831、832，并再经过打线处理连接于载板1表面上所预设的接触点841、842并接续打线处理，最后以合模注胶方式去模压形成一封装胶体6b于半导体芯片3、8外。
亦可于载板1a表面上粘附的完成打线处理的半导体芯片7其芯片表面71处于以另一粘附有胶着材料13的第二芯片例如半导体芯片9迭置于第一芯片的半导体芯片7上(图14中所示)，再将此半成品置入处理槽4中进行排除胶层中的气泡。
进行完气泡排除后的半成品，于半导体芯片9其芯片表面91上设置的焊点921、922焊接一金属线931、932，并再经过打线处理连接于载板1a上所预设的接触点941、942，并接续打线处理，最后以合模注胶方式去模压形成一封装胶体6c于半导体芯片7、9外。
由以上之实施例可知，本发明所提供的半导体封装的芯片粘着胶层气泡排除方法确具产业上的利用价值，故本发明业已符合于专利的要件。惟以上之叙述仅为本发明的较佳实施例说明，凡精于此项技艺者当可依据上述的说明而作其它种种之改良，惟这些改变仍属于本发明之发明精神及权利要求书所界定的范围中。

Claims (11)

1、一种半导体封装的芯片粘着胶层气泡排除方法，其特征在于，该方法包括下列步骤：
a、将至少一个制备好的半导体芯片的其中一面以胶着材料粘附在一载板的表面；
b、在该胶着材料于未老化或未完全老化前，将该粘附有半导体芯片的载板承置在一处理槽中；
c、将该处理槽设定在一具有预定温度及预定压力的槽室环境，并维持一预定时间；
d、使该胶着材料中的气泡或胶着材料与半导体芯片间的气泡或胶着材料与载板胶着界面间的气泡由该胶着材料的四周排出。
2、根据权利要求1所述的半导体封装的芯片粘着胶层气泡排除方法，其特征在于，步骤c中所预定的温度介于摄氏80度至175度之间。
3、根据权利要求1所述的半导体封装的芯片粘着胶层气泡排除方法，其特征在于，步骤c中所预定槽内压力为大于2个大气压。
4、根据权利要求1所述的半导体封装的芯片粘着胶层气泡排除方法，其特征在于，步骤c中所预定时间大于5分钟。
5、一种半导体封装的芯片粘着胶层气泡排除方法，其特征在于，包括下列步骤：
A、将多个制备好的半导体芯片的第一芯片其中一面以胶着材料粘附在一载板的表面；
B、在该胶着材料于未老化或未完全老化前，将该粘附有半导体芯片的载板承置在一处理槽中；
C、将该处理槽设定在一具有预定温度及预定压力的槽室环境，并维持一预定时间；
D、使该胶着材料中的气泡或胶着材料与半导体芯片间的气泡或胶着材料与载板胶着界面间的气泡由该胶着材料的四周排出；
E、将该含有半导体芯片的载板从该处理槽中取出；
F、以另一粘附有胶着材料的第二芯片迭置于该第一芯片之上，再将此半成品置入该处理槽依步骤B、C与D执行消除气泡工艺，并于消除气泡后移出该处理槽；
G、多颗迭置芯片即可依如上程序执行步骤F。
6、根据权利要求5所述的半导体封装的芯片粘着胶层气泡排除方法，其特征在于，步骤C中所预定温度系介于摄氏80度至175度之间。
7、根据权利要求5所述的半导体封装的芯片粘着胶层气泡排除方法，其特征在于，步骤C中所预定槽内压力为大于2个大气压。
8、根据权利要求5所述的半导体封装的芯片粘着胶层气泡排除方法，其特征在于，步骤C中所预定时间大于5分钟。
9、根据权利要求5所述的半导体封装的芯片粘着胶层气泡排除方法，其特征在于，步骤E之后进一步包括有半导体工艺的打线处理步骤。
10、根据权利要求5所述的半导体封装的芯片粘着胶层气泡排除方法，其特征在于，步骤F之后进一步包括有半导体工艺的打线处理步骤。
11、根据权利要求5所述的半导体封装的芯片粘着胶层气泡排除方法，其特征在于，于步骤G之后进一步包含下列步骤：
H、藉由合模注胶方式模压形成一封装胶体于该半导体芯片的表面；
I、将该封装胶体予以烘烤处理，使该封装胶体老化以模封该半导体芯片。
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CN110993512A (zh) * 2019-11-29 2020-04-10 力成科技（苏州）有限公司 一种多段式注胶工艺
CN113053760A (zh) * 2019-12-27 2021-06-29 中芯集成电路（宁波）有限公司 封装方法
CN113345810A (zh) * 2020-02-18 2021-09-03 朋程科技股份有限公司 功率二极管的制造方法
CN114899122A (zh) * 2022-02-16 2022-08-12 安泊智汇半导体设备(上海)有限责任公司 半导体芯片封装除泡设备及除泡方法
CN115463458A (zh) * 2022-07-29 2022-12-13 南京屹立芯创半导体科技有限公司 一种气泡去除装置及气泡去除方法
CN115463458B (zh) * 2022-07-29 2024-06-07 南京屹立芯创半导体科技有限公司 一种气泡去除装置及气泡去除方法

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