CN101517737B - 通过芯片通孔的倒装片互连 - Google Patents
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Abstract
一种声学组件包括具有导电通孔的集成电路封装,所述导电通孔被配置成从所述集成电路封装的有源部分穿透所述集成电路封装的底部部分。所述底部部分是所述集成电路封装的衬底的底侧。将声学元件设置在所述衬底的所述底侧上,并且将所述通孔设置成将所述集成电路封装的有源部分电耦合到所述声学元件。在一个实施例中,所述声学元件是声学叠置体,并且所述集成电路封装是ASIC。可以形成所述组件以用作微束形成换能器。
Description
技术领域
本系统涉及采用倒装片型电互连和贯穿芯片的通孔的互连方法和装置。
背景技术
现有技术集成电路(IC)的当前状态是尺寸不断缩小,复杂性不断提高。随着部件密度的提高,由电耦合部件构成的系统变得非常关键,因为物理互连占据着可用表面积的相当大的部分,从而降低了在可用表面积内设置电路的能力。
已知这样一种电互连技术,其中,通过接触突起或端头(stub)形成互连的一部分,通过接触焊盘或表面形成互连的另一部分。在制造过程中,使突起和焊盘相互接触,以形成电互连。通过引用并入到本文中如同被完全陈述的美国专利No.6015652公开了一种这样的互连系统,其用于安装在衬底上的IC且被称为“倒装片键合”。这一典型的互连系统缓解了一些与其他电互连系统相关的问题,但是该系统仍然占据着很大的本可以为电子部件所能利用的可用表面积。在对诸如专用集成电路(ASIC)的集成电路直接进行电互连时,这一问题将更加严重。
通过引用并入到本文中如同被完全陈述的PCT专利申请WO2004/052209公开了一种为形成微型化换能器阵列而将ASIC耦合到多个声学元件的系统。在所示的系统当中,将突起电耦合到声学元件或ASIC之一,并且将焊盘电耦合到声学元件或ASIC中的另一个。该系统实现了一种小的电封装,例如,可以形成所述电封装以构建用于经食道检查、腹腔镜检查和心脏内部检查的超声换能器。
当前设计的微束形成(uBF)换能器一般利用倒装片工艺以实现诸如声传感器的声学元件与微束形成器ASIC的集成。该工艺在解决将成千上万的元件互连到uBF ASIC上这一难题方面是非常成功的。然而,所得到的装置存在几个问题。例如,倒装片工艺使ASIC直接位于声学元件的后面,并且如所执行的键合类型(例如,端头突起)的规定那样接近所述声学元件的表面。然而,来自ASIC的热量可能会影响声学元件的性能。因此,从管理声学元件的表面温度的角度来看,典型的倒装片互连几乎将声学元件放置在最差的可能位置上,即,接近热源(例如,ASIC)并远离潜在的散热表面。
此外,将声学元件紧密耦合到ASIC的有源部分可能会带来产生由于将声能耦合到ASIC内而导致的模糊伪影(haze artifact)的不利影响,其中所述声能可能传播并导致声学串扰。由于无法将ASIC直接键合到声学元件上,因此ASIC和声学元件之间的倒装片工艺也很复杂。在ASIC和声学元件之间需要物理偏移,以便从切割(dicing)过程的开始到结束将由声学元件的厚度偏差和切割锯片的直径偏差引入的切割容差考虑在内。这一间隔通常是利用具有高长宽比的端头突起或电镀突块引入的,这使组装工艺变得复杂。
当前的uBF ASIC的系统输入/输出(I/O)互连局限于将系统I/O设置在处于ASIC的顶部有源部分上的两个方位边缘上。这需要分配一些空间,以将来自ASIC的顶表面上的键合焊盘的互连提供给诸如柔性电路的下一级互连。可以利用引线键合或者采用各向异性导电膜的键合软线实现互连目的,然而,在任一种情况下,整个换能器(例如,ASIC、声传感器、软线)的物理空间的限制降低了可用于换能器的声学孔径的接触面积的量。此外,出于空间的考虑,柔性电路通常相对简单,只具有几个互连层,这可能限制电性能和/或增加成本。
发明内容
本系统的目的是克服现有技术中的缺点和/或对现有技术做出改进。
本系统包括声学组件和形成所述组件的方法。所述声学组件包括集成电路封装,其具有配置成从所述集成电路封装的有源部分穿过所述集成电路封装的底部部分的导电通孔。所述底部部分是所述集成电路封装的衬底的底侧。将声学元件设置在所述衬底的所述底侧上,并且将所述通孔设置成将所述集成电路封装的所述有源部分电耦合到所述声学元件。在一个实施例中,所述声学元件是声学叠置体。在另一实施例中,所述声学元件是基于硅的微机械加工的超声换能器(MUT)。
在形成所述声学组件的过程中,对所述声学组件进行切割,所述切割贯穿所述声学叠置体,并且进入到所述衬底内。可以在不考虑所述声学元件和所述集成电路封装之间的耦合距离的情况下,通过反转倒装片(invertedflip-chip)互连、导电粘合剂和/或其他适当的耦合系统将所述声学元件耦合到所述通孔。有利地,可以将所述互连装置设置在所述集成电路封装的接近所述有源部分的顶侧上,并且使所述互连装置电耦合到所述集成电路封装的系统输入/输出(I/O)连接。可以在不需要引线键合和其他用于使系统I/O延伸到所述集成电路封装的边缘系统的情况下,通过倒装片互连和/或其他适当的耦合系统将所述互连装置耦合到所述系统I/O连接。在一个实施例中,所述互连装置可以是包括印刷电路板(PCB)的柔性电路。所述集成电路封装可以是用于换能器的微束形成器ASIC,所述换能器例如为可以用于进行经食道检查、腹腔镜检查和心脏内部检查的超声换能器。
附图说明
将参考附图通过举例的方式进一步详细说明本发明,在附图中:
图1示出根据本系统的实施例制备的晶片级集成电路的一部分的示例性侧面透视图;
图2示出根据本系统的实施例的ASIC的示例性透视图;
图3示出根据本系统的实施例的示例性元件,例如,耦合到电部件的由声学元件构成的板或叠置体;
图4示出根据本系统的耦合到电部件的由声学元件构成的叠置体在被切割之后的情况;以及
图5示出根据本系统的实施例的互连系统的细节。
具体实施方式
下文是对示例性实施例的说明,通过与附图结合,所述示例性实施例将展示上述以及其他特征和优点。在下述说明中,出于解释的目的而不是限制的目的阐述了诸如架构、界面、技术等具体细节,用于举例说明。然而,对于本领域技术人员而言,显然可以理解,其他脱离这些细节的实施例也将落在权利要求的范围内。而且,为了清晰起见,省略了对公知装置、电路和方法的详细说明,以避免使对本系统的说明难以理解。此外,应当明确理解,包含附图的目的只是为了举例说明,而不是表示本系统的范围。在附图和说明书中,采用类似的附图标记表示类似的元件。
图1示出根据本系统的实施例制备的诸如ASIC 100的晶片级集成电路的一部分的示例性侧面透视图。ASIC 100形成在硅衬底110上,并且包括代表ASIC 100的有源部分130的微通道有源体积,其中对来自声学元件的声信号进行处理。典型地,可以将微通道有源体积形成为侧边在100-400um的范围内,例如为250um的正方形区域,并且可以将其形成为具有在5-20um的范围内的深度,例如具有10um的深度。ASIC 100还包括通常用于将ASIC100的有源部分的部分互连到声学元件的键合焊盘区域120。ASIC 100可以通过典型的工艺动作例如光刻工艺来形成,所述光刻工艺包括对所期望的层的光沉积、蚀刻、掩模等。
在对ASIC 100的晶片级处理过程中,可以在键合焊盘区域120中形成贯穿ASIC的通孔。所述贯穿ASIC的通孔提供了从位于ASIC的有源部分130中的传感器输入/输出(I/O)穿过ASIC的底表面,从而穿过衬底110的导电通路。可以利用适当的光刻和镀覆工艺例如蚀刻和电镀来形成所述通孔和导电通路。
图2示出根据本系统的实施例的ASIC 200的示例性透视图。如图所示,ASIC 200包括贯穿ASIC的通孔240,其提供了从ASIC 200的有源部分202的I/O穿过衬底210到达ASIC 200的底表面204的导电通路。通过这种方式,根据本系统,使通常耦合到诸如声学叠置体的声学元件的ASIC的I/O一直走线(route through)到ASIC 200的底部部分204。在形成穿孔240之后,可以通过使ASIC 200与晶片分离而使ASIC 200单个化,以制备用于电耦合到声学元件的ASIC 200。
图3示出一种示例性元件,例如耦合到诸如ASIC 300的电部件的由声学元件355构成的板或叠置体350。根据本系统,由于沿ASIC 300的远离有源部分330的底部部分304将声学元件355耦合到ASIC 300,因此可以利用任何适当的耦合工艺将声学元件355电耦合到ASIC,而无需考虑耦合的高度方面。例如,可以利用导电粘合剂或引线突起,而无需考虑互连本身的高度。在一个实施例中,实际上,可以将声学元件反转倒装片键合到ASIC上。术语“反转倒装片键合”是指,本系统使得声学元件键合到ASIC的底侧,这与现有的倒装片键合技术相反,在现有技术中将声学元件键合到ASIC的紧靠近ASIC I/O的顶(有源)侧。与现有系统不同的是,不需要相对较大的耦合高度来容纳切割工艺中所需的容差,因为通过ASIC 300的衬底310使ASIC的有源部分330与声学元件355分开。相应地,还可以在不考虑耦合高度的情况下适当采用其他的用于将声学元件355耦合到ASIC 300的系统。
应当指出,ASIC 300的有源部分330通常是产生热量的部位。根据本系统,将有源部分330设置成进一步远离声学元件355和由声学元件355、ASIC 300等形成的换能器的表面。与现有系统不同的是,通过这种方式,极大简化了管理换能器表面温度的问题。此外,还可以将有源部分330设置成与先前的可能接近程度相比更接近热沉。通过这种方式,根据本系统,提高了到声学元件的热阻,同时降低了到热沉的热阻。
在使声学元件355电耦合到ASIC 300之后,可以施加底层填料,以使所述板相对于ASIC 300保持稳定。底层填料有助于保护声学元件355和ASIC 300之间的电耦合不受环境条件的影响,为组件提供额外的机械强度,用作有助于将热量从声学元件355驱散开的热沉,并且可以有助于补偿所述叠置体的声学元件和ASIC 300之间的任何热膨胀差异。
可以利用沉积工艺、光刻工艺和/或其他类似工艺为所述叠置体提供二维切割网格图案360,以有助于对声学叠置体的切割。如图4所示,可以例如采用切割锯(例如,金刚石颗粒锯)切割叠置体350(例如,参见切口470),从而将叠置体350分成单独的声学元件455。应当容易理解,声学元件455可以具有任何类型和结构,包括有助于3维(3D)成像例如可以用于3D超声成像应用的结构和/或矩阵换能器结构。
通常,如上文讨论的所要求的切割容差使得将ASIC 400电耦合到声学元件455的难度增加。分离各个声学元件455的切口470必须深到足以将叠置体350分成单独的声学元件455。在几个因素的作用下,要求具有较大的切割深度容差。例如,叠置体350的厚度存在偏差。通常,所述叠置体是三种或更多种材料的叠层,即,去匹配层452(例如,碳化钨)、作为转发器的压电晶体层454、以及一个或多个匹配层456(例如,石墨)。三种层叠材料,例如各自具有不同的物理特性,可以导致并非完全平坦的声学叠置体。
此外,形成如此多的切口(例如,数千个)将导致切割锯的锯片磨损。因此,即使对于指定深度的切口,由于锯片磨损,最后的切口的深度也将小于最初的切口的深度。为了补偿这一切口深度的偏差,通常选择切口深度以将较浅的后面的切口考虑在内。此外,由先前在几个单独工艺中结合(例如层叠)在一起的很多部件构成的结构存在累积容差的问题。例如,层的厚度的容差,加上层的平坦度的容差,加上键合厚度的容差等可能导致从所述结构的一部分到所述结构的另一部分的大的累积偏差。还必须通过在切口深度中引入相应的大容差来调节这一潜在的大偏差。
通常将上文列举的所有构成容差加在一起会导致这样的要求,即,在叠置体350和ASIC 400之间具有相对较大(例如,70-100um)的间隙。现有系统中的这一对大间隙的要求将转换成相应的大突起高度。然而,根据本系统,利用导电的贯穿ASIC的通孔440将叠置体350电耦合到ASIC 400。相应地,将叠置体350设置在紧邻ASIC 400的衬底层410、远离ASIC 400的顶部部分402的底部部分404上,ASIC 400的有源部分430和I/O位于所述顶部部分402中。由于衬底410不是ASIC 400的有源部分,因此可以在几乎不用担心对ASIC 400造成潜在损害的情况下切割叠置体350,同时仍然通过穿过叠置体350以及衬底410的一部分进行切割而将切割容差考虑在内。例如,对于厚度在50um到400um的范围内的ASIC衬底层,可以容易地使切割切口470穿过衬底的一部分,而不会影响ASIC的结构或电学完整性,如图4所示。
对衬底的一部分进行切割的额外好处在于,可以通过衬底410的部分的去耦合(分离)来减少由于将声能耦合到ASIC中而产生的模糊伪影。此外,由于将声学元件455设置成更加远离有源部分430,因此进一步降低了将声能耦合到ASIC 400中的可能性。
根据本系统,由于将声学元件设置在远离ASIC的I/O的ASIC的底部部分上,因此为电耦合到其他I/O例如ASIC的传感器I/O提供了更大的灵活性。图5示出根据本系统的实施例的互连系统的细节。所述系统包括诸如ASIC 500的电部件,其中使叠置体550的声学元件555电耦合到ASIC500的背面504,从而使顶部部分502可用于电耦合选项的广泛选择。ASIC500包括衬底510和通孔540。根据本系统可实现的灵活的互连相对于现有系统具有极大的改进,因为可以在不需要引线键合迹线、各向异性导电膜等的情况下使ASIC 500直接附着到诸如柔性电路580、PCB 585等的互连衬底。这通过能够使更复杂的互连和电路(旁路电容等)更接近ASIC而提供提高电性能的能力。利用本系统,可以将更复杂的互连装置设置成与在采用现有系统不得不使用的相对简单的柔性电路的情况下可能实现的接近程度相比更接近ASIC。将互连设置成与ASIC的I/O直接相邻的能力还有助于通过消除对至ASIC的顶表面的引线键合、ACF等的需要而简化互连过程,在现有系统中,需要所述引线键合、ACF等调节声学元件与ASIC I/O的典型接近度。最后,由于本系统的系统I/O不必环绕ASIC的顶部边缘以避开声学元件,因此根据本系统的互连方法可以潜在地消除对用于微束形成阵列的插入物的需要,所述阵列需要平铺两行以上的ASIC。
在所示的示例性实施例中,提供了刚性-柔性互连580。利用本领域公知的接触球590将图5示例性示出的互连580耦合到ASIC 500。此外,可以将互连580倒装片安装到ASIC 500上。
有利地,根据本系统的互连系统提供了下列中的一个或多个:提高的热性能、提高的声学性能、工艺简化、互连改进和互连简化。
当然,应当意识到,根据本系统,可以将上述实施例或工艺中的任何一个与一个或者与一个或多个其他实施例或工艺相结合以提供更进一步的改进。
最后,上述讨论的目的只是对本系统进行举例说明,不应将其视为将所附的权利要求限于任何具体的实施例或一组实施例。因此,尽管已经参考本系统的具体示例性实施例(例如,ASIC、声学元件等)对本系统进行了特别详细的说明,但是还应当认识到在不背离如所附权利要求所述的本系统的较宽和预期的精神和范围的情况下,本领域技术人员可以想出各种变型和可选实施例。相应地,应当将说明书和附图视为采取了举例说明的方式,其并非旨在限制所附权利要求的范围。
在解释所附权利要求时,应当理解:
a)“包括”一词不排除在指定权利要求中列出的元件或动作以外的其他元件或动作的存在;
b)元件前面的词“一”或“一个”不排除多个这样的元件的存在;
c)权利要求中的任何附图标记均不限制权利要求的范围;
d)几个“装置”可以由同一项硬件或软件实施的结构或功能来表示;
e)所公开的元件中的任何一个都可以由硬件部分(例如,包括分立的和集成的电子电路)、软件部分(例如,计算机编程)及其任意组合组成;
f)硬件部分可以由模拟和数字部分之一或这二者组成;
g)可以将所公开的任何装置或其部分结合到一起,或者可以将其分成更多的部分,除非另行明确说明;以及
h)不旨在要求动作或步骤的任何特定顺序,除非另行明确说明。
Claims (14)
1.一种声学组件,包括:
集成电路封装,其包括导电通孔(240)的两维图案,所述导电通孔(240)配置成从所述集成电路封装的有源部分穿透所述集成电路封装的底部部分,其中所述底部部分是所述集成电路封装的半导体衬底(110)的底侧;以及
设置在所述衬底的所述底侧上并电耦合到所述导电通孔(240)的声学叠置体(350),
其中将所述通孔设置成将所述集成电路封装的所述有源部分电耦合到所述声学叠置体(350)的两维阵列的元件(455);并且
其中通过沿两个方向延伸穿过所述声学叠置体并且进入到所述集成电路封装的所述半导体衬底内的切割切口(470),将所述声学叠置体(350)切割为所述两维阵列的元件(455)。
2.根据权利要求1所述的声学组件,其中通过反转倒装片互连将所述声学叠置体耦合到所述通孔。
3.根据权利要求1所述的声学组件,其中通过导电粘合剂将所述声学叠置体耦合到所述通孔。
4.根据权利要求1所述的声学组件,其包括互连装置,所述互连装置设置在所述集成电路封装的接近所述有源部分的顶侧上,并且电耦合到所述集成电路封装的系统输入/输出(I/O)连接。
5.根据权利要求4所述的声学组件,其中通过倒装片互连将所述互连装置耦合到所述系统I/O连接。
6.根据权利要求4所述的声学组件,其中所述互连装置是包括印刷电路板(PCB)的柔性电路。
7.根据权利要求1所述的声学组件,其中所述集成电路封装是微束形成器ASIC。
8.一种形成声学组件的方法,所述方法包括以下动作:
提供集成电路封装;
在所述集成电路封装中形成导电通孔的两维图案,所述导电通孔从所述集成电路封装的有源部分贯穿到所述集成电路封装的底部部分,其中所述底部部分是所述集成电路封装的半导体衬底的底侧;
将声学叠置体设置在所述衬底的所述底侧上;
通过所述通孔将所述声学叠置体电耦合到所述集成电路封装的所述有源部分;以及
利用沿两个方向延伸穿过所述叠置体并且进入到所述衬底内的切割切口,将所述叠置体切割为两维阵列的换能器元件。
9.根据权利要求8所述的方法,其中耦合包括执行反转倒装片耦合工艺的动作。
10.根据权利要求8所述的方法,包括以下动作:
对所述集成电路封装的接近所述有源部分的顶侧进行蚀刻,以露出系统输入/输出(I/O)连接;以及
沉积电耦合到所述系统I/O连接的键合焊盘。
11.根据权利要求10所述的方法,包括以下动作:
将互连装置设置在所述顶侧上;以及
将所述互连装置电耦合到所述系统I/O连接。
12.根据权利要求11所述的方法,其中将所述互连装置电耦合到所述系统I/O连接的动作包括执行倒装片耦合工艺的动作。
13.根据权利要求11所述的方法,其中所述互连装置是包括印刷电路板(PCB)的柔性电路。
14.根据权利要求13所述的方法,其中所述集成电路封装是微束形成器ASIC。
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- 2007-09-18 AT AT07826430T patent/ATE454713T1/de not_active IP Right Cessation
- 2007-09-18 RU RU2009115685/28A patent/RU2449418C2/ru active
- 2007-09-18 CN CN200780035443.2A patent/CN101517737B/zh active Active
- 2007-09-18 EP EP07826430A patent/EP2070114B1/en active Active
- 2007-09-18 DE DE602007004242T patent/DE602007004242D1/de active Active
- 2007-09-18 WO PCT/IB2007/053771 patent/WO2008038183A1/en active Application Filing
- 2007-09-21 TW TW096135619A patent/TW200826209A/zh unknown
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Also Published As
Publication number | Publication date |
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US8242665B2 (en) | 2012-08-14 |
JP5175853B2 (ja) | 2013-04-03 |
CN101517737A (zh) | 2009-08-26 |
RU2449418C2 (ru) | 2012-04-27 |
DE602007004242D1 (de) | 2010-02-25 |
WO2008038183A1 (en) | 2008-04-03 |
EP2070114A1 (en) | 2009-06-17 |
JP2010504639A (ja) | 2010-02-12 |
ATE454713T1 (de) | 2010-01-15 |
EP2070114B1 (en) | 2010-01-06 |
US20100025785A1 (en) | 2010-02-04 |
RU2009115685A (ru) | 2010-11-10 |
TW200826209A (en) | 2008-06-16 |
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