CN101517730B - 在晶片上的硅化物形成 - Google Patents

在晶片上的硅化物形成 Download PDF

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CN101517730B
CN101517730B CN2007800361008A CN200780036100A CN101517730B CN 101517730 B CN101517730 B CN 101517730B CN 2007800361008 A CN2007800361008 A CN 2007800361008A CN 200780036100 A CN200780036100 A CN 200780036100A CN 101517730 B CN101517730 B CN 101517730B
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silicide
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wafer
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silication
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埃里克·格里岑
韦罗妮克·德-容
斯尔詹·科尔迪克
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Koninklijke Philips NV
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Abstract

一种在半导体晶片上选择性形成硅化物的方法，其中在施加SiProt掩膜(10，16，22)之前在整个晶片上沉积金属层(12)，从而对掩膜(10，16，22)的任何蚀刻都不会导致硅晶片的任何表面损伤。

Description

在晶片上的硅化物形成
技术领域
本发明涉及一种在半导体晶片上选择性地形成硅化物的方法。
背景技术
MOS晶体管是半导体器件的重要部件，MOS晶体管的栅极的电特性直接影响到这类器件的质量。MOS晶体管的栅极区典型地包括作为主导电层的多晶硅层或非晶硅层，以及有时候在主导电层上堆叠的硅化物层，例如硅化钴或硅化钛或硅化镍。类似地，MOS晶体管的源极和漏极有源区典型地包括可由硅化物层覆盖的掺杂硅层。这些硅化物层提供了良好的欧姆接触，从而减小了MOS晶体管的层电阻并增加了其中结合了该MOS晶体管的半导体器件的运行速度。
存在许多期望减小集成电路的一些晶体管的接触电阻并通过维持较高接触电阻来保护其它晶体管免受静电放电影响的应用。因此，期望选择性地对需要减小接触电阻的晶体管的栅极、漏极和/或源极区进行硅化而保持其它晶体管的相应区域不被硅化，从而维持有源区和多晶硅区都具有较高接触电阻和方块电阻(sheet resistance)。
在一些已知方法中，典型地采用掩模来防止在不想被硅化的区域上形成硅化物。该掩模可以由叠层来形成，一方面，叠层包括例如通过CVD(化学气相沉积)从原硅酸四乙酯(TEOS)得到的二氧化硅(SiO2)层之类的氧化层，另一方面，叠层包括例如氮化硅(Si3N4)层之类的氮化层。现有技术中将这样的掩模称为硅保护掩模或“SiProt”掩模。在该掩模保护的晶片区域上不形成硅化物。
然而，在上述方法中有许多缺点。掩模的形成需要热预算，该热预算在90nm以及更小的工艺中与结不是太兼容。另外，还会在MOS晶体管中产生应力。最后，上述方法本身需要相对多的步骤，尤其是在沉积钴(Co)之前为去除SiO2阻止层的去氧步骤，这导致挖出不期望的STI(浅槽隔离)槽。
公开号为US2005/64638的美国专利申请描述了一种意在减轻上述缺点的在晶片上选择性地形成硅化物的方法。所提出的方法包括步骤：a)在不想被硅化的区域顶部形成阻止层，b)经由阻止层进行离子注入，c)去除阻止层，d)在该薄层上沉积一个金属层(该金属能够通过与硅进行热反应来形成硅化物)，e)执行适合于对通过步骤d)所沉积的金属进行硅化的热处理，以及f)将没有对步骤e)的热处理进行反应的金属去除。
然而，在该处理流程中，必须在需要硅化的区域处蚀刻SiProt掩模(阻止层)，因此使得这些区域易受蚀刻处理的侵蚀，导致不期望的表面损伤。
发明内容
因此，最好提供一种用于在晶片上选择性地形成硅化物的方法，其中防止了在SiProt层的蚀刻过程中对要被硅化的区域的损伤。
根据本发明，提供了一种在半导体晶片上选择性地形成硅化物的方法，该半导体晶片包括要在其上形成硅化物的第一区域和不想在其上形成硅化物的第二区域，该方法包括：
a)在所述晶片上沉积金属层来覆盖所述第一和第二区域；
b)沉积掩模层来覆盖所述金属层；和
c)执行硅化工艺；
其中使所述掩模层形成图案以使得仅在所述第一区域中的金属暴露于所述硅化工艺。
这样，因为在掩模层之前沉积金属层，所以晶片表面不会遭受任何掩模蚀刻的侵蚀和随后的劣化。
在一个示例实施例中，使掩模层形成图案以使得仅暴露出在半导体晶片的第二区域中的金属层，并随后在执行硅化工艺之前(优选地通过湿法或干法蚀刻)去除金属层的暴露部分。优选地，随后执行选择性蚀刻工艺来去除任何未反应的金属。
在另一个示例实施例中，使掩模层形成图案来仅暴露处在第一区域中的金属层，接下来，在执行硅化工艺之前沉积非晶硅盖层来覆盖第一和第二区域。在这种情况下，可通过干法蚀刻使掩模层形成图案，并且优选地在达到大约100-150℃的相对低的温度下沉积非晶硅盖层。优选地，在硅化工艺之后再次执行选择性蚀刻工艺，以便去除任何残留的或未反应的材料。在一个实施例中，在沉积掩模层之前可以沉积电介质层，并且使用掩模层来蚀刻电介质层，以便仅留下未被暴露于所述硅化工艺的区域中的所述电介质层。
将理解的是金属层可以包括能够被硅化的任何适合的金属，包括但不限于Co、Ni、Ti等。类似地，掩模可以包括任何适合的材料，包括但不限于氧化物、氮化物、碳化物或无定形碳，或者它们的组合。
通过参照下面描述的实施例将明了和说明本发明的这些和其它方面。
附图说明
现在将仅通过例子并参照附图来描述本发明的实施例，其中：
图1示意性示出在根据现有技术的用于在晶片上选择性地形成硅化物的方法的工艺流程中的基本步骤；
图2示意性示出在根据本发明第一示例实施例的用于在晶片上选择性地形成硅化物的方法的工艺流程中的基本步骤；
图3示意性示出在根据本发明第二示例实施例的用于在晶片上选择性地形成硅化物的方法的工艺流程中的基本步骤；和
图4示意性示出在根据本发明第三示例实施例的用于在晶片上选择性地形成硅化物的方法的工艺流程中的基本步骤。
具体实施方式
参照附图中的图1，如上面的简述，在根据现有技术的工艺流程中，首先(1)用SiProt层10覆盖整个晶片，该SiProt层10包括氧化物、氮化物或上面提及的与现有技术相关的类型的叠层。区域A将被硅化，区域B表示不想进行硅化的I/O晶体管。通过湿法蚀刻、干法蚀刻或两者的组合在要硅化的区域处对SiProt层10进行蚀刻(2)。实际上，要硅化的区域往往形成晶片表面的90％-99％左右。接下来，以任何适合的方法对晶片进行清洁，比如湿法蚀刻、干法蚀刻、化学蚀刻、反应蚀刻或物理蚀刻(溅射蚀刻)，并在整个晶片上沉积(3)金属层12。最后，执行(4)热处理(退火)来在未被SiProt层10保护的区域处产生硅化物14，并随后执行选择性的蚀刻处理来去除所有未反应的金属。
如上所述，在参照图1图解说明和描述的工艺流程中，在要硅化的区域中去除SiProt(由于缺陷和残留物)会使这些区域的Si表面劣化。这是需要很专门的清洁处理的原因，但由于不规则的硅化(穿刺，Spiking)导致结泄漏或硅化物侵蚀，因此仍然发生产量降低。
本发明通过首先执行金属沉积步骤，然后防止在预定位置处的金属形成硅化物并最后执行硅化步骤，克服了该缺陷。
参照附图中的图2，在根据本发明的第一示例实施例的方法中，首先(1)在整个晶片上沉积金属(例如Co、Ni、Ti等)层12(例如50-200埃)，既覆盖要硅化的区域(A)也覆盖不想硅化的区域(B)。接下来(2)，在金属层12上沉积硬掩模(例如氧化物/氮化物/碳化物)16，并形成图案来去除不想硅化的区域(B)中的硬掩模16。最后，在进行硅化退火以使得在其中保留了金属层并去除了所有未反应金属的区域中形成硅化物14(4)之前，通过湿法或干法蚀刻将金属层12形成图案，以便从不想硅化的区域中去除金属层并且从要硅化的区域(A)中去除硬掩模(3)。
因此，在提出的方法中，通过(优选地通过湿法蚀刻)去除非常薄(典型地在5到30nm之间)的金属层来形成SiProt图案。所提出的新工艺流程的主要优点之一是SiProt图案形成被限制在I/O晶体管区域(B)，这样对器件的总泄漏造成的影响很小(这是因为要硅化的区域往往形成晶片表面的90％-99％左右，而要保护的区域(输入/输出晶体管)往往仅形成大约1％-10％的晶片表面)。而且，受保护的区域不会遭受由现有技术的装置中与SiProt有关的缺陷而导致的任何硅化问题(即，穿刺和硅化侵蚀，它们都引起结泄漏增大)。
参照附图中的图3，在根据本发明第二示例实施例的方法中，以代表要硅化的区域A和不想硅化的区域B的两个传统结构(1)开始，首先，在整个晶片上再次沉积(2)金属层12(例如Co、Ni、Ti等)。接下来，在金属层12上沉积SiProt层10。SiProt层10可以包括氧化物、氮化物、硅化物或无定形碳层，或它们的组合。然后，优选地通过干法蚀刻将SiProt层10形成图案(4)，以便从要硅化的区域(A)去除SiProt层，留下覆盖原始隔离物的残留隔离物，并留下不想硅化的区域(B)中的SiProt层10。这里将意识到，SIProt层以及蚀刻不会与下面的硅和结相互反应，因此防止了该工艺过程中硅表面的劣化。
在接下来的步骤(5)，在整个晶片表面上沉积牺牲非晶硅盖层30。这种沉积发生在相对低的温度(例如PECVD，可能是基于SiH4的，或者如PVD之类其它技术，～100℃)。在步骤6，进行硅化退火工艺。金属与未掺杂非晶硅的反应速度比与掺杂晶体硅的反应速度快得多。在未保护区域(A，B，C)和SiProt保护区域(a，b，c)上形成了两种不同相和不同厚度的硅化物。可以通过对退火工艺的温度/时间设置来调节厚度和相的差异。在未保护区域和SiProt保护区域上形成不同厚度和相的硅化物使得可以通过未掺杂非晶硅的反应形成富含硅的稳定硅化物14(例如MSi2)以及通过掺杂晶体硅形成薄的、含硅少的相的硅化物(如MSi)或不稳定的固溶体硅化物(例如MxSiy)32。从而后面能够从受保护区域选择性地去除后一种硅化物。
最后，去除(7)硅盖层和SiProt层(在将无定形碳作为SiProt层的情况下，可以通过揭起(lift off)来去除)，留下未反应金属的区域12，然后将区域12以及薄的不稳定硅化物蚀刻掉(8)(例如通过湿法蚀刻)。
因此，通过在金属沉积步骤之后沉积SiProt层克服了上述与现有技术相关的缺点。因此，当(通过蚀刻)将SiProt层形成图案时，下面的硅不会劣化，即当没有残留物并且没有由于蚀刻或由于所需要的清洁工艺(典型地是溅射蚀刻)而引起的Si缺陷时，硅化得到改善，并减少了结泄漏，这使该工艺与超浅结(USJ)或SOI尤为兼容。所提出的方法的基本思想包括在金属层顶部沉积牺牲非晶Si盖层，并在该盖层与下面的金属之间布置SiProt层。牺牲Si盖层使得来自SD结的硅消耗减小，从而进一步增强与USJ和SOI的兼容性。
在另一个称为升高式硅化(elevated silicidation)的公知的工艺流程中，首先在在提高的温度(典型地高于600℃)下执行选择性外延硅生长工艺以在源极和漏极上生长额外的硅层。接着，在整个晶片上沉积金属层，并进行硅化退火从而在与硅层接触的金属区域处形成硅化物。然后选择性地蚀刻掉未反应的金属。然而，由于使用了高温，因此结的轮廓劣化，显然这是不期望的。另外，所需的选择性外延生长工艺不容易实现，这导致在隔离区域(隔离物/STI)上有发生短路的风险。
参照附图中的图4，根据本发明的第三示例实施例解决了这些附加的问题，并且尤其在没有与选择性外延硅生长相关的缺点的情况下实现了普通升高源-漏极(elevated source/drain)结构的一个特定有益效果，即减小了结的硅消耗。与根据本发明第一示例实施例的方法一样，以源-漏结构(1)开始，首先在整个晶片表面上沉积(2)金属层12。接着，在金属层12上沉积(3)电介质材料(氧化物或氮化物)的层18，下文将电介质材料层18称为硬掩模。然后，优选地使用(4)反向有源掩模(inverse active mask)22和用来表示无需硅化的有源区域的附加设计层以及干法蚀刻工艺(5)来将硬掩模18形成图案，干法蚀刻工艺从要硅化的区域中去除硬掩模，但留下了被保护的STI和原始隔离物上的残留隔离物。接着，在相对低的温度下沉积(6)非晶硅层24，并执行(7)硅化退火工艺，以便非晶硅层24与要硅化的区域中的金属12进行反应以在这些区域中形成硅化物14。最后，执行(8)未反应的硅、电介质和金属的选择性湿法蚀刻。
与传统的升高源-漏极结构(其中在金属沉积之前沉积牺牲硅(以提供不是来源于结的硅))不同，在上面描述的第三示例实施例中，在金属沉积之后沉积牺牲硅。
因为在相对低的温度下(例如，PECVD-150℃，PVD-100℃)沉积非晶硅层，所以不会有结劣化。另外，在硅化工艺期间大多数Si消耗来自于非晶硅盖层，而结区域仅仅消耗非常少量的硅，这是因为掺杂晶体硅与金属层的反应比未掺杂的非晶Si盖层与金属层的反应慢得多。第三示例实施例是上述第二示例实施例的扩展的、全面综合的版本，其中使用了特殊步骤从而使得在隔离区域(STI或LOCOS)上不会形成硅化物。
应注意，上述实施例说明而非限制本发明，所属领域技术人员将能设计许多不脱离由所附权利要求限定的本发明范围的可选的实施例。在权利要求中，置于括号中的任何参考符号不应理解为限制该权利要求。词语“包括”和“包含”之类不排除在任何权利要求或作为整体的说明书中列举的那些部件或步骤之外的部件或步骤存在。引用单个部件不排除多个这类部件的引用，反之亦然。在相互不同的从属权利要求中记载的特定措施这一简单事实并不表示不能使用这些措施的组合来获得有益效果。

Claims (4)

1.一种在半导体晶片上选择性地形成硅化物的方法，该半导体晶片包括要在其上形成硅化物的一个或多个第一区域(A)以及不想在其上形成硅化物的一个或多个第二区域(B)，所述方法包括：
a)在所述晶片上沉积金属层(12)来覆盖所述第一和第二区域(A，B)；
b)施加掩模层(10，22)来覆盖所述金属层(12)；和
c)执行硅化工艺；
其中使所述掩模层(10，22)形成图案以使得仅在所述一个或多个第一区域中的金属层暴露于所述硅化工艺，接下来，在执行硅化工艺之前沉积非晶硅盖层(30，24)来覆盖第一和第二区域。
2.如权利要求1所述的方法，其中通过干法蚀刻使所述掩模层(10)形成图案，并且在100-150℃的温度下沉积非晶硅盖层(30)。
3.如权利要求2所述的方法，其中在硅化工艺之后执行选择性蚀刻工艺，以便去除在所述一个或多个第二区域(B)上形成的不稳定硅化物或未反应的材料。
4.如权利要求1所述的方法，其中在施加所述掩模层(22)之前沉积电介质层(18)来覆盖所述金属层(12)，并且在去除电介质层(18)之前使所述掩模层(22)形成图案以暴露所述一个或多个第一区域(A)处的所述电介质层(18)。
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