CN101452959A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN101452959A
CN101452959A CNA2008101797542A CN200810179754A CN101452959A CN 101452959 A CN101452959 A CN 101452959A CN A2008101797542 A CNA2008101797542 A CN A2008101797542A CN 200810179754 A CN200810179754 A CN 200810179754A CN 101452959 A CN101452959 A CN 101452959A
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辛恩宗
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Abstract

本发明公开一种半导体器件及其制造方法。该半导体器件包括：栅极结构，该栅极结构包括：形成在半导体衬底上的氮氧化硅(SiON)层，形成在该氮氧化硅(SiON)层上的氮氧硅铪(HfSiON)层，形成在该氮氧硅铪(HfSiON)层上的多晶硅层，以及形成在该多晶硅层上的硅化物层；间隔件，位于该栅极结构的侧壁处；以及源极区和漏极区，置于该栅极结构的相对两侧。该半导体制造方法能够减小由铪(Hf)造成的钉扎。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件及其制造方法。
背景技术
为了增加晶体管的速度，对使用金属栅极和高K栅极绝缘材料以实现低栅极功函数(work function)和垂直电场的栅极结构已经进行了广泛地探讨和研究。
通常，将铪(Hf)基金属栅极氧化物用作高K栅极绝缘材料。在这种情况中，在栅电极和金属栅极氧化物之间的界面表面上，或在金属栅极氧化物和硅衬底之间的界面表面上，会发生Hf钉扎(pinning)，从而造成平带(flatband)漂移现象。
因此，可能会出现晶体管的阈值电压(Vth)漂移，并且会造成负偏压温度不稳定性(NBTI)这样的恶化。
发明内容
本发明提供一种半导体器件及其制造方法。
本发明实施例也提供一种半导体器件及其制造方法，其中该方法能够减小由铪(Hf)造成的钉扎。
根据特定实施例，该半导体器件包括：栅极结构，该栅极结构包括：形成在半导体衬底上的氮氧化硅(SiON)层，形成在该氮氧化硅(SiON)层上的氮氧硅铪(HfSiON)层，形成在该氮氧硅铪(HfSiON)层上的多晶硅层，以及形成在该多晶硅层上的硅化物层；间隔件，位于该栅极结构的侧壁处；以及源极区和漏极区，置于该栅极结构的相对两侧。
根据其它实施例，一种半导体器件的制造方法包括以下步骤：由以下步骤形成该栅极结构：在半导体衬底上形成氧化硅(SiOX)层，在该氧化硅(SiOX)层上形成硅酸铪(HfSiO)层，通过在包括该氧化硅(SiOX)层和该硅酸铪(HfSiO)层的该半导体衬底上实施氮等离子体工艺，形成氮氧化硅(SiON)层和氮氧硅铪(HfSiON)层，在该氮氧硅铪(HfSiON)层上形成多晶硅层，在该多晶硅层上生长硅锗(SiGe)层，以及图案化该氮氧化硅(SiON)层、该氮氧硅铪(HfSiON)层、该多晶硅层和该硅锗(SiGe)层；在该栅极结构的侧面形成间隔件以及源极区和漏极区；以及通过硅化该硅锗(SiGe)层形成栅电极。
根据其它实施例，一种半导体器件的制造方法，包括以下步骤：在半导体衬底上形成氧化硅层，在该氧化硅层上形成硅酸铪层，通过在该氧化硅层和该硅酸铪层上实施氮等离子体工艺，形成氮氧化硅层和氮氧硅铪层，在该氮氧硅铪层上形成多晶硅层，图案化该氮氧化硅层、该氮氧硅铪层和该多晶硅层；在该栅极结构的侧面形成间隔件；以及在该栅极结构的相对两侧的该半导体衬底中形成源极区和漏极区。
附图说明
图1至图7是示出了各种实施例的半导体器件及其制造方法的示意图。
具体实施方式
下文将参考随附附图详细描述根据本发明实施例的半导体器件及其制造方法。
图1至图7是示出了各种实施例的半导体器件及其制造方法的示意图。
参见图7，示例性半导体器件包括：半导体衬底100、隔离层200以及NMOS晶体管300和PMOS晶体管400，其中隔离层200确定半导体衬底100上的有源区，以及NMOS晶体管300和PMOS晶体管400形成在该有源区中。
隔离层200包括绝缘材料，并且可以通过浅沟槽隔离(STI)工艺和/或局部硅氧化(LOCOS)工艺形成该隔离层200。
半导体衬底100包括P阱区110和N阱区120，其中P阱区110掺杂有P型杂质，以及N阱区120掺杂有N型杂质。
NMOS晶体管300形成在P阱区110上。NMOS晶体管300包括栅极结构360、间隔件370以及源极/漏极区380，其中间隔件370形成在栅极结构360的侧壁处，以及源极/漏极区380形成在设置于栅极结构360的相对两侧的有源区中。注入氟的含氟层390可以形成在栅极结构360下面的沟道区中。
同时，栅极结构360包括氮氧化硅(SiON)层310、第一氮氧硅铪(HfSiON)层320、第二HfSiON层330、多晶硅层340、以及硅化物层350。
第二HfSiON层330具有的铪(Hf)含量小于第一HfSiON层320具有的铪(Hf)含量，并且多晶硅层340可以包括氟离子。
注入氟离子的多晶硅层340防止由第一HfSiON层320和第二HfSiON层330造成的Hf钉扎。
硅化物层350可以具有完全硅化的镍(Ni FUSI)结构。由于上述的NiFUSI结构具有低功函数特征，因此Ni FUSI结构可以防止电子和/或空穴迁移率的恶化。
尽管未在图中示出，但硅化物可以形成在源极/漏极区380上。
同样地，PMOS晶体管400形成在N阱区120上。PMOS晶体管400包括栅极结构460、间隔件470以及源极/漏极区480，其中间隔件470形成在栅极结构460的侧壁处，以及源极/漏极区480形成在位于栅极结构460的相对两侧的有源区中。此外，注入氟的含氟层390可以形成在栅极结构460下面的沟道区中。
同时，栅极结构460包括SiON层410、第一HfSiON层420、第二HfSiON层430、多晶硅层440、以及硅化物层450。
第二HfSiON层430具有的Hf含量小于第一HfSiON层320具有的Hf含量，并且多晶硅层440可以包括氟离子。
注入氟离子的多晶硅层440防止由第一HfSiON层420和第二HfSiON层430造成的Hf钉扎。
硅化物层450可以具有Ni FUSI结构。由于上述的Ni FUSI结构具有低功函数特征，因此Ni FUSI结构可以防止电子和/或空穴迁移率的恶化。
尽管未在图中示出，但硅化物可以形成在源极/漏极区480上。
同时，在特定实施例中，栅极结构360和460包括SiON层310和410、第一HfSiON层320和420、第二HfSiON层330和430、多晶硅层340和440、以及硅化物层350和450。可以选择性地形成第二HfSiON层330和430和多晶硅层340和440。
例如，根据另一个实施例，栅极结构360和460可以包括SiON层310和410、第一HfSiON层320和420、多晶硅层340和440、以及硅化物层350和450。
根据又一个实施例，栅极结构360和460可以包括SiON层310和410、第一HfSiON层320和420、第二HfSiON层330和430、以及硅化物层350和450。
下文将参考图1至图7详细描述根据本发明第一实施例的示例性半导体器件及其制造方法。
参见图1，在半导体衬底100上形成隔离层200以确定有源区。可以通过浅沟槽隔离(STI)工艺和/或局部硅氧化(LOCOS)工艺形成隔离层200。
然后，选择性地注入P型杂质和N型杂质，从而形成P阱区110和N阱区120。
此时，可以使用P阱区110和N阱区120将氟离子注入半导体衬底100的表面中，从而可以形成含氟层390。可以选择性地形成含氟层390(例如，在注入之前，先掩蔽非注入区域)。通过用于P阱区110和N阱区120的阱退火工艺，活化含氟层390的氟。
含氟层390可以防止在HfSiON层的Hf和半导体衬底100的Si晶格(lattice)之间的钉扎。
参见图2，通过热氧化在半导体衬底100上形成二氧化硅层(SiO2)。此后，先通过金属有机化学气相沉积(MOCVD)，在热的SiO2层上沉积含有Hf比率为40％至60％的HfSiO；然后，再通过MOCVD，沉积含有Hf比率为5％至10％的HfSiO。
然后，通过远距离等离子体氮化(RPN)工艺，使氮气(N2)与HfSiO和SiO2反应(例如在温度为800℃至850℃条件下)，从而在半导体衬底100上形成SiON层510、第一HfSiON层520、以及第二HfSiON层530。
第二HfSiON层530具有的Hf含量小于第一HfSiON层520具有的Hf含量，从而减小由Hf造成的Si晶格钉扎。
在进行等离子体氮化(例如RPN)工艺期间，注入氮离子，从而提高在半导体衬底100和绝缘层结构之间的接触表面的任何不良的界面粗糙，其中该绝缘层结构包括SiON层510、第一HfSiON层520、以及第二HfSiON层530。
参见图3，通过低压CVD(LP-CVD)在半导体衬底100上形成多晶硅层540，其中半导体衬底100包括SiON层510、第一HfSiON层520、以及第二HfSiON层530，并且多晶硅层540的厚度可以为70nm至100nm，以及可以将氟离子注入多晶硅层540中。
注入氟离子的多晶硅层540防止由第一HfSiON层520和第二HfSiON层530的Hf造成的Hf钉扎。
参见图4，在多晶硅层540上形成栅电极层550。此时，栅电极层550的厚度可以为150nm至200nm，并且可以通过外延生长硅锗(SiGe)形成栅电极层550。包括锗(Ge)的硅(Si)结构有助于选择性地形成Ni FUSI结构。
参见图5，图案化SiON层510、第一HfSiON层520、第二HfSiON层530、多晶硅层540、以及栅电极层550，从而形成栅极结构360和460，其中栅极结构360和460构成NMOS晶体管300和PMOS晶体管400。
然后，注入诸如铟(In)、锑(Sb)、砷(As)、或氟化硼(BF)等杂质，以形成轻掺杂漏极(LDD)区(未示出)，并且形成间隔件370和470(通常，通过毯覆沉积一层或多层介电层，诸如二氧化硅层或氮化硅层、二氧化硅上氮化硅双层、或二氧化硅/氮化硅/二氧化硅三层等，随后进行各向异性蚀刻而形成)。
然后，使用间隔件370和470作为离子注入掩模，注入大量杂质(已在上文中列出)，从而使源极/漏极区380和480与LDD区一起形成。
参见图6，在半导体衬底100上形成缓冲氧化物层600，并且在该缓冲氧化物层600上实施化学机械抛光(CMP)工艺，从而暴露栅极结构360和460的上部。
然后，在半导体衬底100上部之上涂覆镍(Ni)700之后，在温度为400℃的条件下，在合成结构上实施初级热处理，其中半导体衬底100包括栅极结构360和460以及缓冲氧化物层600。此时，栅电极层350和450的Si(可选择地，还有Ge)与Ni反应，以形成局部硅化物层。
此后，除去未与栅电极层350和450反应的部分Ni以及缓冲氧化物层600。随后，在合成结构上实施次级热处理，从而形成Ni FUSI结构。
因此，可以制造如图7所示的半导体器件。
尽管未在图中示出，但硅化物可以形成在如图7所示的源极/漏极区380和480上。
此外，根据不同实施例，尽管硅化物层可以包括硅化镍(Ni)，但钛(Ti)、钽(Ta)、钴(Co)、以及铂(Pt)中的至少之一可用于替代Ni，以形成金属硅化物层。
说明书中所涉及的“一实施例”、“实施例”、“示例性实施例”等，其含义是结合实施例描述的特定特征、结构、或特性均包括在本发明的至少一个实施例中。说明书中出现于各处的这些短语并不一定都涉及同一个实施例。此外，当结合任何实施例描述特定特征、结构或特性时，都认为其落在本领域技术人员结合其它实施例就可以实现这些特征、结构或特性的范围内。
尽管对实施例的描述中结合了其中多个示例性实施例，但可以理解的是本领域技术人员完全可以推导出许多其它变化和实施例，并落入本公开内容的原理的精神和范围之内。尤其是，可以在该公开、附图和所附权利要求的范围内对组件和/或附件组合设置中的排列进行多种变化和改进。除组件和/或排列的变化和改进之外，对于本领域技术人员而言，其它可选择的应用也是显而易见的。

Claims (20)

1.一种半导体器件，包括：
栅极结构，其包括：位于半导体衬底上的氮氧化硅层，位于该氮氧化硅层上的氮氧硅铪层，位于该氮氧硅铪层上的多晶硅层，以及位于该多晶硅层上的硅化物层；
间隔件，位于该栅极结构的侧壁处；以及
源极区和漏极区，置于该栅极结构的相对两侧。
2.根据权利要求1所述的半导体器件，其中该氮氧硅铪层包括：第一氮氧硅铪层和第二氮氧硅铪层，其中该第二氮氧硅铪层位于该第一氮氧硅铪层上，并且该第二氮氧硅铪层的铪含量小于该第一氮氧硅铪层的铪含量。
3.根据权利要求2所述的半导体器件，其中该第一氮氧硅铪层的铪与氮的键合率为40％至60％，并且该第二氮氧硅铪层的铪与氮的键合率为5％至10％。
4.根据权利要求1所述的半导体器件，其中该多晶硅层包括氟离子。
5.根据权利要求1所述的半导体器件，还包括：氟化层，该氟化层包括注入的氟离子，且该氟化层位于该源极区和漏极区之间。
6.根据权利要求1所述的半导体器件，其中该硅化物层包括硅化镍。
7.根据权利要求1所述的半导体器件，还包括硅锗层，该硅锗层位于该多晶硅层上。
8.根据权利要求1所述的半导体器件，其中该硅化物层位于该硅锗层上。
9.一种半导体器件的制造方法，该方法包括以下步骤：
由以下步骤形成栅极结构：在半导体衬底上形成氧化硅层，在该氧化硅层上形成硅酸铪层，通过在包括该氧化硅层和该硅酸铪层的该半导体衬底上实施氮等离子体工艺，形成氮氧化硅层和氮氧硅铪层，在该氮氧硅铪层上形成多晶硅层，在该多晶硅层上生长硅锗层，以及图案化该氮氧化硅层、该氮氧硅铪层、该多晶硅层和该硅锗层；
在该栅极结构的侧面形成间隔件以及源极区和漏极区；以及
通过硅化该硅锗层，形成栅电极。
10.根据权利要求9所述的方法，其中形成该栅电极的步骤包括：
在该半导体衬底上形成缓冲氧化物层，并且通过化学机械抛光工艺暴露该硅锗层；
在该缓冲氧化物层和该硅锗层上涂覆金属；
在涂覆有该金属的该半导体衬底上实施初级热处理工艺；以及
除去未与该硅锗层反应而残留的部分该金属和除去该缓冲氧化物层，并且在合成结构上实施次级热处理工艺。
11.根据权利要求9所述的方法，还包括以下步骤：在该半导体衬底上形成该氧化硅层之前，将氟离子注入该半导体衬底中。
12.根据权利要求9所述的方法，其中形成该硅酸铪层的步骤包括：形成第一硅酸铪层，并且在该第一硅酸铪层上形成第二硅酸铪层，该第二硅酸铪层的铪含量小于该第一硅酸铪层的铪含量。
13.根据权利要求12所述的方法，其中该第一硅酸铪层的铪的比率为40％至60％，并且该第二硅酸铪层的铪的比率为5％至10％。
14.根据权利要求9所述的方法，还包括以下步骤：将氟离子注入该多晶硅层。
15.一种半导体器件的制造方法，包括以下步骤：
在半导体衬底上形成氧化硅层，
在该氧化硅层上形成硅酸铪层，
通过在该氧化硅层和该硅酸铪层上实施氮等离子体工艺，形成氮氧化硅层和氮氧硅铪层，
在该氮氧硅铪层上形成多晶硅层，
图案化该氮氧化硅层、该氮氧硅铪层和该多晶硅层；
在该栅极结构的侧面形成间隔件；以及
在该栅极结构的相对两侧的该半导体衬底中形成源极区和漏极区。
16.根据权利要求15所述的方法，还包括以下步骤：在该多晶硅层上生长硅锗层，其中将该硅锗层与该氮氧化硅层、该氮氧硅铪层和该多晶硅层一起图案化。
17.根据权利要求16所述的方法，还包括以下步骤：硅化该硅锗层，以形成硅化物层。
18.根据权利要求17所述的方法，其中硅化该硅锗层的步骤包括：
在该半导体衬底上形成缓冲氧化物层；
化学机械抛光该缓冲氧化物层，以暴露该硅锗层；
在该缓冲氧化物层和该硅锗层上涂覆金属；
加热涂覆有该金属的该半导体衬底，以形成金属硅化物；以及
除去该金属的未反应部分。
19.根据权利要求18所述的方法，还包括以下步骤：除去该金属的未反应部分之后，加热合成结构。
20.根据权利要求15所述的方法，其中形成该硅酸铪层的步骤包括：形成第一硅酸铪层，并且在该第一硅酸铪层上形成第二硅酸铪层，该第二硅酸铪层的铪的含量小于该第一硅酸铪层的铪的含量。
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