CN101409279B - 包含与芯片背面相连的电子元件的半导体器件 - Google Patents

包含与芯片背面相连的电子元件的半导体器件 Download PDF

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CN101409279B
CN101409279B CN2008102115517A CN200810211551A CN101409279B CN 101409279 B CN101409279 B CN 101409279B CN 2008102115517 A CN2008102115517 A CN 2008102115517A CN 200810211551 A CN200810211551 A CN 200810211551A CN 101409279 B CN101409279 B CN 101409279B
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chip
electronic component
plate
back side
substrate
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CN101409279A (zh
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米夏埃尔·鲍尔
爱德华·菲尔古特
约阿希姆·马勒
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Infineon Technologies AG
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Abstract

本发明涉及一种包含与芯片背面相连的电子元件的半导体器件，其中提供了一种半导体封装，其包括：基片；包含第一表面和与第一表面相对的背面的至少一个芯片，该第一表面与基片电连接；与至少一个芯片的背面相连的导电层；以及与导电层相连并与基片电通信连接的至少一个电子元件。

Description

包含与芯片背面相连的电子元件的半导体器件
技术领域
本发明涉及一种半导体器件，尤其是一种包含有与芯片背面相连的电子元件的半导体器件。
背景技术
小型多功能电子器件的市场需求推动了半导体器件、封装以及最近的布置在芯片上的整个系统的发展。许多电子器件如移动电话采用多种特殊设计的电子元件。然而，电子器件内的可用空间是有限的，尤其是当电子器件制造得较小时。
大部分半导体封装方法提供与载体相连的芯片以及邻近该芯片与载体相连的一个或多个电子元件。这些电子元件中的一些通常由终端用户消费者依据终端应用以特定方式调谐。因此，封装制造商经常需要提供多种封装，每种都配置为由消费者依据他们需要的终端用途来封装。这些特殊设计的封装限制了封装制造商提供一套对多个消费者有用的灵活且包含广泛的封装方法。封装制造商更愿意制造具有规模经济的、适于满足许多消费者的个别需求的封装。
这些高级电子器件的制造商和消费者都想要尺寸减小而功能性增强的器件。
由于这些原因以及其它原因，所以需要做出本发明。
发明内容
本发明的一个方面提供一种半导体封装，该半导体封装包括：基片；包含第一表面以及与第一表面相对的背面的至少一个芯片，该第一表面与基片电连接；与至少一个芯片的背面相连的导电层；以及与导电层相连并与基片电通信连接的至少一个电子元件。
附图说明
包含了附图以提供对实施例的进一步理解，这些附图并入本说明书并构成了本说明书的一部分。附图示出了实施例，并和说明一起用于阐述实施例的原理。由于参考下面的详细说明可以更好地理解实施例，因此其他实施例以及实施例的许多设想的优点将很容易明白。附图的元件没有必要相对于彼此成比例。相似的参考数字表示相应的类似部件。
图1是依据一个实施例的包含与载体相连的芯片以及与芯片背面相连的电子元件的半导体封装的剖面图。
图2A和图2B是构造为将电子元件连接至图1所示的芯片背面的导电多层结构的两个实施例的剖面图。
图3是依据一个实施例的包含与载体相连的多个芯片的半导体封装的剖视图，其中，每个芯片均包含与芯片的背面相连的电子元件。
图4是依据一个实施例的包含与载体相连的多芯片、与含通孔的板相连的多个电子元件的半导体封装的剖面图，其中，该板与芯片的背面相连。
图5是依据一个实施例的包含与载体相连的多个芯片、与含通孔的板相连的多个电子元件的半导体封装的剖面图，其中，该板与每个芯片的背面相连。
图6A是依据一个实施例的构造为连接至芯片组件的电子元件组件的分解侧视图。
图6B是图6A所示的与图6A所示的芯片组件相连的电子元件组件的剖面图。
图7是依据一个实施例的包含与转接板相连的芯片以及与芯片背面相连的多个电子元件的嵌入式晶圆级封装的剖面图。
图8是依据一个实施例的包含与转接板相连的芯片以及与连接到芯片背面的板相连的多个电子元件的嵌入式晶圆级封装的剖面图。
具体实施方式
在下面详细描述中，参考构成本说明书的一部分的附图，其中，示出了可以实施本发明的具体实施例。在这一方面，诸如“顶”、“底”、“前”、“后”、“前导”、“尾随”等方向性术语参考所描述的附图的方向来使用。由于这些实施例的组件可以在许多不同方向放置，所以方向性术语仅用于说明的目的，而没有任何限制的意思。应该理解的是，在不背离本发明的范围的条件下，可以使用其它实施例，并且可以进行结构或逻辑改变。所以，下面的详细描述不应被理解为限制性的意思，并且本发明的范围由所附的权利要求限定。
应该理解的是，如果没有其它特别注明，这里描述的不同示例性实施例的特征可以彼此结合。
如本说明书中所使用的，术语“相连的”和/或“电连接的”并不意味着元件必须直接相连在一起；在“相连的”和/或“电连接”的元件之间可以设置有插入元件。
实施例提供了电子元件的集成，这些电子元件可以掩埋在半导体封装内以开辟空间用于在半导体封装的载体/基片之上安装其它元件。某些实施例提供了与芯片背面相连的无源去耦件，其中这些件具有低寄生电感并适用于高频或高速电路。
下面描述的实施例提供具有垂直堆叠的与芯片背面相连的电子元件的通用半导体封装方法。一个或多个芯片与封装的载体相连，并且一个或多个电子元件与芯片背面相连。由于电子元件与芯片背面相连而不是与芯片并排，因此节省了载体上的空间以用于其它元件或其它布线结构。电子元件以提高封装设计功能性的方式与芯片背面相连并与载体电通信连接。
不同的实施例提供了与分开的板相连的电子元件。在装配到芯片背面之前可以对电子元件/板的性能进行功能测试。如此，与芯片背面相连的电子元件在装配进封装之前经过质量检查，这提高了封装的良率。另外，将电子元件直接与板相连减少了助焊剂(solderflux)以及与助焊剂相关的对印刷电路板的污染。
下面描述的实施例提供具有构造为由制造商调谐并与芯片背面相连的电子元件。例如，与芯片背面相连的无源电子元件更靠近信号线附近，这使得能够对无源元件和芯片进行更精确的调谐。封装内的由制造商调谐的电子元件为终端用户/消费者提供完整的封装方法。由制造商调谐的电子元件使制造商能够为各种终端用户消费者提供更灵活、通用的封装方法。下面描述的半导体封装容纳有包括引线框架、再分配层、电路板和嵌入式晶圆级器件在内的任何形式的转接板结构。
图1是依据一个实施例的半导体封装20的剖面图。半导体封装20包括：基片22；具有构造为与基片22相连的第一表面26以及与第一表面26相对的背侧面28的芯片24；与芯片24的背侧面28相连的第一电子元件30和第二电子元件32；以及沉积在芯片24上方、电子元件30、32上方和基片22的一部分上方的封装材料34。
在一个实施例中，基片22包括构造为与另一器件(如印刷电路板)相连的第一表面40、以及与第一表面40相对的第二表面42。在一个实施例中，基片22包括连通在第一表面40和第二表面42之间的导电盘44。在一个实施例中，芯片24的第一表面26限定芯片24的有源区域，并且芯片24是通过一个或多个焊料凸块46安装在导电盘44上的倒装芯片。在这个实施例中，基片22是构造为将芯片24以倒装芯片方式安装在导电盘44上的载体。在另一个实施例中，基片22包括任何合适的转接板(或者称为中介层interposer)例如引线框架、电路板、嵌入式晶圆级器件的再分配层、或其它合适的载体。
在一个实施例中，芯片24包括在第一表面26和背面28之间延伸并限定了从第一表面26至背面18的电性路径的一个或多个过孔50。在一个实施例中，过孔50包括延伸穿过芯片24的孔、引线孔或开口，这些孔构造为使得能够布线/连接至芯片24。芯片24通常包括存储芯片、逻辑芯片、半导体芯片，以及/或者其它合适的集成电路芯片。
在一个实施例中，电子元件30、32包括无源元件。合适的无源元件包括电阻器、电容器、电感器或具有特定电子特性而且不能执行电子指令的其它电子元件。在一个实施例中，电子元件30、32是有源元件，比如有源芯片或能够完成如执行电子指令等行为的其它逻辑器件。在一个实施例中，电子元件30、32中的一个是无源元件，并且电子元件30、32中的另一个是有源元件。
在一个实施例中，电子元件30、32通过导电层60与芯片24的背面28相连。在一个实施例中，导电层60沉积在芯片24的背面28上并填充过孔50以形成从电子元件30、32延伸穿过导电层60、穿过过孔50、越过凸块46并穿过导电盘44的电性路径。在一个实施例中，导电层60包括构造为将电子元件30、32连接至芯片24的背面28的金属化层或金属化多层。导电层60通过合适的沉积工艺沉积在芯片24的背面28上，合适的沉积工艺包括溅射、气相沉积、增强和/或辅助气相沉积、电(galvanic)沉积或其它合适的工艺。
在一个实施例中，导电层60沉积在芯片24的背面28上，并既为电子元件30、32提供了焊盘(pad)又为芯片24提供了整体电磁屏蔽。在一个实施例中，导电层60只沉积在芯片24的背面28的一部分(也就是少于全部)上。如此，就最小化了造成相对于芯片24电力短路的可能性。在另一个实施例中，导电层60以选择性地平衡芯片24的电压补偿的方式沉积在芯片24的整个背面28上。
在一个实施例中，封装材料34包括环氧树脂、树脂、聚合材料或其它适于在制造封装20时模制的合适电绝缘材料。
半导体封装20提供与芯片24的背面28相连的无源和/或有源的电子元件30、32。电子元件30、32更接近于通向芯片24的信号线，这使得可以在半导体封装20内更精确地调谐(tuning)元件30、32。
图2A是依据一个实施例的导电层60的剖面图。在一个实施例中，导电层60是多层结构，它包括构造为接触芯片24(图1)的背面28的第一层62、第二层64、第三层66以及构造为提供连接电子元件30、32的电连接表面的第四层68。在一个实施例中，第一层62是包括铝或其它构造为连接至芯片24的背面28的合适金属。在一个实施例中，第二层64包括钛，并且第三层66包括镍或比如镍钒(Ni-V)的含镍合成物。在一个实施例中，第四层68包括比如银、铜、或金的导电金属或其它合适的电连接层。
图2B是依据另一个实施例的电导层60的剖面图。在一个实施例中，电导层60包括含有第一层72、第二层74、第三层76、第四层78和第五层80的多层堆叠70。堆叠70中的其它合适层数也是可以接受的。通常，层72、74、76、78分别与如上所述的层62、64、66、68类似。在一个实施例中，层80是构造为最小化金属离子从层78进入电子元件30、32的移动的扩散阻挡层。例如，在一个实施例中，层78是比如银的金属，并且层80包括构造为提供阻挡银离子从层78移动到电子元件30、32中的扩散阻挡层的钛。在一个实施例中，层80包括钛、钛合金、或钛合成物，尽管用于扩散阻挡层80的其它合适形式也是可以接受的。
这里描述的实施例包括沉积在芯片24的背面28的层60，其中，层60完整地密封芯片24，以隔绝破坏性的电磁干扰并提供用于附着电子元件30、32的通信焊盘。
图3是依据另一个实施例的半导体封装100的剖面图。在一个实施例中，半导体封装100包括载体102、与载体102相连的第一芯片104和第二芯片106、与第一芯片104的背面110相连的第一电子元件108、以及与第二芯片106的背面114相连的第二电子元件112。在一个实施例中，芯片104包括与背面110相对的第一表面120，其中第一表面120是有源区域，并且芯片104通过凸块122以倒装芯片方式安装在载体102上，从而使得有源区域120面向载体102。芯片104、106的其它形式和其它安装形式也是可以接受的。
在一个实施例中，载体102包括构造为与另一器件(如印刷电路板)相连的第一表面130、与第一表面130相对的第二表面132、以及在第一表面130和第二表面132之间延伸的多个导电盘134。在一个实施例中，凸块122将芯片104、106电连接至载体102的盘134。
在一个实施例中，芯片104包括在背面110和第一表面120之间延伸的一个或多个过孔140，并且芯片106类似地包括延伸穿过芯片106的一个或多个过孔105。在一个实施例中，金属化层160沉积在芯片104的背面110上以及芯片106的背面114上。金属化层160包括如上面图2A和图2B中描述的金属化层，以及如下面描述的导电板。
半导体封装100提供与基片102相连的多个芯片104、106以及分别与芯片104、106的背面110、114相连的电子元件108、112。在一个实施例中，半导体封装100可选地包括沉积在芯片104、106上、电子元件108、112上以及基片102的一部分上的封装材料170。
图4是依据另一个实施例的半导体封装200的剖面图。在一个实施例中，半导体封装200包括转接板202或载体202、与载体202电连接的芯片204、构造为与芯片204的背面208电连接的板206、与板206相连的第一电子元件210、以及与板206相连的第二电子元件212。
转接板202或载体202与上述基片22类似，并且包括导电盘220。芯片204与上述芯片24(图1)类似并且包括有源芯片、逻辑芯片、或其它集成电路芯片。芯片204提供延伸穿过芯片204的过孔230或引线孔230。过孔230是构造为提供穿过芯片204的电通信路径而配置。在一个实施例中，芯片204通过凸块/连接件232与转接板202相连，并且电子元件210、212与导电盘220电通信连接。
板206被构造为支撑电子元件210、212并且提供电子元件210、212和芯片204之间的电连接。在一个实施例中，板206是限定垂直(如图4的方向)延伸穿过板206的一组通孔的直接构件板。在一个实施例中，导电材料(如焊糊或焊锡(solder)或其它金属层)沉积在板206上以形成穿过板206的电性路径，该路径适于将电子元件210、212与芯片204和转接板202的盘220电连接。
在一个实施例中，板206与芯片204的背面208相连，并且随后将电子元件210、212安装至板206。在一个示范性实施例中，电子元件210、212利用铜金属层直接铜结合到板206。在下面描述的另一个实施例中，首先将电子元件210、212安装至板206，测试功能和性能，随后将板206安装至芯片204的背面208。在任何情况下，半导体封装200包括以垂直方式与芯片204的背面208相连的多个电子元件210、212，这种方式使封装200能在载体202上提供用于其它元件的可用空间。
图5是依据另一个实施例的半导体封装300的剖面图。半导体封装300包括基片302、与基片302相连的第一芯片303和第二芯片304、与芯片303的背面307和芯片304的背面308相连的板306、以及与板306相连的多个电子元件310、312。
在一个实施例中，载体302包括构造为将封装300电连接至其它器件(如印刷电路板)的焊盘320。在一个实施例中，芯片303包括在背面307和有源表面331(或者称为主动表面)之间连通的过孔330，并且芯片303的有源表面331通过凸块332以倒装芯片方式安装至焊盘320。在一个实施例中，芯片304类似地以倒装芯片方式安装至焊盘320。将芯片303、304安装至载体302的其它方式也是可以接受的。
在一个实施例中，板306与上述图4中的板206类似，并且包括被制造为包括穿过板306延伸的多个通孔的直接构件板。在一个实施例中，电子元件310、312通过焊锡(solder)或其它导电材料与板306相连。焊锡或其它导电材料填充了形成在板306内的通孔，使得电子元件310、312穿过板306、穿过芯片303、304和凸块332与载体302的盘320电通信连接。
半导体封装300包括连接至板306的多个电子元件310、312，该板与芯片303、304的背面相连，从而使封装300能在载体302上提供用于其它元件的可用空间。
图6A依据一个实施例的半导体封装组件400的剖视图。半导体组件400包括构造为与芯片组件404相连的电子元件组件402。
在一个实施例中，电子元件组件402包括支撑一个或多个电子元件408a、408b、408c、408d的导电板406。在一个实施例中，电子元件408a-408d包括一个或多个无源元件和/或一个或多个有源元件。例如，在一个实施例中，电子元件408a是无源元件，并且电子元件408b是有源元件。电子元件408a-408d以这样的方式与板406电连接，该方式使得在将板406安装至芯片组件404之前，能够对电子元件组件402进行功能测试和/或质量检查。
在一个实施例中，芯片组件404包括载体412和至少一个限定了与载体412相连的芯片背面416的芯片414。在其它实施例中，多个这样的芯片414与载体412相连。在一个实施例中，载体412包括多个导电盘420，并且芯片414包括延伸穿过芯片414的厚度的多个过孔430。在一个实施例中，芯片414通过焊料凸块432与载体412相连，使得过孔430与盘420电连接。
在一个实施例中，在连接到芯片组件404之前，制造电子元件组件402并对其进行功能测试。例如，在一个实施例中，将电子元件408a-408d与板406相连并且对电子元件组件402进行功能测试以检验电子元件408a-408d的期望性能。从而，在制成组件402以完成半导体封装之前，验证了电子元件408a-408d并且保证了它们的性能。如此，增加了电子元件408a-408d的良率(yield)和由电子元件组件402制成的半导体封装的良率。
图6B是依据一个实施例的半导体封装450的剖面图。半导体封装450包括与芯片组件404相连的电子元件组件402，以及沉积在电子元件组件402和芯片组件404的一部分上的封装材料452。在一个实施例中，电子元件组件402在与芯片组件404相连之前进行电性功能测试和/或质量检查。在一个实施例中，封装材料452包括环氧树脂、树脂、聚合材料或其它合适的电绝缘材料。在一个实施例中，封装材料452是模制在电子元件组件402和芯片组件404的一部分上的环氧树脂。
图7是依据另一个实施例的半导体封装500的剖面图。半导体封装500包括转接板、与转接板502相连的芯片504、与芯片504的背面510相连的第一电子器件506和第二电子器件508、以及围绕着电子器件506、508和芯片504模制的材料512。
在一个实施例中，转接板502包括已经从载体系统(未显示)剥离的再分配层520，并且包括互联件522。在一个实施例中，再分配层520和互联件522结合以限定构造为连接到其它电子器件(比如印刷电路板)的球栅阵列。
在一个实施例中，芯片504包括从芯片504的背面延伸到芯片504的连接件侧532的过孔530。在一个实施例中，芯片504和材料512结合以限定嵌入式晶圆级球栅阵列芯片组件的一部分、或没有第一级互联件的晶圆级封装。例如，在一个实施例中，芯片504直接形成在转接板502上，使得芯片504和转接板502电连接并且没有结合第一级互联件的布线。在这点上，转接板502和芯片504提供了封装厚度T小于约200微米的“薄”晶圆级封装。例如，在一个实施例中，芯片504的厚度约为50微米，并且材料512沉积在芯片504和转接板502上，使得半导体封装500是厚度T小于约200微米的薄晶圆级封装。
在一个实施例中，封装500包括沉积在材料512上的可选硬化层534，该硬化层被构造为对薄晶圆级封装提供结构完整性。如此，尽管封装500通常是薄的并且适于低重量和高器件密度的应用，但硬化层534为封装500提供了合适的封装牢固级和耐用级。应该理解，硬化层534没必要按比例绘制。硬化层534包括环氧树脂、塑料、增强层和其它适当硬的材料。
在一个实施例中，电子元件506、508通过导电层540与芯片504的背面510相连。在一个实施例中，导电层540是金属化层。在另一个实施例中，导电层540是沉积在芯片504的背面510上的多层金属化涂层。如此，电子元件506、508与导电层540、过孔530、转接板502和互联件522电通信连接。从而，电子元件506、508通过电性路径与互联件522相连。
在一个实施例中，导电层540沉积在芯片背面510的仅一部分上，以使芯片背面510的不包括电子元件506、508的一部分的不期望电短路的可能性最小化。
图8是依据另一个实施例的嵌入式晶圆级封装600的剖面图。嵌入式晶圆级封装600包括转接板602、与转接板602相连的芯片604、与芯片604的背面608相连的板606、与板606相连的第一电子器件610和第二电子器件612、以及模制在电子元件610、612和芯片604上的材料614。
在一个实施例中，芯片604和转接板602是包括已经从载体体系(未显示)剥离(或者说去除接合)的再分配层620并且包括互联件622的晶圆级封装。在一个实施例中，再分配层620和互联件622结合以限定构造为连接至其它电子元件(如印刷电路板)的球栅阵列。
在一个实施例中，芯片604包括从芯片604的背面608延伸至互联件622的过孔630。与上述图7中的封装500类似，在一个实施例中，芯片604和材料614结合以限定嵌入式晶圆级球栅阵列芯片组件的一部分、或没有第一互联件的晶圆级封装。
在一个实施例中，封装600包括与上述硬化层534(图7)类似的硬化层。硬化层被构造为对薄晶圆级封装提供结构完整性。
在一个实施例中，电子元件610、612通过板606与芯片604的背面608相连。在一个实施例中，板606与板206(图4)类似并包括限定了适于将电子元件电连接至板606并将板606电连接至芯片604的多个通孔或引线孔的板。如此，电子元件610、612与板606相连并且与过孔630、转接板602和互联件622电通信连接，以和互联件622形成电性路径。
板606使得能够在封装600的最终组装之前对元件610、612进行电连接和功能测试。将元件610、612直接布置在板606上形成良好的电连接并在转接板602上为其它元件或其它引线规划留出空间。当元件610、612中的一个或多个包括无源元件时，无源元件与封装600的信号线更靠近地电连接，从而能够容易地调谐无源元件，以用于具体应用的功能。
尽管在此示出并描述了具体实施例，但是本领域普通技术人员应该理解的是，在不背离本发明的范围的条件下，各种可选和/或等同的实施方式可以代替所描述和示出的具体实施例。本申请旨在覆盖本文中所讨论的与芯片背面连接的电子元件的具体实施例的任何修改或变形。所以，本发明旨在仅由权利要求及其等同物限定。

Claims (17)

1.一种半导体封装，包含：
基片；
至少一个芯片，包含第一表面和与所述第一表面相对的背面，所述第一表面与所述基片电相连；所述第一表面是有源表面，所述芯片限定在所述第一表面和所述背面之间延伸的过孔，
与所述至少一个芯片的背面相连的导电层；
与所述导电层相连并与所述基片电通信连接的至少一个电子元件；其中至少一个电子元件安装到所述芯片的背面上；其中，所述导电层包括限定了通孔结构的板以及沉积在所述板的一部分上方和所述通孔的一部分中的金属层；所述金属层限定了从所述电子元件穿过所述板和至少一个过孔延伸至所述基片的电性路径。
2.根据权利要求1所述的半导体封装，其中，所述有源表面通过凸块以倒装芯片方式结合至所述基片，并且所述至少一个电子元件通过所述过孔和所述凸块与所述基片电通信连接。
3.根据权利要求1所述的半导体封装，其中，所述基片包括再分配层并且所述至少一个芯片包括与所述再分配层电相连的嵌入式芯片，所述芯片限定在所述第一表面和所述背面之间延伸的过孔，并且所述至少一个电子元件通过所述过孔与所述再分配层电通信连接。
4.根据权利要求1所述的半导体封装，其中，所述至少一个电子元件包括从由电阻器、电感器和电容器组成的组中选择的无源电子元件。
5.根据权利要求1所述的半导体封装，其中，所述至少一个电子元件包括有源电子元件。
6.根据权利要求1所述的半导体封装，其中，所述金属层包括铜并且所述至少一个电子元件直接铜结合至所述板。
7.一种半导体封装，包括：
限定了第一表面和第二表面的载体；
与所述载体相连的至少一个芯片；所述至少一个芯片包括第一表面、与所述第一表面相对的第二表面、形成第一表面和第二表面之间的在所述芯片中的第一过孔和第二过孔，所述第一表面与所述载体电相连；其中第一表面是有源表面；
与所述芯片的第二表面相连的结合层；所述结合层通过形成在所述芯片中的所述第一过孔和所述第二过孔中的至少一个与所述载体电相通；
与所述结合层相连的至少一个电子元件，所述结合层包括限定了通孔结构的板以及沉积在所述板的一部分上方和所述通孔的一部分中的金属层；所述金属层限定了从所述电子元件穿过所述板和所述芯片内的第一和第二过孔延伸至所述基片的电性路径；沉积在所述芯片和所述载体的第一表面上的封装材料。
8.根据权利要求7所述的半导体封装，其中，所述至少一个芯片包括沉积在所述第一表面上的金属凸块，所述金属凸块与所述载体的第一表面电相连。
9.根据权利要求7所述的半导体封装，其中所述载体包括含有电性互联件的薄膜并且所述至少一个芯片与所述电性互联件电相连。
10.一种电子器件，包含：
基片；
至少一个包括第一表面和与所述第一表面相对的背面的芯片；所述第一表面与所述基片电相连；其中第一表面是有源表面；所述芯片限定从第一侧延伸到背面的过孔；
将至少一个电子元件安装至所述芯片的所述背面上的装置，使得所述至少一个电子元件与所述基片电通信连接，其中用于将至少一个电子元件电连接至所述芯片的背面的装置包括限定了通孔结构的板以及沉积在所述板的一部分上方和所述通孔的一部分中的金属层；所述金属层限定了从所述电子元件穿过所述板和第一过孔和第二过孔延伸至所述基片的电性路径。
11.一种制造包括垂直堆叠元件的半导体封装的方法，所述方法包括：
提供基片；
提供包括第一表面和与所述第一表面相对的背面的至少一个芯片，所述第一表面与所述基片相连；所述第一表面是有源表面，所述芯片限定在所述第一表面和所述背面之间延伸的过孔，以及
将至少一个电子元件安装到所述芯片的背面上，其中所述至少一个电子元件与基片电通信连接；
其中，将至少一个电子元件安装包括：
将至少一个电子元件与限定了通孔结构的板相连；
对与所述板相连的所有电子元件进行功能测试；以及
将所述板与所述芯片的背面相连包括沉积金属层在所述板的一部分上方和所述通孔的一部分中并且限定了从所述至少一个电子元件穿过所述板和至少一个过孔延伸至所述基片的电性路径。
12.根据权利要求11所述的方法，其中，所述至少一个芯片通过金属凸块以倒装芯片方式与所述基片相连。
13.根据权利要求11所述的方法，其中，提供至少一个芯片包括将所述至少一个芯片以倒装芯片方式嵌入到载体基片中。
14.根据权利要求11所述的方法，其中，将至少一个电子元件与所述芯片的背面相连包括通过金属化层将无源电子元件和有源元件中的至少一个与所述芯片的背面相连。
15.一种制造包括垂直堆叠元件的半导体封装的方法，所述方法包括：
提供基片；
提供与所述基片电连接的至少一个芯片；所述至少一个芯片具有第一表面和与所述第一表面相对的背面，所述第一表面是有源表面并且所述第一表面与所述基片电相连；所述芯片限定在所述第一表面和所述背面之间延伸的过孔，
将至少一个电子元件与板电连接，所述板限定了通孔结构；
对与所述板相连的所有电子元件进行功能测试；
将所述板安装到所述芯片的背面上并与所述芯片的露出的背面相连，使得所述至少一个电子元件通过所述至少一个芯片的过孔和所述基片电通信连接，包括沉积金属层在所述板的一部分上方和所述通孔的一部分中并且限定了从至少一个电子元件穿过所述板和至少一个过孔延伸至所述基片的电性路径。
16.根据权利要求15所述的方法，其中，将至少一个电子元件与板电连接包括将至少一个无源电子元件与板电连接。
17.根据权利要求15所述的方法，其中，将至少一个电子元件与板电连接包括将至少一个半导体芯片与板电连接。
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