CN101404272A - 贴片式半导体元件及制备方法 - Google Patents
贴片式半导体元件及制备方法 Download PDFInfo
- Publication number
- CN101404272A CN101404272A CNA2008102004478A CN200810200447A CN101404272A CN 101404272 A CN101404272 A CN 101404272A CN A2008102004478 A CNA2008102004478 A CN A2008102004478A CN 200810200447 A CN200810200447 A CN 200810200447A CN 101404272 A CN101404272 A CN 101404272A
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- tablet
- solder
- welding
- conductor
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
Description
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNA2008102004478A CN101404272A (zh) | 2008-09-25 | 2008-09-25 | 贴片式半导体元件及制备方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNA2008102004478A CN101404272A (zh) | 2008-09-25 | 2008-09-25 | 贴片式半导体元件及制备方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN101404272A true CN101404272A (zh) | 2009-04-08 |
Family
ID=40538212
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA2008102004478A Pending CN101404272A (zh) | 2008-09-25 | 2008-09-25 | 贴片式半导体元件及制备方法 |
Country Status (1)
Country | Link |
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CN (1) | CN101404272A (zh) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102263037A (zh) * | 2011-07-09 | 2011-11-30 | 强茂电子(无锡)有限公司 | 表面贴装二极管框架成形及组装方法 |
TWI476887B (zh) * | 2011-07-11 | 2015-03-11 | ||
CN105449075A (zh) * | 2015-11-06 | 2016-03-30 | 常州志得电子有限公司 | 一种新型贴片二极管制造工艺及其专用焊接模具 |
CN105489488A (zh) * | 2015-11-26 | 2016-04-13 | 钟运辉 | 一种贴片式二极管以胶道为本体的制造方法 |
CN106328548A (zh) * | 2015-06-15 | 2017-01-11 | 苏州普福斯信息科技有限公司 | 晶圆印刷锡膏在二极管封装中的应用方法 |
CN108376714A (zh) * | 2018-03-01 | 2018-08-07 | 山东沂光集成电路有限公司 | 一种sma贴片二极管 |
-
2008
- 2008-09-25 CN CNA2008102004478A patent/CN101404272A/zh active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102263037A (zh) * | 2011-07-09 | 2011-11-30 | 强茂电子(无锡)有限公司 | 表面贴装二极管框架成形及组装方法 |
TWI476887B (zh) * | 2011-07-11 | 2015-03-11 | ||
CN106328548A (zh) * | 2015-06-15 | 2017-01-11 | 苏州普福斯信息科技有限公司 | 晶圆印刷锡膏在二极管封装中的应用方法 |
CN105449075A (zh) * | 2015-11-06 | 2016-03-30 | 常州志得电子有限公司 | 一种新型贴片二极管制造工艺及其专用焊接模具 |
CN105449075B (zh) * | 2015-11-06 | 2018-02-13 | 常州志得电子有限公司 | 一种新型贴片二极管制造工艺及其专用焊接模具 |
CN105489488A (zh) * | 2015-11-26 | 2016-04-13 | 钟运辉 | 一种贴片式二极管以胶道为本体的制造方法 |
CN108376714A (zh) * | 2018-03-01 | 2018-08-07 | 山东沂光集成电路有限公司 | 一种sma贴片二极管 |
CN108376714B (zh) * | 2018-03-01 | 2021-03-16 | 山东沂光集成电路有限公司 | 一种sma贴片二极管 |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: SHANGHAI JINKE SEMICONDUCTOR + EQUIPMENT CO., LTD. Free format text: FORMER OWNER: LIN MAOCHANG Effective date: 20110701 |
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C41 | Transfer of patent application or patent right or utility model | ||
COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201102 NO. 280, YANGGUANG GARDEN, CHANGXI ROAD, XINQIAO TOWN, SONGJIANG DISTRICT, SHANGHAI TO: 201108 NO. 135 (AREA B, BUILDING 1), LANE 1421, ZHUANXING ROAD, MINHANG DISTRICT, SHANGHAI |
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TA01 | Transfer of patent application right |
Effective date of registration: 20110701 Address after: 201108 Shanghai city Minhang District Zhuan Hing Road 1421 Lane 135 (1 B) Applicant after: Shanghai Jinke Semiconductor & Equipment Co.,Ltd. Address before: 201102 Shanghai, new town, West Garden Road, No. sunshine garden, No. 280 Applicant before: Lin Maochang |
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C12 | Rejection of a patent application after its publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20090408 |