CN201853700U - 矩阵式dip引线框架及该框架的ic封装件 - Google Patents
矩阵式dip引线框架及该框架的ic封装件 Download PDFInfo
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Abstract
一种矩阵式DIP引线框架,及基于该框架的IC封装件,其矩阵式DIP引线框架由框架及设在框架内的若干个单元框架组成,所述单元框架在所述框架上呈矩阵式分布且行数为奇数行,其中第2n-1行与第2n行的相邻单元框架的基岛通过连接条与所述框架边框相连,第2n-1行与第2n行的相邻单元框架的外引线脚交错排列,并通过栅条与所述框架边框连接。本实用新型提高了框架材料的利用率,且结构简单合理,具有成本低、节能减排等优点,广泛应用于LED灯管、电脑接口类型、供应电源模块、网络变压器、DIP开关、压力传感器、方便实现PCB板的穿孔焊接,及标准逻辑IC、存储器LSI等领域。
Description
技术领域
本实用新型涉及半导体封装的DIP引线框架、基于该引线框架的IC芯片封装件。
背景技术
长期以来,DIP系列产品封装制造一直受制于早期80年代开发出来的引线框架模式,当时因受引线框架压延铜箔制造技术、冲压模具及冲压技术的影响,封装方面受塑封模具、电镀选镀技术、切筋成形模具技术、上芯/压焊设备的识别精度和工作窗口范围等条件的制约,引线框架一般设计在10mm~30mm以内的宽度,呈双排或单排设计,每条10~20个单元不等。这种框架采用传统塑封模具,挂镀线电镀,手动切筋成型。这样的生产方式不仅生产效率低,而且使用传统塑封模具、挂镀线电镀、手动切筋成形模具配置加工产品时安全风险大,并且产品外形尺寸一致性差,封装成品率低,产品的质量靠多配检验员来把关,导致生产成本高、效率低。
经过20多年的发展,上述材料制造技术和生产设备配套技术、封装生产的生产制造技术和封装应用技术及其标准化程度都发生了巨大的变化。单条框架可以做到70mm~80mm宽,若设计成多排,可数倍于现有框架(单/双排)数量,对引线框架制造厂来说可提高材料的利用率。
由于目前单/双排DIP系列产品属人员密集型封装产品,存在生产效率低、材料利用率低、加工过程错误率高、使用设备多、导致占地面积大、能源消耗大、DIP手动加工模具安全风险大等问题。
目前集成电路引线框架上的单元框架呈单行分布,各单元框架两侧的外引脚与基岛分别连在两侧框架边框上。由于集成电路技术的进步,电子产品层次与功能提升趋向多功能化、高速化、大容量化、高密度化、轻量化。因此许多新颖的载体结构技术与材料被开发出来,由于集成电路体积减小的同时需要增加集成电路模块的数量,就需要进一步减小集成电路封装模块的体积,即缩小集成电路封装的体积。因此,引线框架体积势必也要求缩小。
发明内容
本实用新型的目的之一在于提供一种矩阵式DIP引线框架;
目的之二在于提供基于所述矩阵式DIP引线框架的IC封装件;
从而达到降低框架材料的消耗和提高塑封料利用率,提高生产效率和产品质量,减少错误率、降低安全风险,是一种降低成本、节能减排的有效途径。
本实用新型是这样实现的:一种矩阵式DIP引线框架,由框架及设在框架内的若干个单元框架组成,所述单元框架在所述框架上呈矩阵式分布且行数为奇数行,其中第2n-1行与第2n行的相邻单元框架的基岛通过连接条与所述框架边框相连,第2n-1行与第2n行的相邻单元框架的外引线脚交错排列,并通过栅条与所述框架边框连接。
所述单元框架投入和产出效益对比分析为5行是最优。
一种双芯片IC封装件,包括所述单元框架上的载体及该载体堆叠放置的第一、第二芯片,具体为:该载体上先置第一IC芯片,该第一IC芯片上的焊盘通过键合线与内引脚相连,之后,第一IC芯片上再置第二IC芯片,第一、第二IC芯片通过铜或金焊线键合相连,采用铜或金线通过球焊把第二IC芯片和单元框架的引线脚相连,最后,塑封体覆盖了第一、第二IC芯片键合金或铜线及单元框架的引线脚而构成了电路整体。
本实用新型由于相邻单元框架的相邻引脚采用内交错型设计,框架尺寸控制在255mm×80mm以内,以DIP8L-5P为例,可使相邻单元在X方向的步距只为13.716mm,而现有的单排或双排引线框架的相邻框架的引脚是平行相连设计,以DIP8L-2P为例,其相邻单元在X方向的步距为18.288mm,DIP8L-5P步距比DIP8L-2P减少了4.572mm,提高了框架材料的利用率。与现有双排框架相比,引线框架材料利用率提高了26.93%(见表1);
表 1 DIP8L-5P与DIP8L-2P框架消耗对比
项目 | 每条框架尺寸(mm) | 平均每只面积(mm)2 | 面积比(%) |
DIP8L-2P | 182.88×24.638 | 225.8 | S2p/S5p: 136.36 |
DIP8L-5P | 251.3076×59.436 | 165 | S5p/S2p: 73.07 |
本发明的矩阵式DIP引线框架的结构使得生产配置方案更加优化,可采用MGP塑封模具、自动排片机和冲流道机,自动切筋成形系统(切筋、成形、分离各一副模具),高速线电镀线电镀,以DIP8L为例,5排框架的生产效率是双排框架的2.25倍(见表2),节约塑封料42.26%(见表3)。
表 2 DIP8L-5P与DIP8L-2P塑封生产效率对比
项目 | 每模数量(只) | 每天模数(次) | 封装数量(只) | 生产效率对比(%) |
DIP8L-2P | 320 | 400 | 128000 | S2p/S5p: 56.14 |
DIP8L-5P | 720 | 400 | 288000 | S5p/S2p: 2.25 |
表 3 DIP8L-5P与DIP8L-2P塑封料消耗对比
项目 | 每模数量只 | 重量×块数g | 平均每只数量g/只 | 每只用量比(%) |
DIP8L-2P | 320 | 80×3 | 0.75 | C2P/C5P:173.2 |
DIP8L-5P | 720 | 6.5×48 | 0.433 | C5P /C2P:55.73 |
本实用新型矩阵式DIP引线框架的结构可选用国产品牌普通材料和环保材料的粘片胶、塑封料,可实现低成本材料的选择应用及以铜线键合工艺为主,金线键合为辅的低成本生产方案和工艺技术。
本实用新型结构简单合理,具有成本低、节能减排等优点,广泛应用于LED灯管、电脑接口类型、供应电源模块、网络变压器、DIP开关、压力传感器、方便实现PCB板的穿孔焊接,及标准逻辑IC、存储器LSI等领域。
附图说明
图1是本实用新型的矩阵式DIP引线框架结构示意图;
图2是图1中的I放大图,为相邻封装单元框架单载体结构示意图;
图3是图1中的I放大图,为相邻封装单元框架双载体结构示意图;
图4是本实用新型单载体双芯片平面封装件剖面示意图;
图5是本实用新型双载体双芯片平面封装件剖面示意图;
图6是本实用新型双芯片堆叠封装件剖面示意图。
具体实施方式
下面结合附图对本实用新型作进一步的说明。
实施例1,参照图1、图2,一种单载体矩阵式DIP引线框架,其单元框架是单载体结构且行数为奇数行,其中第2n-1行与第2n行的相邻单元框架的基岛通过连接条18与所述框架边框相连,第2n-1行与第2n行的相邻单元框架的外引线脚交错排列,并通过栅条19与所述框架边框连接。例如:框架A单元和框架B单元为相邻的两个单元框架,其中B8夹在A1、A2引线脚之间,A2夹在B8和B7引线脚之间,B7夹在A2和A3引线脚之间,A3夹在B7和B6引线脚之间,B6夹在A3和A4引线脚之间,A4夹在B6和B5引线脚之间,其它依次类推。
实施例2,参照图1、图3,一种双载体矩阵式DIP引线框架,其单元框架是双载体结构且行数为奇数行,即每个单元框架有2个载体;其中单元框架A的引脚A7、A8与载体Z2相连、引脚A3与载体Z1相连,相邻单元框架B的引脚B7和B8与载体Z4相连、引脚B3与载体Z3相连接;其中第2n-1行与第2n行的相邻单元框架的基岛通过连接条18与所述框架边框相连,第2n-1行与第2n行的相邻单元框架的外引线脚交错排列,并通过栅条19与所述框架边框连接。例如:单元框架A和单元框架B为相邻的两个封装单元,其中B8夹在A1、A2引线脚之间,A2夹在B8和B7引线脚之间,B7夹在A2和A3引线脚之间,A3夹在B7和B6引线脚之间,B6夹在A3和A4引线脚之间,A4夹在B6和B5引线脚之间,其它依次类推。并且根据需要还有更多结构的异型结构框架。
实施例3,参照图1、图2、图4,一种基于实施例1的单元框架的双芯片IC封装件,包括所述单元框架上的载体1,该单元框架的载体1上并行放置第一、第二IC芯片11、12,该第一IC芯片11和第二IC芯片12上的焊盘上先各预植一个金线或铜线焊球10,然后用金线或铜线在第一IC芯片11的金线或铜线球10上堆叠金线或铜线键合球,拱丝拉弧在第二IC芯片12上的焊盘的金或铜球上堆叠金或铜键合球,形成键合球20,该键合球20使第一、第二IC芯片11、12相连;所述第一、第二IC芯片11、12的外焊盘通过铜或金焊线5键合与单元框架的内引脚4相连;最后,塑封体6完全覆盖了第一、第二IC芯片11、12、键合金或铜线5、9、金或铜球10、键合球20及单元框架的引线脚4而构成了电路整体。
实施例4,参照图1、图2、图6,一种基于实施例1的单元框架的双芯片IC堆叠封装件,包括所述封装单元上的载体1及该载体1堆叠放置的第一、第二芯片13、14,具体为:该载体1上先置第一IC芯片13,该第一IC芯片13上的焊盘通过键合线5与内引脚4相连,之后,第一IC芯片13上再置第二IC芯片14,第一、第二IC芯片13、14通过铜或金焊线15键合相连,采用铜或金线16通过球焊把第二IC芯片14和单元框架的引线脚4相连,最后,塑封体6覆盖了第一、第二IC芯片13、14、键合金或铜线5、15、16及单元框架的引线脚4而构成了电路整体。
本实施例中的芯片经过粗磨、细磨、抛光后可实现3芯片或4芯片或5芯片或6芯片堆叠的多芯片IC封装件。
实施例5,参照图1、图3、图5,一种基于实施例2的单元框架的双芯片IC封装件,包括所述单元框架上的载体7、8,该载体7、8上分置第一、第二IC芯片11、12,第一IC芯片11或第二IC芯片12上的焊盘上先各预植一个金或铜球10,然后用金或铜线在第一IC芯片11的金或铜球10上堆叠金或铜键合球,拱丝拉弧在第二IC芯片12上的焊盘的金或铜球上堆叠金或铜键合球,形成键合球20,该键合球20使第一、第二IC芯片11、12相连;所述第一、第二IC芯片11、12外焊盘通过金或铜焊线5键合与封装单元的内引脚4相连,最后,塑封体6完全覆盖了第一、第二IC芯片11、12、键合金或铜线5、9、金或铜球10、键合球20及单元框架的引线脚4而构成了电路整体。
实施例3及实施例5的双芯片IC封装件的封装工艺流程如下:
晶圆减薄主轴转速为2400 rpm-3000 rpm,晶圆减薄厚度380um±20um;
晶圆减薄、划片的设备和工艺同普通双排框架封装晶圆减薄、划片工艺;
b、上芯
采用单载体单元框架或双载体单元框架,先在单或双载体上点上粘片胶(导电胶或绝缘胶),将芯片粘在载体上,若是不同的芯片,先粘小芯片,粘完所有小芯片后再粘另一个载体上的芯片,粘片机通常采用AD829A和AD828两种粘片机,根据芯片尺寸和芯片尺寸的大小选择吸嘴和点胶头的形状和尺寸,吸嘴上芯的升降高度为4000-6500step,顶针上升高度为100-160step,顶针上升延迟时间为5-10ms,点胶高度为1400-2000step,粘片胶厚度控制在8-38um内,固化烘烤氮气流量>0.8 l/h,烘烤温度175-180℃,3小时;
c、压焊
衬底加热温度为228℃-235℃,调节打火流量为2600mA-3100mA,调节打火放电时间为630us-710us,使金球头部融化以获得表面圆滑无缺陷的金球FAB,接线劈刀上加上时间为10ms±3ms的超声波和压力,超声频率为120KHZ±10 KHZ,输出方式为电流,功率为41mw±3mw,压力输出为32gf±2gf;
d、塑封、后固化
多排矩阵式框架塑封使用MGP塑封模具,注塑压力:(1200-1800)Psi、注塑时间:7-15S、模具温度:160-180℃、合模压焊:8-20Mpa、固化时间:120-150s,后固化温度175-180℃,7小时;
e、打印
同普通DIP塑料封装集成电路生产工艺;
f、电镀
电镀设备从以前的挂镀电镀方式改为高速线电镀方式,先将塑封后的产品送高速电镀线电镀,镀液温度:35-45℃,电镀电流:95±5A/槽,镀层厚度控制在:7.0-20.32um;
g、切筋成型
采用自动切筋成型系统,自动进料,自动入管。
实施例4的双芯片IC堆叠封装件的封装工艺流程如下:
a.减薄/划片
下层芯片对应的晶圆减薄厚度为:200μm +10μm,粗糙度Ra 0.10mm~0.05mm,上层芯片对应的晶圆减薄厚度为:180μm +10μm,减薄机具备8″~12″超薄减薄抛光功能,采用防翘曲薄减薄抛光工艺;
b、一次上芯
采用单载体单元框架,使用专用上料夹,点胶头均匀的将导电胶点在引线框架载体上,将下层芯片(大芯片)粘在载体上,吸嘴上芯的升降高度为4000-6500step,顶针上升高度为100-160step,顶针上升延迟时间为5-10ms,点胶高度为1400-2000step,粘片胶厚度控制在8-38um内,固化烘烤氮气流量>0.8 l/h;
c、二次上芯
在第一层芯片正面先点上绝缘胶(QMI538NB),再将第二个芯片对准粘在上面,放在一层芯片的正面。两次上芯后一次固化,烘烤温度:150-175℃,烘烤时间:180min;
d、压焊
双芯片堆叠封装,一般情况下,先连接上下芯片间的焊线,其次连接下层芯片与引脚间连线,最后焊接上层芯片与引脚间连接,焊线高度要严格控制,弧高控制在150um-300um,防止上下层焊线间短路。线间距小于2倍的线径为不良;
塑封、打印、电镀、切筋成型方法同DIP单芯片封装件。
利用实施例1的单芯片IC封装件的生产工艺与现有DIP塑封集成电路生产流程一样。
Claims (7)
1.一种矩阵式DIP引线框架,由框架及设在框架内的若干个单元框架组成,其特征在于:所述单元框架在所述框架上呈矩阵式分布且行数为奇数行,其中第2n-1行与第2n行的相邻单元框架的基岛通过连接条(18)与所述框架边框相连,第2n-1行与第2n行的相邻单元框架的外引线脚交错排列,并通过栅条(19)与所述框架边框连接。
2.根据权利要求1所述的矩阵式DIP引线框架,其特征在于:所述单元框架是单载体结构且行数为奇数行,其中第2n-1行与第2n行的相邻单元框架的基岛通过连接条(18)与所述框架边框相连,第2n-1行与第2n行的相邻单元框架的外引线脚交错排列,并通过栅条(19)与所述框架边框连接。
3.根据权利要求1所述的矩阵式DIP引线框架,其特征在于:所述单元框架是双载体结构且行数为奇数行,即每个单元框架有两个载体;其中单元框架A的引脚A7、A8与载体Z2相连、引脚A3与载体Z1相连,相邻单元框架B的引脚B7和B8与载体Z4相连、引脚B3与载体Z3相连接;其中第2n-1行与第2n行的相邻单元框架的基岛通过连接条(18)与所述框架边框相连,第2n-1行与第2n行的相邻单元框架的外引线脚交错排列,并通过栅条(19)与所述框架边框连接。
4.根据权利要求1或2或3所述的矩阵式DIP引线框架,其特征在于:所述单元框架为5行。
5.一种根据权利要求2的双芯片IC封装件,其特征在于:包括所述单元框架上的载体(1),该单元框架的载体(1)上并行放置第一、第二IC芯片(11、12),该第一IC芯片(11)和第二IC芯片(12)上的焊盘上先各预植一个金或铜球(10),然后用金或铜线在第一IC芯片(11)的金或铜球(10)上堆叠金线或铜线键合球,拱丝拉弧在第二IC芯片(12)上的焊盘的金或铜球上堆叠金线或铜线键合球,形成键合球(20),该键合球(20)使第一、第二IC芯片(11、12)相连;所述第一、第二IC芯片(11、12)的外焊盘通过铜或金焊线(5)键合与单元框架的内引脚(4)相连;最后,塑封体(6)完全覆盖了第一、第二IC芯片(11、12)、键合金或铜线(5、9)、金或铜球(10)、键合球(20)及单元框架引线脚(4)而构成了电路整体。
6.一种根据权利要求2的双芯片IC封装件,其特征在于:包括所述单元框架上的载体(1)、及该载体(1)中堆叠放置的第一、第二芯片(13、14)具体为:该载体(1)上先置第一IC芯片(13),该第一IC芯片(13)上的焊盘通过键合线(5)与内引脚(4)相连,之后,第一IC芯片(13)上再置第二IC芯片(14),第一、第二IC芯片(13、14)通过铜或金焊线(15)键合相连,采用铜或金线(16)通过球焊把第二IC芯片(14)和单元框架的引线脚(4)相连,最后,塑封体(6)覆盖了第一、第二IC芯片(13、14)、键合金或铜线(5、15、16)及单元框架的引线脚(4)而构成了电路整体。
7.一种根据权利要求3的双芯片IC封装件,其特征在于:包括所述单元框架上的载体(7、8),该载体(7、8)上分置第一、第二IC芯片(11、12),第一IC芯片(11)或第二IC芯片(12)上的焊盘上先各预植一个金或铜球(10),然后用金或铜线在第一IC芯片(11)的金或铜球(10)上堆叠金线或铜线键合球,拱丝拉弧在第二IC芯片(12)上的焊盘的金或铜球上堆叠金线或铜线键合球,形成键合球(20),该键合球(20)使第一IC芯片(11)和第二IC芯片(12)相连;所述第一、第二IC芯片(11、12)外焊盘通过金或铜焊线(5)键合与所述单元框架的内引脚(4)相连,最后,塑封体(6)完全覆盖了第一、第二IC芯片(11、12)、键合金或铜线(5、9)、金或铜球(10)、键合球(20)及单元框架的引线脚(4)而构成了电路整体。
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CN108257881A (zh) * | 2018-01-03 | 2018-07-06 | 四川明泰电子科技有限公司 | 一种tdip8l芯片封装方法 |
CN110010749A (zh) * | 2017-12-22 | 2019-07-12 | 朗德万斯公司 | 具有引线框架的灯管 |
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CN102074540B (zh) * | 2010-11-26 | 2013-01-09 | 天水华天科技股份有限公司 | 矩阵式dip引线框架、该框架的ic封装件及其生产方法 |
CN110010749A (zh) * | 2017-12-22 | 2019-07-12 | 朗德万斯公司 | 具有引线框架的灯管 |
CN110010749B (zh) * | 2017-12-22 | 2022-04-08 | 朗德万斯公司 | 具有引线框架的灯管 |
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