CN102044445B - 无外引脚半导体封装构造的导线架制造方法 - Google Patents
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Abstract
本发明公开一种无外引脚半导体封装构造的导线架制造方法,其先提供一绝缘载板,再对绝缘载板的至少一表面进行钻孔作业,以形成彼此相互分离的数个通孔。接着,于通孔内形成对应构形的导电接点,因而制备形成一无外引脚半导体封装构造(QFN)的导线架。如此,可使所述导线架在由材料厂出货时已预先具备最终导线架形态,因此封装厂在进行后段封装作业时即不再需要进行任何蚀刻作业,故有利于避免封装半成品在制造过程中受到污染,并可简化封装厂后段封装作业。
Description
【技术领域】
本发明是有关于一种无外引脚半导体封装构造的导线架制造方法,特别是有关于一种可避免封装半成品在制造过程中受到蚀刻液的污染并可简化封装厂后段封装作业的无外引脚半导体封装构造的导线架制造方法。
【背景技术】
现今,半导体封装产业为了满足各种高密度封装的需求,逐渐发展出各种不同型式的封装构造,而这些封装构造通常是选用导线架(leadframe)或封装基板(substrate)来做为承载芯片的载板(carrier),其中常见使用导线架的封装构造例如为小外型封装构造(small outline package,SOP)、方型扁平封装构造(quad flat package,QFP)或四方扁平无外引脚封装构造(quad flat no-leadpackage,QFN)等。
请参照图1A、1B、1C、1D及1E所示,其揭示一种现有四方扁平无外引脚封装构造(QFN)的制造流程示意图,其主要包含一金属板11、一芯片12、数条导线13及一封装胶体14。在制造流程上,如图1A所示,首先准备一金属板11,其是一平坦且未加工过的金属板体。接着,如图1B所示,对所述金属板11的一第一表面进行第一次半蚀刻(half-etching)作业,因而形成一芯片承座111及数个接点112的预设凸岛状构形(profile),其中所述数个接点112以单组或多组方式环绕排列在所述芯片承座111的周围。在第一次半蚀刻作业后,如图1C所示,将所述芯片12固定在所述芯片承座111上,且利用所述数条导线13进行打线作业,以将所述芯片12上的数个接垫分别电性连接到所述数个接点112上。在打线作业后,如图1D所示,利用所述封装胶体14进行封胶作业,以包埋保护所述芯片12、导线13及所述金属板11的第一表面侧,所述封装胶体14仅裸露出所述金属板11的一第二表面。在封胶作业后,如图1E所示,对所述金属板11的第二表面进行第二次半蚀刻(half-etching)作业,因而使所述芯片承座111及所述接点112的凸岛状构形彼此分离,因而形成一四方扁平无外引脚型的导线架110架构。如此,即可完成一无外引脚半导体封装构造100的制造,其中所述接点112的裸露下表面即可做为输入/输出端子。
然而,上述无外引脚半导体封装构造100在实际上仍具有下述问题,例如:在进行第二次半蚀刻作业时,所述金属板11与所述封装胶体14已是一封装半成品,因此蚀刻液等加工处理液体等可能对封装半成品的外观或内部元件造成污染或腐蚀等损害。再者,第二次半蚀刻作业也会蚀刻掉所述接点112的下表面的侧缘部分,若蚀刻时间等参数控制不当,即可能过度蚀刻所述接点112,进而影响所述接点112外形的良品率(yield)或后续进行表面固定(SMT)时的电性连接质量。而且,若第二次半蚀刻作业失败,则整个封装半成品都要报废,其不良品的报废成本因包含所述芯片12、导线13及封装胶体14在内,故将使报废成本大幅提高。另外,在现行的封装产业中,所述金属板11可能是在上游材料厂制做到如图1B的状态后,再被运送到封装厂进行图1C及1D的上芯片、打线及封胶等后段作业。然而,在上述制造流程中,在封胶作业之后,尚需在封装厂内进行图1E的第二次半蚀刻作业。惟,大多数的封装厂本身并没有蚀刻设备,因此为了实施上述制造流程,封装厂必需额外建立蚀刻作业的生产线,而此举将大幅增加封装厂的作业复杂度及设备成本。
故,有必要提供一种无外引脚半导体封装构造的导线架制造方法,以解决现有技术所存在的问题。
【发明内容】
本发明的主要目的在于提供一种无外引脚半导体封装构造的导线架制造方法,其中先提供一绝缘载板,再对绝缘载板的至少一表面进行钻孔作业,以形成彼此相互分离的数个通孔。接着,于通孔内形成对应构形的导电接点,因而制备形成一无外引脚半导体封装构造(QFN)的导线架。如此,可使所述导线架在由材料厂出货时已预先具备最终导线架形态,因此封装厂在进行后段封装作业时即不再需要进行任何蚀刻作业,故有利于避免封装半成品在制造过程中受到污染,并可简化封装厂后段封装作业。
本发明的次要目的在于提供一种无外引脚半导体封装构造的导线架制造方法,其中仅需使用机械或激光的钻孔方式,故能尽量避免芯片承座及导电接点的表面受到蚀刻液污染,以减少对其进行表面处理(如电镀)之前的表面清洁需求,故有利于简化导线架的制造过程及降低导线架的加工处理成本。
为达成本发明的前述目的,本发明提供一种无外引脚半导体封装构造的导线架的制造方法,其特征在于:所述制造方法包含:提供一绝缘载板,具有一第一表面及一第二表面;对所述绝缘载板的第一表面进行第一次钻孔作业,以形成数个彼此相互分离的第一凹陷部;对所述绝缘载板的第二表面进行第二次钻孔作业,以形成数个彼此相互分离的第二凹陷部,所述第一及第二凹陷部相互对应且连通形成数个通孔;以及,在所述通孔中填入一导电材料,以形成数个彼此相互分离的导电接点,因而所述绝缘载板及导电接点共同构成一无外引脚半导体封装构造的导线架。
再者,本发明提供另一种无外引脚半导体封装构造的导线架的制造方法,其特征在于:所述制造方法包含:提供一绝缘载板,具有一第一表面及一第二表面;对所述绝缘载板的第一表面进行一次钻孔作业,以贯穿所述绝缘载板形成数个彼此相互分离的通孔;以及,在所述通孔中填入一导电材料,以形成数个彼此相互分离的导电接点,因而所述绝缘载板及导电接点共同构成一无外引脚半导体封装构造的导线架。
在本发明的一实施例中,在构成所述导线架之后,另包含:提供一芯片并将所述芯片固定在所述绝缘载板上;利用数个导线来电性连接所述芯片与所述导电接点;以及利用一封装胶材来包覆保护所述芯片、所述导线以及所述导线架靠近所述芯片的表面,以构成一无外引脚半导体封装构造。
在本发明的一实施例中,在形成所述通孔及填入所述导电材料时,另同时形成至少一个芯片承座(die pad),其中所述导电接点围绕在所述芯片承座周围。
在本发明的一实施例中,在构成所述导线架之后,另包含:提供一芯片并将所述芯片固定在所述芯片承座上;利用数个导线来电性连接所述芯片与所述导电接点;以及利用一封装胶材来包覆保护所述芯片、所述导线以及所述导线架靠近所述芯片的表面,以构成一无外引脚半导体封装构造。
在本发明的一实施例中,在构成所述导线架之后,另包含:提供一倒装芯片(flip chip,FC);利用数个凸块来电性连接所述倒装芯片与所述导电接点;以及利用一封装胶材来包覆保护所述倒装芯片、所述凸块以及所述导线架靠近所述芯片的表面,以构成一无外引脚半导体封装构造。
在本发明的一实施例中,所述绝缘载板的绝缘材料选自纤维/树脂半固化片(prepreg)或环氧树脂模造塑料(epoxy molding compound,EMC)。所述纤维/树脂半固化片是将玻纤布或白牛皮纸等绝缘性载体材料,含浸在液态的树脂中,使其吸饱后再缓缓拖出及刮走多余含量,并经过热风与红外线的加热,挥发掉多余的溶剂且促使进行部份之聚合反应而形成。
在本发明的一实施例中,所述第一凹陷部的孔径大于所述第二凹陷部的孔径;或者,所述第二凹陷部的孔径大于所述第一凹陷部的孔径。
在本发明的一实施例中,所述第一次钻孔作业选择使用机械钻孔或激光钻孔来形成所述第一凹陷部;及所述第二次钻孔作业选择使用机械钻孔或激光钻孔来形成所述第二凹陷部。
在本发明的一实施例中,所述钻孔作业选择使用机械钻孔或激光钻孔来形成所述通孔。
在本发明的一实施例中,在所述通孔中填入所述导电材料的步骤中,选择以电镀或印刷的方式将所述导电材料填入所述通孔中。
在本发明的一实施例中,在形成所述导电接点后,所述导电接点(及/或所述芯片承座)的至少一表面进一步电镀形成至少一助焊层。
【附图说明】
图1A、1B、1C、1D及1E是一现有四方扁平无外引脚封装构造(QFN)的制造流程示意图。
图2A、2B、2C、2D、2E、2F及2G是本发明第一实施例无外引脚半导体封装构造的制造方法的流程示意图。
图3A、3B及3C是本发明第一实施例的绝缘载板各种导电接点的排列及构形的上视图。
图4A、4B、4C、4D、4E及4F是本发明第二实施例无外引脚半导体封装构造的制造方法的流程示意图。
图5A及5B是本发明第三及第四实施例无外引脚半导体封装构造的示意图。
【具体实施方式】
为让本发明上述目的、特征及优点更明显易懂,下文特举本发明较佳实施例,并配合附图,作详细说明如下。再者,本发明所提到的方向用语,例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」或「侧面」等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。
请参照图2A至2G所示,其揭示本发明第一实施例无外引脚半导体封装构造的制造方法的流程示意图,其中本发明主要应用在制做无外引脚半导体封装构造(QFN)的导线架,本发明的无外引脚半导体封装构造的制造方法主要包含:提供一绝缘载板21,具有一第一表面211及一第二表面212;对所述绝缘载板21的第一表面211进行第一次钻孔作业,以形成数个彼此相互分离的第一凹陷部213;对所述绝缘载板21的第二表面212进行第二次钻孔作业,以形成数个彼此相互分离的第二凹陷部214,所述第一及第二凹陷部213、214相互对应且连通形成数个通孔215;以及,在所述通孔215中填入一导电材料,以形成数个彼此相互分离的导电接点216,因而所述绝缘载板21及导电接点216共同构成一无外引脚半导体封装构造(QFN)的导线架210。
请参照图2A所示,本发明第一实施例无外引脚半导体封装构造的制造方法首先提供一绝缘载板21,具有一第一表面211及一第二表面212。在本步骤中,所述绝缘载板21可选自各种具良好电绝缘性的材料,例如纤维/树脂半固化片(prepreg)或环氧树脂模造塑料(epoxy molding compound,EMC)等,但并不限于此。上述纤维/树脂半固化片是指将玻纤布或白牛皮纸等绝缘性载体材料,含浸在液态的树脂中,使其吸饱后再缓缓拖出及刮走多余含量,并经过热风与红外线的加热,挥发掉多余的溶剂且促使进行部份之聚合反应而形成的绝缘载板。所述绝缘载板21可利用后续步骤来制做单一导线架210或同时制做二个或以上的导线架210。本实施例在此是举例示意同时制做二个或数个导线架210,但为了使本发明技术特征更容易被了解,下文皆是针对单一导线架210的架构来进行简单说明。再者,所述绝缘载板21的第一表面211及第二表面212则是分别以图2A中的上表面及下表面为例来进行说明。
请参照图2B所示,本发明第一实施例无外引脚半导体封装构造的制造方法接着对所述绝缘载板21的第一表面211进行第一次钻孔作业,以形成数个彼此相互分离的第一凹陷部213。在本步骤中,所述第一次钻孔作业可以选择使用机械钻孔、激光(laser)钻孔或冲压(punch)钻孔来形成所述第一凹陷部213,所述第一凹陷部213能初步分隔定义出后续步骤欲形成的数个导电接点216的凸岛状构形(profile)的上半部,如图3A及3B的实线位置所示,所述第一凹陷部213的孔形可以是圆形、矩形、正方形或其他几何形状。必要时,如图3C所示,也可以同时由某些具有较大孔径的第一凹陷部213来定义出后续步骤欲形成的至少一个芯片承座(die pad)217的凸岛状构形的上半部,其中所述导电接点216的第一凹陷部213是围绕在所述芯片承座217的第一凹陷部213的周围。所述第一凹陷部213的形成不需搭配无法重复使用的蚀刻液、光刻胶膜(photoresist layer)及保护膜,故有利于简化第一次钻孔作业的制造过程并能相对降低加工所需的耗材成本。
请参照图2C所示,本发明第一实施例无外引脚半导体封装构造的制造方法接着对所述绝缘载板21的第二表面212进行第二次钻孔作业,以形成数个彼此相互分离的第二凹陷部214,所述第一及第二凹陷部213、214相互对应且连通形成数个通孔215。在本步骤中,所述第二次钻孔作业同样可以选择使用机械钻孔、激光钻孔或冲压钻孔来形成所述第二凹陷部214,所述第二凹陷部214能初步分隔定义出后续步骤欲形成的数个导电接点216的凸岛状构形的下半部,如图3A及3B的虚线位置所示,所述第二凹陷部214的孔形可以是圆形、矩形、正方形或其他几何形状。必要时,如图3C所示,也可以同时由某些具有较大孔径的第二凹陷部214来定义出后续步骤欲形成的至少一个芯片承座217的凸岛状构形的下半部,其中所述导电接点216的第二凹陷部214是围绕在所述芯片承座217的第二凹陷部214的周围。所述第二凹陷部214的形成不需搭配无法重复使用的蚀刻液、光刻胶膜及保护膜,故有利于简化第二次钻孔作业的制造过程并能相对降低加工所需的耗材成本。在形成所述数个彼此相互分离的第二凹陷部214之后,所述第一及第二凹陷部213、214即可相互对应且连通形成数个彼此相互分离的通孔215,其中每一通孔215在横截面上具有一T字形或倒凸字形的构形。
请参照图2D所示,本发明第一实施例无外引脚半导体封装构造的制造方法接着在所述通孔215中填入一导电材料,以形成数个彼此相互分离的导电接点216,因而所述绝缘载板21及导电接点216共同构成一无外引脚半导体封装构造(QFN)的导线架210。在本步骤中,所述导电材料可选自各种具良好导电性的金属,例如铜、铁、铝、镍、锌或其合金等。同时,填入方式可以是电镀(electro-plating)或印刷(printing)。由所述第一及第二凹陷部213、214形成的通孔215能完全分隔定义出所述数个导电接点216(及芯片承座217)的凸岛状构形,其中每一所述数个导电接点216(及芯片承座217)在横截面上也对应具有一T字形或倒凸字形的构形,故能形成一自锁(mold lock)微结构,以相对增加所述导线架210的结构可靠度。在本实施例中,所述第一次钻孔作业形成的第一凹陷部213的孔径大于所述第二次钻孔作业形成的第二凹陷部214的孔径,此时所述绝缘载板21的第一表面211侧用以在后续步骤承载芯片30、导线40及封装胶材50等组件。
惟,在其他实施方式中,所述第一次钻孔也可以先形成较小孔径的凹陷部,也就是,所述第一次钻孔作业形成的第一凹陷部213的孔径小于所述第二次钻孔作业形成的第二凹陷部214的孔径,此时所述绝缘载板21的第二表面212侧用以在后续步骤承载芯片30、导线40及封装胶材50等组件。此外,所述导电接点216(及/或所述芯片承座217)的至少一表面也可进一步电镀形成至少一助焊层(未绘示),以增加后续打线的电性连接质量。
请参照图2E、2F及2G所示,本发明第一实施例无外引脚半导体封装构造的制造方法在构成所述导线架210之后,另包含:提供一芯片30并将所述芯片30固定在所述绝缘载板21上;利用数个导线40来电性连接所述芯片30与所述导电接点216;以及利用一封装胶材50来包覆保护所述芯片30、所述导线40以及所述导线架210靠近所述芯片30的表面,以构成一无外引脚半导体封装构造200。若同一所述导线架210包含数个所述无外引脚半导体封装构造200,则进一步再进行一切割步骤,以分离各个所述无外引脚半导体封装构造200。在本步骤中,若所述绝缘载板21形成有所述芯片承座217,则将所述芯片30固定在所述芯片承座217上。在本实施例中,所述导线40可选自金线、铜线、铝线、镀钯铜线或其他金属线材,本发明并不加以限制。所述数个导线40是电性连接在所述芯片30朝上的一有源表面的数个接垫与所述导电接点216的表面之间。所述封装胶材50优选是选自环氧树脂模造塑料(epoxy molding compound,EMC),其泛指常用的封装材料。在制造所述无外引脚半导体封装构造200之后,由于所述导电接点216在横截面上具有一T字形或倒凸字形的构形,因此能形成一自锁微结构,以防止所述导电接点216脱离所述绝缘载板21,故可相对增加所述导线架210的结构可靠度。
值得注意的是,当所述绝缘载板21也选自环氧树脂模造塑料时,所述绝缘载板21与所述封装胶材50实际上是在二个不同的先后步骤中各自形成的不同结构部分。再者,本发明最初是由所述绝缘载板21通过二次钻孔作业及电镀或印刷加工来形成所述导线架210的结构;反观,图1A至1E的现有制造方法则是由所述金属板11通过二次半蚀刻作业来形成所述导线架110的结构,两者的制造方式在最初材料及加工方式等方面存在有显着差异。
请参照图4A至4F所示,本发明第二实施例的无外引脚半导体封装构造及其导线架的制造方法相似于本发明第一实施例,并大致沿用相同元件名称及图号,第二实施例包含下列步骤:提供一绝缘载板21,具有一第一表面211及一第二表面212;对所述绝缘载板21的第一表面211进行一次钻孔作业,以贯穿所述绝缘载板21形成数个彼此相互分离的通孔215;以及,在所述通孔215中填入一导电材料,以形成数个彼此相互分离的导电接点216,因而所述绝缘载板21及导电接点216共同构成一无外引脚半导体封装构造(QFN)的导线架210。在构成所述导线架210之后,另包含:提供一芯片30并将所述芯片30固定在所述绝缘载板21上;利用数个导线40来电性连接所述芯片30与所述导电接点216;以及利用一封装胶材50来包覆保护所述芯片30、所述导线40以及所述导线架210靠近所述芯片30的表面,以构成一无外引脚半导体封装构造200。必要时,也可类似于图3A所示,同时形成至少一个芯片承座(die pad),其中所述导电接点216围绕在所述芯片承座周围,所述芯片承座用以承载所述芯片30。上述第二实施例的差异特征在于:所述第二实施例的绝缘载板21是直接贯穿所述绝缘载板21形成所述通孔215,而非由所述第一凹陷部213及第二凹陷部214所连通形成的。所述通孔215是一长条状通孔,其横截面形状相似于I形。此差异特征的优点在于:能进一步缩小所述导电接点216的尺寸及间距,使得所述半导体封装构造200能在相同长宽尺寸的导线架210规格下设置更多数量的导电接点216。因此,有利于进一步相对提高所述导电接点216的布局密度。
请参照图5A所示,本发明第三实施例的无外引脚半导体封装构造及其导线架的制造方法相似于本发明第一实施例,并大致沿用相同元件名称及图号,但第三实施例的差异特征在于:所述第三实施例的导线架210仅包含数个导电接点216及一绝缘载板21,并省略设置芯片承座(如图3C所示)。再者,所述第一凹陷部213的宽度设计成大于所述第二凹陷部214的宽度,使得所述导电接点216的横截面形状相似于T形。另外,所述芯片30的有源表面是朝向所述导电接点216,且是通过数个凸块40’而以倒装芯片(flipchip,FC)的方式来设置在所述导电接点216上,所述凸块40’用以取代导线,以电性连接在所述导电接点216及所述芯片30的有源表面的接垫之间。所述封装胶材50用来包覆保护所述芯片30、所述凸块40’以及所述导线架210靠近所述第一凹陷部213的表面,以构成一种倒装芯片式的无外引脚半导体封装构造(FC-QFN)200。
请参照图5B所示,本发明第四实施例的无外引脚半导体封装构造及其导线架的制造方法相似于本发明第二实施例,并大致沿用相同元件名称及图号,但第四实施例的差异特征在于:所述第四实施例的导线架210仅包含数个导电接点216及一绝缘载板21,并省略设置芯片承座(如图3C所示)。再者,所述通孔215是一长条状通孔,其横截面形状相似于I形。另外,所述芯片30的有源表面是朝向所述导电接点216,且是通过数个凸块40’而以倒装芯片(flip chip,FC)的方式来设置在所述导电接点216上,所述凸块40’用以取代导线,以电性连接在所述导电接点216及所述芯片30的有源表面的接垫之间。所述封装胶材50用来包覆保护所述芯片30、所述凸块40’以及所述导线架210的一表面,以构成另一种倒装芯片式的无外引脚半导体封装构造(FC-QFN)200。
如上所述,相较于现有无外引脚半导体封装构造及其导线架的制造方法容易在第二次半蚀刻作业时造成污染、腐蚀或不良品,且需在封装厂内进行第二次半蚀刻作业会大幅增加封装厂的作业复杂度及设备成本等缺点,图2A至5B的本发明先提供一绝缘载板21,再对所述绝缘载板21的至少一表面211或212进行钻孔作业,以形成彼此相互分离的数个通孔215。接着,于所述通孔215内形成对应构形的导电接点216,因而制备形成一导线架210,以供制造一无外引脚半导体封装构造(QFN)200。如此,可使所述导线架210在由材料厂出货时已预先具备最终导线架形态,因此封装厂在进行后段封装作业时即不再需要进行任何蚀刻作业,故有利于避免封装半成品在制造过程中受到污染,并可简化封装厂后段封装作业。再者,本发明仅需使用机械、激光或冲压的钻孔方式,故能尽量避免芯片承座及导电接点的表面受到蚀刻液污染,以减少对其进行表面处理(如电镀)之前的表面清洁(如研磨或清洗)需求,故有利于简化所述导线架210的制造过程及降低所述导线架210的加工处理成本。
本发明已由上述相关实施例加以描述,然而上述实施例仅为实施本发明的范例。必需指出的是,已公开的实施例并未限制本发明的范围。相反地,包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。
Claims (10)
1.一种无外引脚半导体封装构造的导线架制造方法,其特征在于:所述导线架制造方法包含:
提供一绝缘载板,具有一第一表面及一第二表面;
对所述绝缘载板的第一表面进行第一次钻孔作业,以形成数个彼此相互分离的第一凹陷部;
对所述绝缘载板的第二表面进行第二次钻孔作业,以形成数个彼此相互分离的第二凹陷部,所述第一及第二凹陷部相互对应且连通形成数个通孔;以及
在所述通孔中填入一导电材料,以形成数个彼此相互分离的导电接点,因而所述绝缘载板及导电接点共同构成一无外引脚半导体封装构造的导线架。
2.一种无外引脚半导体封装构造的导线架制造方法,其特征在于:所述导线架制造方法包含:
提供一绝缘载板,具有一第一表面及一第二表面;
对所述绝缘载板的第一表面进行一次钻孔作业,以贯穿所述绝缘载板形成数个彼此相互分离的通孔;以及
在所述通孔中填入一导电材料,以形成数个彼此相互分离的导电接点,因而所述绝缘载板及导电接点共同构成一无外引脚半导体封装构造的导线架。
3.如权利要求1或2所述的无外引脚半导体封装构造的导线架制造方法,其特征在于:在构成所述导线架之后,另包含:
提供一芯片并将所述芯片固定在所述绝缘载板上;
利用数个导线来电性连接所述芯片与所述导电接点;以及
利用一封装胶材来包覆保护所述芯片、所述导线以及所述导线架靠近所述芯片的表面,以构成一无外引脚半导体封装构造。
4.如权利要求1或2所述的无外引脚半导体封装构造的导线架制造方法,其特征在于:在形成所述通孔及填入所述导电材料时,另形成至少一个芯片承座,其中所述导电接点围绕在所述芯片承座周围。
5.如权利要求4所述的无外引脚半导体封装构造的导线架制造方法,其特征在于:在构成所述导线架之后,另包含:
提供一芯片并将所述芯片固定在所述芯片承座上;
利用数个导线来电性连接所述芯片与所述导电接点;以及
利用一封装胶材来包覆保护所述芯片、所述导线以及所述导线架靠近所述芯片的表面,以构成一无外引脚半导体封装构造。
6.如权利要求1或2所述的无外引脚半导体封装构造的导线架制造方法,其特征在于:在构成所述导线架之后,另包含:
提供一倒装芯片;
利用数个凸块来电性连接所述倒装芯片与所述导电接点;以及
利用一封装胶材来包覆保护所述倒装芯片、所述凸块以及所述导线架靠近所述芯片的表面,以构成一无外引脚半导体封装构造。
7.如权利要求1或2所述的无外引脚半导体封装构造的导线架制造方法,其特征在于:所述绝缘载板的绝缘材料选自纤维/树脂半固化片或环氧树脂模造塑料。
8.如权利要求1所述的无外引脚半导体封装构造的导线架制造方法,其特征在于:所述第一凹陷部的孔径大于所述第二凹陷部的孔径;或者,所述第二凹陷部的孔径大于所述第一凹陷部的孔径。
9.如权利要求1所述的无外引脚半导体封装构造的导线架制造方法,其特征在于:所述第一次钻孔作业选择使用机械钻孔或激光钻孔来形成所述第一凹陷部;及所述第二次钻孔作业选择使用机械钻孔或激光钻孔来形成所述第二凹陷部。
10.如权利要求2所述的无外引脚半导体封装构造的导线架制造方法,其特征在于:所述钻孔作业选择使用机械钻孔或激光钻孔来形成所述通孔。
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