CN101317267A - 基于引线框架中的精密间距布线的系统封装（sip）器件 - Google Patents

基于引线框架中的精密间距布线的系统封装（sip）器件 Download PDF

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CN101317267A
CN101317267A CNA2006800442975A CN200680044297A CN101317267A CN 101317267 A CN101317267 A CN 101317267A CN A2006800442975 A CNA2006800442975 A CN A2006800442975A CN 200680044297 A CN200680044297 A CN 200680044297A CN 101317267 A CN101317267 A CN 101317267A
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conductive layer
fine
semiconductor device
pad
pitch
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CN101317267B (zh
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迪尔克·彼得斯
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Sheng Investment Co Ltd
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Koninklijke Philips Electronics NV
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Abstract

在一个示例实施例中，提供了用以安装集成电路(IC)器件(205)的封装基板(200)。该封装基板包括焊盘连接端(215)所环绕的IC器件放置区域(290)。为了在焊盘连接端附近放置表面安装器件，提供了多个元件焊盘(235a，235b，235c，235d)。多个元件焊盘围绕焊盘连接端(215)。多个器件管脚(225a，225b，225c，225d，245a，245b，245c，245d)围绕元件焊盘。具有精密间距导电通路(270)的多个器件管脚中的一个或多个将多个器件管脚中的一个或多个耦接至一组对应的焊盘连接端(215)，或一组对应的元件焊盘；精密间距导电通路(270)穿过多个元件焊盘之间的区域。

Description

基于引线框架中的精密间距布线的系统封装（SIP）器件
技术领域
本发明设计集成电路(IC)封装。更具体地，本发明涉及线在基于高性能引线框架的封装的基板中的布线(例如在系统封装器件中出现的布线)以容纳另外的元件。
背景技术
电子工业继续依赖于半导体技术的发展来实现更紧凑面积内的更高性能器件。对于很多应用而言，实现更高性能的器件，需要将大量的电子器件集成到单个硅晶片中。随着单位给定硅晶片面积上的电子器件的数量的增大，制造工艺变得更加困难。
迄今已经生产出了具有多种不同学科应用的多种半导体器件。这种基于硅的半导体器件通常包括金属氧化物半导体场效应晶体管(MOSFET)，诸如p沟道MOS(PMOS)、n沟道MOS(NMOS)和互补型MOS(CMOS)晶体管、双极性晶体管、BiCMOS晶体管。这种MOSFET器件包括导电栅极和类硅基板之间的绝缘材料，从而，这些器件通常被称为IGFET(insulated-gate FET，绝缘栅FET)。
这些半导体器件的每一个通常包括一个半导体基板，其上形成了多个有源器件。给定有源器件的特定结构可以随器件类型而变化。例如，在MOS晶体管中，有源器件通常包括源极区域和漏极区域以及调制源极与漏极之间电流的栅极电极。
而且，这种器件可以是在多种晶片制造工艺中生产的数字器件或者模拟器件，例如，CMOS、BiCMOS、Bipolar等。基板可以是硅、砷化镓(GaAs)或其他适于在其上建造微电子电路的基板。
在经过制造工艺之后，硅晶片具有预定数目的器件。这些器件被测试，搜集和封装合格器件。
复杂IC器件的封装在它的最终性能中起日渐重要的作用。在IC器件中，除了集成电路裸片之外，经常需要多个元件来执行使用者需要的希望的功能。封装必须适合现代技术的需要。例如，RF器件经常需要诸如片状电容器之类的表贴器件(SMD)来将RF与电路的其他部件断开。在总线器件中，输出的同时转换(SSO)通常需要在足够接近供电轨的地方有足够大的电容，以使SSO噪声最小。在功率管理器件中经常需要表贴器件。
可以在专利合作条约(PCT)下的国际申请公开的Kloen等人的名为“Semiconductor Device and Method of Manufacturing Same”(国际公开号，WO03/085731，公开日期，2003-10-16)和于2004年10月8日提交的同一发明人的名为“Semiconductor Device and Methodof Manufacturing Same”的美国专利申请10/510,591中发现一种适于高性能器件的示例封装。该封装已知为薄型通用无引脚工业封装(即，TULIP)。可以在PCT下的国际申请公开的Groenhuis等人的名为“Carrier，Method of Manufacturing a Carrier and an Electronic Device”(国际公开号：WO03/085728，公开日期：2003-10-16)和于2004年10月8日提交的同一发明人的名为“Carrier，Method ofManufacturing a Carrier and an Electronic Device”的美国专利申请10/510,588中发现另一个示例封装。通过全文引用将这些参考文献合并入本文。围绕该平台的封装包括但不限于QFN(Quad Flat-packNo-leads，四方扁平无引脚封装)、DQFN(Depopulated very-thin QuadFlat-pack No-leads，缩减型超薄四方扁平无引脚封装)、HVQFN(Heatsink Very-thin Quad Flat-pack No-leads，散热超薄四方扁平无引脚封装)、SSON(Shrink Small Outline，No leads，缩小外形无引脚封装)、XSON(eXtremely thin Small Outline，No lead，薄型极小外形无引脚封装)。
在一个示例产品中，SMD通常被焊接到在印刷电路板(PCB)上距封装IC一定距离的连接端上。安装在封装外侧的SMD消耗了宝贵的板空间，增大了板的成本。而且，有源芯片和SMD之间的距离会降低产品的性能。特别是在RF中，选择外部SMD的合适位置是一个挑战。IC设计中的这种挑战可能延迟上市时间。SMD可能包括但不限于SIP(系统封装)或MCM(silicon chips inmulti-chip-module package，多芯片模块封装的硅芯片)、诸如电阻、电容和电感之类的分立元件。
在另外一种示例产品中，可以将SMD放置在封装中没有键合线的位置。完全利用了宝贵的空间。
参照图1。在现有技术封装的示例中，基板100具有键合在其上的器件裸片110。SMD 120附着在焊盘130上。焊盘连接端140的外环环绕焊盘连接端145的内环。键合线160、165将焊盘连接端140、145耦接至在器件裸片110上的键合焊盘(未示出)。SMD位于远离键合线160、165的地方，没有键合线穿过SMD。
而且，使SMD位于封装内部并处于键合线下面是非常困难的，或者是不可能的，这是因为SMD可能在成型工艺过程中扰乱模塑料的流动，导致额外的引线偏移以及键合线之间的短路。在一些示例设计规则中，不可以在SMD下布线，这是因为在当前可行的具有引线框架的布线间距精度太低(例如，0.4mm，0.2mm的线宽和0.2mm的间距)。
发明内容
存在对布线方案的需要，这种方案使附加元件安装在IC封装内，这种IC封装可以增强产品的性能，并有效地利用封装的容积，并有效地减小生产成本。
发现本发明有利于促进附加元件安装在靠近IC器件裸片的IC封装内。采用连接线的精密间距布线来布置在附加元件的下面，允许IC器件裸片和封装之间的更短的键合线。键合线不穿过附加元件。而且，附加器件被放置在器件基板的范围内。在密封过程中，IC器件裸片和附加元件增益都被密封起来，不被操作环境影响。而且，密封材料的流动不为附加元件所干扰，附加元件可能导致额外的引线偏移，这会导致键合线之间的短路。
在根据本发明的示例实施例中，提供了用以安装集成电路(IC)器件的封装基板。该封装基板包括由焊盘连接端包围的IC器件放置区域。为了将表面安装器件放置在焊盘连接端附近，提供了多个元件焊盘。这些多个元件焊盘包围焊盘连接端。多个器件管脚包围元件焊盘。具有精密间距导电通路的多个器件管脚的一个或多个将多个器件管脚的一个或多个耦接至一组对应的焊盘连接端或一组对应的元件焊盘，精密间距导电通路穿过多个元件焊盘之间的区域。
在另一个示例实施例中，提供了一种半导体器件，其包括一个具有开口的底面层。载体具有与第二侧面相对的第一侧面，其中，第一侧面包括具有预定图案的导电层，该预定图案限定了多个相互隔离的连接导体，以及其中，第二侧面与底面层接触并包括与放置在基板上的连接导体对应的接触表面，其中，在底面层中的开口允许到连接导体的连接。载体包括在第一和第二侧面之间限定的腔，该腔具有裸片焊盘区域，载体另外还包括元件焊盘区域。元件焊盘区域规定了表面安装器件在载体上的布局，元件焊盘区域耦接至选择的具有精密间距导电通路的连接导体。集成电路(IC)包括位于腔内的裸片区域，并附着在底面层的裸片焊盘区域。该IC另外包括键合焊盘，该键合焊盘线键合至连接导体。钝化封壳密封该IC器件，并延伸至载体。钝化封装是机械锚定在连接导体的侧面中的。
在又一个示例实施例中，提供了一个半导体器件。该半导体器件包括具有开口的底面层。提供了载体，该载体具有与第二侧面相对的第一侧面。第一侧面包括导电层，该导电层包括预定图案，该预定图案限定了多个相互隔离的连接导体。该导电层具有第一导电层、第二导电层和第三导电层，第二导电层包括一种可以在蚀刻剂中被蚀刻的材料，这种蚀刻剂使第一导电层和第三导电层基本上不受影响，这种蚀刻剂限定了在连接导体侧面上的凹槽。导电层还包括预定图案，该预定图案限定了多个互相隔离的连接导体，第二侧面接触底面层并包括与放置在基板上的连接导体对应的接触表面，底面层中的开口允许到连接导体的连接。载体包括在第一侧面和第二侧面之间限定的腔，该腔具有裸片焊盘区域，载体还包括元件焊盘区域。元件焊盘区域规定了表面安装器件在载体上的布局，元件焊盘区域耦接至选择的具有精密间距导电通路的连接导体，该精密间距导电通路被限定在第一导电层或第三导电层。包括裸片区域的集成电路(IC)器件位于腔中，并附着在底面层的裸片焊盘区域，另外还包括线键合至连接导体的键合焊盘。提供了一种钝化封壳，该封壳密封IC器件并延伸至载体，其中，钝化封壳是机械锚定在连接导体的侧面的凹槽中的，该凹槽提供了到钝化封装的附接。
本发明的上述综述不是为了表述本发明的每个公开实施例或每一个方面。在附图和下文的详细描述中提供了其他方面和其他示例实施例。
附图说明
结合附图，考虑到下述的本发明多个实施例的详细描述，可以更完全地理解本发明，其中：
图1(现有技术)是一个低精度间距基板，其描述了示例产品裸片的键合以及远离键合线的表面安装器件(SMD)的布局；
图2是根据本发明设计的具有精密间距布线的QFN引线框架封装的示例实施例；
图3是图2的侧视图；以及
图4是制造根据本发明的IC器件中的示例工艺的流程图。
具体实施方式
当本发明可以修改为多种修改和可替换的形式时，通过附图中的示例示出了它们的细节，并对这些细节进行了详细的描述。然而，应当理解的是，这不是要将本发明局限于描述的特定实施例。相反，是为了覆盖落在由所附权利要求限定的本发明的精神和范围内的所有的修改方案、等价方案和可替换方案。
已经发现本发明在更加有效地利用高性能封装内的空间方面很有用处。在封装基板中从SMD器件到焊盘连接端的线的精密间距布置显著地减小了引线键合的长度，所述焊盘连接端依次引线键合至IC器件键合焊盘。引线键合越短，越容易制造。而且，使与较长的引线键合相关的寄生电感和电容最小。另外，减小了来自产品的印刷电路板上的SMD的连接布线。在RF和混合信号应用中，这些引线的缩减变得日益重要。例如，无线通信中的产品得益于减小的裸片尺寸和附加元件(例如，SMD、MCM等)的紧密布局。
在根据本发明的示例实施例中，HVQFN封装具有用于连接SMD到IC器件的精密间距布线。虽然描述了一个特定的封装，但是，本领域技术人员可以意识到，可以设计和使用其他类型的封装。可以使用本发明的封装是那些采用引线框架的封装。这些封装可以包括但不局限于无引脚芯片载体(leadless chip carrier，LCC)、薄型通用无引脚工业封装(thin universal leadless industrial package，TULIP)以及薄型阵列塑料封装(Thin Array Plastic Package，TAPP)等。例如，在功率管理器件中，由于电气接地和低温阻抗而需要暴露的金属裸片焊盘。对于RF器件，暴露的金属裸片焊盘形成了电气接地平面。
参照图2。多行QFN基板200具有放置在其上的器件裸片205。QFN基板可以采用TULIP技术。这种基板可以具有多于一个的夹在绝缘层之间的导电层。多个层提供了基板布线设计中的多种选择。键合线210将器件裸片205通过焊盘连接端215耦接至基板。外排器件管脚包围内排器件管脚。例如，管脚225a、225b、225c和225d是外排器件管脚，管脚245a、245b、245c和245d是内排器件管脚。如虚线所示，这些内排器件管脚包围元件焊盘，以容纳表面安装器件(SMD)235a、235b、235c和235d。SMD 220a、220b、220c和220d被放置在基板的角落。两个SMD 220c和220d具有精密间距布线，这些布线将这些器件耦接至焊盘连接端215。在多个SMD下面，来自内排器件管脚和外排器件管脚的精密间距布线用于将这些管脚连接至焊盘连接端215。例如，外部管脚225a和内部管脚245a具有精密间距布线270，其将这些各个焊盘连接至在器件裸片205附近的焊盘连接端。精密间距布线小于0.4mm(即，0.2mm线宽，0.2mm线间距)并克服了一些引线框架的低精度布线间距。在一个示例封装中，该精密间距布线大约是150μm(即，75μm线宽和75μm间距)。在根据本发明的其他封装中，该精密间距布线大约是100μm(即，50μm线宽和50μm间距)。在其余的封装中，该精密间距布线大约是80μm(40μm线宽和40μm间距)，允许200μm长度的2倍布线轨迹(3×间距+2×线宽)。在一种应用中的示例封装中，两个焊接连接之间的最小距离(例如，双排封装中的管脚)是大约200μm。在80μm的情况下，可能在2个管脚之间具有2倍轨迹。
与图1中的现有技术封装进行对比，键合线210不必要穿过SMD，键合线的长度更短。而且，不像图1中的封装的焊盘120上的SMD 130那样，可以更靠近器件裸片来放置SMD。
在根据本发明的另一个实施例中，TULIP平台适于合并该精密间距布线，使得可以在IC器件裸片附近放置SMD。参照图3，在图2的侧视图中，根据本发明，可以采用TULIP平台。TULIP可以具有一个层(1层)或三个层(3层)。在一个示例实施例中，使用的三个层包括Cu(1)、Ni(2)和Cu(3)。精密间距布线层270必须是一个薄层，换句话说，制备引线框架凹槽的下蚀刻会将精密间距布线轨迹蚀刻掉。在3层TULIP中，底层Cu层(3)可以用作精密布线层270。用粘合剂265将裸片205附着在裸片焊盘290上。将器件封装在模塑材料260中。在Ni(2)层中限定的凹槽295提供了对模塑材料260的锚定。从而，如图2所示，没有精密间距布线轨迹被直接提供在SMD 240下面。从封装的外侧可以看到Cu精密间距轨迹。然而，当这样的器件被安装在印刷电路板(PCB)上时，有短路的危险。通过向精密间距导电布线轨迹和不应该涂覆焊接剂的区域直接涂覆阻焊剂275，可以防止在PCB上由于焊接剂280而形成的短路。
在另一个示例实施例中，上部的Cu层(1)被用作精密间距导电通路(未示出)。通常，由于这些精密间距导电通路穿过元件焊盘，所以他们被布置在SMD 240下面。由封装设计的特定需求决定对限定精密间距导电通路的Cu层(1)或Cu层(3)的选择。
参照图4。在根据本发明的示例实施例中，可以封装IC器件。选择适于给定应用的引线框架5。设计具有用于SMD的合适的元件焊盘的引线框架，限定精密间距导线通路的布线，来将SMD耦接至选择的连接导体。采用根据本发明的精密间距布线可以适用于采用或没采用TULIP技术的引线框架。用粘合剂将IC裸片附着在引线框架中的裸片焊盘10。粘合剂可以是胶水或者胶带(例如，作为裸片载体涂覆的QFN封装带)。在粘附裸片之后，对粘合剂进行固化。然后对裸片进行引线键合15。键合裸片和引线框架组件被密封在一个钝化封壳中。在特定的示例工艺中，对组件进行平板成型和后固化处理20。在QFN类型封装中采用平板成型(或映像成型)来在一个步骤中将所有的IC器件密封在一个长带中。长带中的映像被密封在模塑材料中。然后，从映像中锯切出分离的器件。在后固化过程中，在大约150℃的烘焙箱中对长带进行烘焙。通常会在长带上放置重物，以增强模塑材料的固化和长带的平整。对密封的IC器件进行回蚀处理25。该蚀刻隔离了引线框架的接触焊盘，并将IC裸片底面向上暴露于裸片附着粘附剂。在“带中测试”中，对IC器件进行电测试30。分离并用带子捆IC器件35。丢弃有缺陷的器件。可以以阵列形式布置封装IC器件带，像在前述实施例中那样。
虽然参照一些特定的示例实施例对本发明进行了描述，但是本领域技术人员将认识到，在不脱离所附权利要求设定的本发明的精神和范围的情况下，可以对本发明进行很多改变。

Claims (21)

1.一种封装基板(200)，其用以安装集成电路(IC)器件，该封装基板包括：
IC器件放置区域(290)，其被焊盘连接端(215)环绕；
多个元件焊盘(235)，其用以将表面安装器件(240)放置在焊盘连接端(215)附近，多个元件焊盘环绕焊盘连接端(215)；以及
多个器件管脚(225，245)，其环绕元件焊盘，多个器件管脚(225，245)中的一个或多个具有精密间距导电通路(270)，这些导电通路将多个器件管脚中的一个或多个耦接至一组对应的焊盘连接端或一组对应的元件焊盘，精密间距导电通路穿过多个元件焊盘之间的区域。
2.根据权利要求1所述的封装基板，其中，所述基板包括一个或多个额外的导电层和一个或多个绝缘层。
3.根据权利要求2所述的封装基板，其中，通过限定在一个或多个额外的导电层中的其他的导电通路，将额外的多个器件管脚耦接至对应的额外一组焊盘连接端。
4.根据权利要求1所述的封装基板，其中，所述表面安装器件(240)包括从下列选择出的至少一个：表面安装电容、表面安装电阻、表面安装电感、集成电路芯片、振荡器。
5.根据权利要求1所述的封装基板，其中，在累计线宽和间距方面，将所述精密间距导电通路布置为小于大约80μm。
6.根据权利要求1所述的封装基板，其中，在累计线宽和间距方面，将所述精密间距导电通路布置在大约80μm到大约150μm的范围内。
7.一种半导体器件(200)，其包括：
具有开口的底面层；
载体，具有与第二侧面相对的第一侧面，其中，第一侧面包括导电层(1，2，3)，所述导电层具有预定图案，所述预定图案限定了多个相互隔离的连接导体(225，245)，以及其中，第二侧面与底面层接触，并包括与用以放置在基板上的连接导体对应的接触表面(280)，其中，底面层中的开口允许到连接导体的连接(280)；所述载体包括在第一和第二侧面之间限定的腔，所述腔具有裸片焊盘区域，所述载体还包括元件焊盘区域(235)，所述元件焊盘区域规定了表面安装器件(240)在载体上的布局，元件焊盘区域耦接至选择的具有精密间距导电通路的连接导体；
集成电路(IC)器件(205)，包括裸片区域，所述裸片区域位于腔中并附着在底面层的裸片焊盘区域(290)，还包括键合焊盘，所述键合焊盘被引线键合至连接导体；以及
钝化封壳(260)，其密封了IC器件(205)并延伸至载体，其中，钝化封壳是机械锚定到连接导体(225，245)中的侧面中的。
8.根据权利要求7所述的半导体器件，其中，所述侧表面具有凹槽，所述凹槽(295)提供了到钝化封壳的附接。
9.根据权利要求8所述的半导体器件，其中，所述凹槽是凹形或刻槽。
10.根据权利要求8所述的半导体器件，其中，所述导电层包括第一导电层(1)、第二导电层(2)和第三导电层(3)，第二导电层包括一种可以在一种蚀刻剂中被蚀刻的材料，这种蚀刻剂对第一导电层和第三导电层基本上没有影响，该蚀刻剂限定了在连接导体侧面中的凹槽。
11.根据权利要求10所述的半导体器件，其中，在第一导电层(1)中限定了精密间距导电通路。
12.根据权利要求10所述的半导体器件，其中，在第三导电层(3)中限定了精密间距导电通路(270)。
13.根据权利要求12所述的半导体器件，其中，用阻焊剂(275)保护精密间距导电通路(270)。
14.根据权利要求7所述的半导体器件，其中，所述元件焊盘区域环绕所述裸片焊盘区域。
15.根据权利要求7所述的半导体器件，其中，所述表面安装器件包括从下列选择出的至少一个：表面安装电容、表面安装电阻、表面安装电感、集成电路芯片、振荡器。
16.根据权利要求15所述的半导体器件，其中，所述表面安装器件是双端器件。
17.根据权利要求11所述的半导体器件，其中，在累计线宽和间距方面，将所述精密间距导电通路布置为小于大约80μm。
18.根据权利要求11所述的半导体器件，其中，在累计线宽和间距方面，将所述精密间距导电通路布置在大约80μm到大约150μm的范围内。
19.一种半导体器件(200)，其包括：
具有开口的底面层；
载体，具有与第二侧面相对的第一侧面，其中，第一侧面包括导电层(1，2，3)，所述导电层(1，2，3)具有预定图案，所述预定图案限定了多个相互隔离的连接导体(225，245)，所述导电层具有第一导电层(1)、第二导电层(2)和第三导电层(3)，第二导电层包括一种可以在一种蚀刻剂中被蚀刻的材料，这种蚀刻剂对第一导电层和第三导电层基本上没有影响，该蚀刻剂限定了在连接导体侧面中的凹槽(295)；第二侧面与底面层接触，并包括与用于放置在基板上的连接导体对应的接触表面(280)，其中底面层中的开口允许到连接导体的连接；所述载体包括在第一侧面和第二侧面之间限定的腔，所述腔具有裸片焊盘区域，所述载体还包括元件焊盘区域(220，235)，所述元件焊盘区域规定了表面安装器件(240)在载体上的布局，所述元件焊盘区域耦接至选择的具有精密间距导电通路(270)的连接导体，所述精密导电通路被限定在第一导电层(1)或第三导电层(3)中；
集成电路(IC)器件，包括裸片区域(290)，所述区域位于腔中，并附着(265)在底面层的裸片焊盘区域，还包括键合焊盘(215)，所述键合焊盘被引线键合至所述连接导体(225，245)；以及
钝化封壳(260)，其密封了IC器件，并延伸至载体，其中，所述钝化封壳机械锚定到所述连接导体侧面中的凹槽(295)中，其中，凹槽提供了到钝化封壳的附接。
20.根据权利要求19所述的半导体器件，其中，将阻焊剂涂覆到不具有连接导体的区域中的底面层上。
21.根据权利要求20所述的半导体器件，其中，将所述阻焊剂(275)涂覆到限定在第三导电层(3)中的所述精密间距导电通路(270)上，当将半导体器件焊接到印刷电路板(PCB)上时，所述阻焊剂密封所述精密间距导电通路。
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