CN101295982A - 频率合成器 - Google Patents
频率合成器 Download PDFInfo
- Publication number
- CN101295982A CN101295982A CNA2008100860411A CN200810086041A CN101295982A CN 101295982 A CN101295982 A CN 101295982A CN A2008100860411 A CNA2008100860411 A CN A2008100860411A CN 200810086041 A CN200810086041 A CN 200810086041A CN 101295982 A CN101295982 A CN 101295982A
- Authority
- CN
- China
- Prior art keywords
- coupled
- frequency
- metal oxide
- pair
- locked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910044991 metal oxide Inorganic materials 0.000 claims description 42
- 150000004706 metal oxides Chemical class 0.000 claims description 42
- 239000004065 semiconductor Substances 0.000 claims description 42
- 239000003990 capacitor Substances 0.000 claims description 11
- 230000000295 complement effect Effects 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 7
- 239000000872 buffer Substances 0.000 description 6
- 230000006641 stabilisation Effects 0.000 description 4
- 238000011105 stabilization Methods 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 206010027336 Menstruation delayed Diseases 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
- H03B5/1212—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0893—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
- H03K3/356034—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration
- H03K3/356043—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
本发明提供了一种频率合成器。频率合成器包含:谐波锁相以及锁频检测器,低通滤波器,压控振荡器,以及分频器。谐波锁相以及锁频检测器接收参考信号以及分割信号。低通滤波器耦接于谐波锁相以及锁频检测器。压控振荡器耦接于低通滤波器并提供输出信号。分频器耦接于压控振荡器以及谐波锁相以及锁频检测器之间。分割信号的频率为参考信号的谐波频率。本发明提供的频率合成器增加了等效输入频率以及分频比。因此,频率合成器允许低频参考信号,抑制了参考突波,并减少了其稳定时间。
Description
技术领域
本发明是关于一种频率合成器(frequency synthesizer),特别是关于具有谐波锁相以及锁频(harmonic locked phase/frequency)检测器的频率合成器。
背景技术
电子系统中的频率合成器是用于从单一固定时间基准(fixed timebase)或振荡器中产生任何范围的频率。很多现代的电子装置,包括:无线电接收机,移动电话,手提式步话机(walkie-talkies),无线电收发机(CB radio),卫星接收机,全球定位系统等,都具有频率合成器。因为57-64千兆赫兹(GHz)的毫米波段被通告可用于通常的非授权的使用,频率合成器可以对用于短距离室内通信的千兆数据率(giga-data-rate)无线传输起促进作用。对于数千兆字节每秒(Gb/s)的无线收发器来说,超高速频率合成器起到了非常重要的作用。
基于频率合成器的锁相环是设计者常用的一种结构。锁相环比较两个信号的频率,并且产生误差信号(error signal),误差信号与输入频率之间的差值成比例。误差信号用于驱动压控振荡器(voltage controlled oscillator),压控振荡器产生输出频率。输出频率通过分频器反馈到系统的输入端,产生一个负反馈回路。如果输出频率偏移,则误差信号会增加,驱动相反方向的频率以减少误差。因此输出被锁定在其它输入的频率上。此输入被称为参考,具有非常稳定的频率,且来自于晶体振荡器。
同时,众所周知,由于较薄的栅极氧化物厚度以及较短的通道长度,现代增强型互补金属氧化物半导体(complementary metal oxide semiconductor,CMOS)技术中的主动装置会受到栅极漏电流以及通道长度调制效应的影响,其会导致在超高频压控振荡器设计中的某些负面效应。首先,为了获得用于压控振荡器的宽调节范围,通常会使用较大的可变电容。然而,寄生电容限制了振荡频率。并且会导致栅极漏电流降低相噪声性能。其次,因为具有短通道长度的交叉耦接装置可以提供有限的输出电阻,来自电感电容槽(LC tank,以下简称为LC槽)的等效品质因素降低。这也会导致相噪声性能的降低,甚至会导致压控振荡器故障。
发明内容
为解决以上技术问题,本发明提供了一种频率合成器。
本发明提供了一种频率合成器,包含:谐波锁相以及锁频检测器,用于接收参考信号以及分割信号;低通滤波器,耦接于谐波锁相以及锁频检测器;压控振荡器,耦接于低通滤波器并提供输出信号;以及分频器,耦接于压控振荡器以及谐波锁相以及锁频检测器之间,用于将输出信号分频;其中,分割信号的频率为参考信号的一谐波频率。
本发明另提供了一种频率合成器,包含:谐波锁相以及锁频检测器,用于接收参考信号以及分割信号;低通滤波器,耦接于谐波锁相以及锁频检测器;压控振荡器,耦接于低通滤波器,并提供输出信号;以及分频器,耦接于压控振荡器以及谐波锁相以及锁频检测器之间,用于将输出信号分频。其中,压控振荡器包含:一对金属氧化物半导体晶体管,其中,此对金属氧化物半导体晶体管中的每一个金属氧化物半导体晶体管具有耦接于地的源极,以及交叉耦接于此对金属氧化物半导体晶体管中另一金属氧化物半导体晶体管的漏极的栅极;以及分布式电感电容槽,耦接于此对金属氧化物半导体晶体管的漏极之间,分布式电感电容槽包含:一对分布式电感,耦接于供应电压以及此对金属氧化物半导体晶体管的此对漏极之间;以及一对分布式电容,耦接于此对分布式电感以及地之间。
本发明另提供了一种频率合成器,包含:谐波锁相以及锁频检测器,接收参考信号以及分割信号;低通滤波器,耦接于谐波锁相以及锁频检测器;压控振荡器,耦接于低通滤波器,并提供输出信号;以及分频器,耦接于压控振荡器以及谐波锁相以及锁频检测器之间,用于将输出信号分频。其中该分频器包含:主锁存器;以及从锁存器,从锁存器包含多个数据输入端,数据输入端的每一个耦接于主锁存器的一对应的数据输出端,以及多个数据输出端,交叉耦接于主锁存器的多个对应的数据输入端。其中,主锁存器以及从锁存器各包含:一对互补金属氧化物半导体反相器,此对互补金属氧化物半导体反相器中的一个包含一电容,此电容耦接于一提升晶体管的栅极以及一下拉晶体管的栅极之间,此对互补金属氧化物半导体反相器中的另一个包含另一电容,此另一电容耦接于另一提升晶体管的栅极以及另一下拉晶体管的栅极之间;第一对N通道金属氧化物半导体晶体管,第一对N通道金属氧化物半导体晶体管中的一个包含:源极,耦接于下拉晶体管的漏极,栅极,接收输出信号,以及漏极,经由串联连接的电阻以及电感耦接于供应电压,第一对N通道金属氧化物半导体晶体管中的另一个包含:另一源极,耦接于该另一下拉晶体管的漏极,另一栅极,接收该输出信号,以及另一漏极,经由串联连接的另一电阻以及另一电感耦接于一供应电压;第二对N通道金属氧化物半导体晶体管,包含:一对源极,耦接于另一下拉晶体管的一漏极,一对栅极交叉耦接于第一对N通道金属氧化物半导体晶体管的对应的漏极,以及,一对漏极,耦接于该多个电阻以及该多个电感之间的节点。
本发明提供了基于频率合成器的谐波锁定(harmonic-locked)锁相环(phase lock loop,以下简称为PLL)。频率合成器增加了等效输入频率以及分频比(dividing ratio)。因此,频率合成器允许低频参考信号,抑制了参考突波(reference spur),并减少了其稳定时间(settling time)。
附图说明
图1A为依据本发明一实施例的频率合成器100的方框图。
图1B为图1A所示的频率合成器100的细化方框图。
图2为图1A所示的谐波锁相以及锁频检测器110的方框图。
图3A以及图3B分别为图1B中所示的压控振荡器130的一实施例的电路图。
图3C为图1B中所示的压控振荡器130的一实施例的四个子电感L1、L2、L3以及L4的布局图。
图4A为图1B所示的分频器140的一实施例的方框图。
图4B为图4A所示的分频器中的电流复用锁存器的一实施例的电路图。
图5A以及图5B分别为同步4/5分频电路的一实施例的方框图。
图6A,图6B以及图6C分别为信号端谐波锁相检测器于早期,晚期以及锁定状态的时序图。
具体实施方式
图1A是为依据本发明一实施例的频率合成器的方框图。频率合成器100包含:谐波锁相以及锁频检测器110,低通滤波器120,压控振荡器130,以及分频器140。谐波锁相以及锁频检测器110接收参考信号fref以及分割信号(divided signal)fdiv。低通滤波器120耦接于谐波锁相以及锁频检测器110。压控振荡器130耦接于低通滤波器120并提供输出信号fout。分频器140耦接于压控振荡器130以及谐波锁相以及锁频检测器110之间。分割信号fdiv的频率是为参考信号fref的谐波频率。谐波锁相以及锁频检测器110可以同时包括谐波锁相检测器(harmonic locked phase detector,以下简称为PD)以及谐波锁频检测器(harmonic locked frequency detector,以下简称为FD),也可以仅包括PD,或仅包括FD。
图1B为图1A所示的频率合成器100的细化方框图。请参考图1A,分割信号fdiv以及参考信号fref分别表示图1B中所示反馈时钟CKdiv以及参考时钟CKref的频率。在此实施例中,分割信号fdiv的频率为参考信号fref频率的两倍。请参考图1B,PD以及FD被用于减少突波以及减少稳定时间。压控振荡器130具有分布式LC槽且分频器140具有电流复用冲击载荷结构(current-reuse split-load structure),因此,可以完成高频操作。另外,128/129双模预置分频器(dual-modulus divide-by-128/129prescaler)150位于分频器140以及谐波锁相以及锁频检测器110之间。在较佳实施例中,频率合成器100进一步包含缓冲器170,缓冲器170耦接于压控振荡器130以及分频器140之间,且缓冲器170耦接于压控振荡器130的输出以及频率合成器100的输出之间。
图2为图1A所示的谐波锁相以及锁频检测器110的方框图。谐波锁相以及锁频检测器110包含D触发器210,异或门220,提升电流源230,以及下拉电流源240。D触发器210的数据输入端D接收参考信号fref,D触发器210的时钟输入端接收分割信号fdiv。异或门220接收参考信号fref以及D触发器210的反向输出信号Q。异或门220的输出信号控制提升电流源230,以及分割信号fdiv控制下拉电流源240。其中,分割信号fdiv以及参考信号fref分别表示图2中所示反馈时钟CKdiv以及参考时钟CKref的频率。
图3A以及图3B分别为图1B所示的压控振荡器130的一实施例的电路图。压控振荡器300包含一对金属氧化物半导体晶体管(MOS transistors)T1/T2以及分布式LC槽310,其中,分布式LC槽310耦接于金属氧化物半导体晶体管T1/T2的漏极D。金属氧化物半导体晶体管T1/T2进一步包含耦接于地GND的源极S以及交叉耦接于漏极D的栅极G。分布式LC槽310包含一对分布式电感L/L’以及一对分布式电容C/C’,其中,分布式电感L/L’耦接于供应电压VDD以及金属氧化物半导体晶体管T1/T2的漏极D之间,分布式电容C/C’耦接于分布式电感L/L’以及地GND之间。具体来说,每个分布式电感L/L’均可被平均地被分为两个串联连接的子电感且每个分布式电容C/C’均可被平均地被分为两个连接于对应的子电感以及地GND之间的子电容子电感之间的节点O/O’提供了频率合成器100的输出信号Vout1/Vout2。请参考图3B,电感L1以及L4与交叉耦接的金属氧化物半导体晶体管T1/T2的寄生电容共振。因此,振荡频率得到增强。四个子电感L1、L2、L3以及L4的布局如图3C所示。另外,如图3A所示,附加的电阻跨接于子电感因此,压控振荡器300的输出阻抗增加,且相噪声因此被抑制。为了降低漏电流,采用了小的可变电容来代替大的可变电容。为了获得宽调节范围,使用了如图3B所示的由三个开关控制的金属电容器。当压控振荡器300驱动分频器140且使用50的负载时,会用到两个独立的缓冲器(图1B中所示的缓冲器160以及缓冲器170)。另外,压控振荡器300进一步包含一对可变电容M/M’,每个可变电容M/M’包含栅极、源极以及漏极,其中,M的栅极耦接于子电感L1与L2之间的节点,M’的栅极耦接于子电感L3与L4之间的节点,且源极以及漏极相连以接收控制电压Vctrl,因此,控制电压Vctrl可以控制压控振荡器300。
图4A为图1B所示的分频器140的一实施例的方框图。分频器包含主锁存器410以及从锁存器420。从锁存器420的数据输入端D/D耦接于主锁存器410的对应的数据输出端Q/Q,且从锁存器420的数据输出端Q/Q交叉耦接于主锁存器410的对应的数据输入端D/D。分频器产生输出信号Vout,I以及Vout,Q以进行后续处理。其中,主锁存器410以及从锁存器420均可以为电流复用锁存器。
为了容忍压控振荡器过程的影响以及温度的变化,需要具有宽操作范围的分频器。图4B为图4A所示的分频器中的电流复用锁存器的一实施例的电路图。在传统的电流型逻辑(current-mode logic)锁存器中,具有较大宽度或较大直流偏移电流的输入时钟晶体管需要操作于非常高的频率上。在此实施例中,基于电流复用技术,增加了提升晶体管M5、M6以增加输入时钟晶体管的总跨导。另外,减少了晶体管M1,M2,M3以及M4的偏移电流以增强转换速度。与传统的分路升高技术相比,冲击载荷技术可以扩大操作频率的范围。为了实现静态的除2分频器(static divide-by-2 divider),需要用到主锁存器以及从锁存器。请参考图4B,如图4A所示的主锁存器410以及从锁存器420分别包含一对互补金属氧化物半导体(complementary metal oxidesemiconductor,以下简称为CMOS)反相器INV/INV’,第一对N通道金属氧化物半导体(N-channel Metal Oxide Semiconductor,以下简称为NMOS)晶体管M1/M2,以及第二对NMOS晶体管M3/M4。CMOS反相器INV包含电容C1、M5以及M7,电容C1耦接于提升晶体管M5的栅极以及下拉晶体管M7的栅极之间。CMOS反相器INV’包含电容C2、M6以及M8,电容C2耦接于提升晶体管M6以及下拉晶体管M8之间。晶体管M5以及M6可以为P通道金属氧化物半导体(P-channel Metal Oxide Semiconductor,以下简称为PMOS)晶体管。第一对NMOS晶体管M1/M2分别包含耦接于下拉晶体管M7/M8漏极的源极,用于从压控振荡器接收输出信号的栅极,以及依序通过电阻R以及电感L耦接于供应电压VDD的漏极。
如图1B所示的128/129双模预置分频器150包含:同步4/5分频电路(synchronous divide-by-4/5circuit)以及异步32分频电路(asynchronousdivide-by-32 circuit),其中,异步32分频电路由5个串级(cascade)的2分频器来实现。图5A以及图5B分别为同步4/5分频电路的一实施例的方框图。具体的描述请参考C.Lee等人发表于2006年9月IEEE Custom IntegratedCircuits Conference(一种与集成电路设计相关的国际会议)中的文章“A 44GHzdual-modulus divide-by-4/5prescaler in 90nm CMOS technology(在90纳米CMOS技术中44GHz的4/5双模预置分频器)”。为获得高速4/5预除器,使用了合并的或非(NOR)门及D触发器(DFF)电路来替代串级的或非门以及D触发器。门延迟因此而降低,同时操作速度得到了提升。需要注意的是,预除器使用了无被动电感的电流模式逻辑(Current Mode Logic,以下简称为CML)电路。
图6A,图6B以及图6C分别为信号端谐波锁相检测器的时序图。在此实施例中,图1B中所示的谐波锁相检测器实际上由差分CML电路实现。如图1B所示,反馈时钟CKdiv来自异步32分频电路的倒数第二个D触发器。反馈时钟CKdiv的频率为参考时钟CKref频率的两倍(也就是,fdiv=2fref),反馈时钟CKdiv被看作是下降信号“DN”。上升信号“UP”产生于图2所示的异或门220以及D触发器210。图6A,图6B以及图6C分别为谐波锁相检测器于早期,晚期以及锁定状态的时序图。例如,图6A,图6B以及图6C所示的上升以及下降信号的等效频率为锁定状态下参考时钟的频率的两倍。由于传统的频率检测器也能于谐波频率锁定,因此,在此实施例中使用了一种传统的频率检测器。通过谐波锁相以及锁频检测器,由于具有更高的等效输入频率,可以获得低参考突波以及快的稳定时间。电压至电流转换器(voltage-to-current converter,简称V/I)可将相位及频率误差转换为电压,以通过芯片上的回路滤波器控制压控振荡器。
本发明提供了一种基于频率合成器的谐波锁定PLL。频率合成器增加了等效输入频率以及分频比。因此,频率合成器允许低频参考信号,抑制了参考突波,并减少了其稳定时间。
虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,任何所属技术领域中的技术人员,在不脱离本发明的范围内,可以做一些改动,因此本发明的保护范围应与权利要求所界定的范围为准。
Claims (9)
1.一种频率合成器,其特征在于,所述的频率合成器包含:
谐波锁相以及锁频检测器,用于接收参考信号以及分割信号;
低通滤波器,耦接于所述的谐波锁相以及锁频检测器;
压控振荡器,耦接于所述的低通滤波器,并提供输出信号;以及
分频器,耦接于所述的压控振荡器以及所述的谐波锁相以及锁频检测器之间,用于将所述的输出信号分频;
其中,所述的分割信号的频率为所述的参考信号的谐波频率。
2.如权利要求1所述的频率合成器,其特征在于,所述的谐波锁相以及锁频检测器包含:
D触发器,于数据输入端接收所述的参考信号,并于时钟输入端接收所述的分割信号;
异或门,接收所述的参考信号以及所述的D触发器的反向输出信号;
提升电流源;以及
下拉电流源;其中,所述的提升电流源由所述的异或门的输出信号控制,以及所述的下拉电流源由所述的分割信号控制。
3.如权利要求1所述的频率合成器,其特征在于,所述的频率合成器进一步包含预除器,耦接于所述的分频器以及所述的谐波锁相以及锁频检测器之间。
4.一种频率合成器,其特征在于,所述的频率合成器包含:
谐波锁相以及锁频检测器,用于接收参考信号以及分割信号;
低通滤波器,耦接于所述的谐波锁相以及锁频检测器;
压控振荡器,耦接于所述的低通滤波器,并提供输出信号;以及
分频器,耦接于所述的压控振荡器以及所述的谐波锁相以及锁频检测器之间,用于将所述的输出信号分频;
其中,所述的压控振荡器包含:
一对金属氧化物半导体晶体管,其中,所述的这对金属氧化物半导体晶体管中的每一个金属氧化物半导体晶体管具有耦接于地的源极,以及交叉耦接于所述的这对金属氧化物半导体晶体管中另一金属氧化物半导体晶体管的漏极的栅极;以及
分布式电感电容槽,耦接于所述的这对金属氧化物半导体晶体管的所述的这对漏极之间,所述的分布式电感电容槽包含:
一对分布式电感,耦接于供应电压以及所述的这对金属氧化物半导体晶体管的所述的这对漏极之间;以及
一对分布式电容,耦接于所述的这对分布式电感以及地之间。
5.如权利要求4所述的频率合成器,其特征在于,所述的这对分布式电感中的每一个被平均地分为两个串联连接的子电感,以及所述的这对分布式电容中的每一个被平均地分为两个子电容,所述的两个子电容连接于对应的子电感以及地之间,其中,所述的两个子电感之间的节点提供所述的频率合成器的输出信号。
6.如权利要求5所述的频率合成器,其特征在于,所述的压控振荡器进一步包含多个电阻,所述的多个电阻中的每一个跨接于所述的两个子电感。
7.如权利要求5所述的频率合成器,其特征在于,所述的压控振荡器进一步包含:一对可变电容,所述的这对可变电容中的每一个包含:栅极,源极以及漏极,其中所述的栅极耦接于所述的两个子电感之间的对应的节点,以及所述的源极及所述的漏极相连,接收控制电压,所述的控制电压可控制所述的压控振荡器。
8.一种频率合成器,其特征在于,所述的频率合成器包含:
谐波锁相以及锁频检测器,接收参考信号以及分割信号;
低通滤波器,耦接于所述的谐波锁相以及锁频检测器;
压控振荡器,耦接于所述的低通滤波器,并提供输出信号;以及
分频器,耦接于所述的压控振荡器以及所述的谐波锁相以及锁频检测器之间,用于将所述的输出信号分频;
其中所述的分频器包含:
主锁存器;以及
从锁存器,包含多个数据输入端,所述的多个数据输入端的每一个耦接于所述的主锁存器的对应的数据输出端,以及多个数据输出端,交叉耦接于所述的主锁存器的多个对应的数据输入端;
其中,所述的主锁存器以及所述的从锁存器各包含:
一对互补金属氧化物半导体反相器,所述的这对互补金属氧化物半导体反相器中的一个包含电容,所述的电容耦接于提升晶体管的栅极以及下拉晶体管的栅极之间,所述的这对互补金属氧化物半导体反相器中的另一个包含另一电容,所述的另一电容耦接于另一提升晶体管的栅极以及另一下拉晶体管的栅极之间;
第一对N通道金属氧化物半导体晶体管,所述的第一对N通道金属氧化物半导体晶体管中的一个包含:源极,耦接于所述的下拉晶体管的漏极,栅极,接收所述的输出信号,以及漏极,经由串联连接的电阻以及电感耦接于供应电压,所述的第一对N通道金属氧化物半导体晶体管中的另一个包含:另一源极,耦接于所述的另一下拉晶体管的漏极,另一栅极,接收所述的输出信号,以及另一漏极,经由串联连接的另一电阻以及另一电感耦接于供应电压;
第二对N通道金属氧化物半导体晶体管,包含:一对源极,耦接于所述的另一下拉晶体管的漏极,一对栅极交叉耦接于所述的第一对N通道金属氧化物半导体晶体管的所述的这对应的漏极,以及,一对漏极,耦接于所述的多个电阻以及所述的多个电感之间的节点。
9.如权利要求8所述的频率合成器,其特征在于,所述的这对互补金属氧化物半导体反相器的提升晶体管为P通道金属氧化物半导体晶体管。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US91405007P | 2007-04-26 | 2007-04-26 | |
US60/914,050 | 2007-04-26 | ||
US11/952,423 US7605667B2 (en) | 2007-04-26 | 2007-12-07 | Frequency synthesizer with a harmonic locked phase/frequency detector |
US11/952,423 | 2007-12-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101295982A true CN101295982A (zh) | 2008-10-29 |
CN101295982B CN101295982B (zh) | 2011-03-16 |
Family
ID=39886234
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2008100860411A Active CN101295982B (zh) | 2007-04-26 | 2008-03-14 | 频率合成器 |
Country Status (3)
Country | Link |
---|---|
US (3) | US7605667B2 (zh) |
CN (1) | CN101295982B (zh) |
TW (1) | TWI344273B (zh) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102447467A (zh) * | 2010-10-12 | 2012-05-09 | 上海华虹Nec电子有限公司 | 可下拉电流io电路 |
CN102055543B (zh) * | 2009-11-05 | 2013-03-27 | 博通集成电路(上海)有限公司 | 解调广播接收机 |
CN103023484A (zh) * | 2012-12-03 | 2013-04-03 | 无锡海威半导体科技有限公司 | 超低功耗键扫式状态选择电路 |
CN103762978A (zh) * | 2014-01-20 | 2014-04-30 | 东南大学 | 基于谐波混频的无分频器宽带低相噪频率合成器 |
CN107306133A (zh) * | 2016-04-18 | 2017-10-31 | 中芯国际集成电路制造(上海)有限公司 | 一种分频器及频率合成器 |
CN107771373A (zh) * | 2015-05-18 | 2018-03-06 | 高通股份有限公司 | 具有副本偏置的高速的ac耦合的基于反相器的缓冲器 |
CN110868207A (zh) * | 2019-10-30 | 2020-03-06 | 西安邮电大学 | 一种延时锁相环及其鉴相器电路 |
CN111629463A (zh) * | 2020-06-12 | 2020-09-04 | 深圳昂瑞微电子技术有限公司 | 一种振荡电路 |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7605667B2 (en) * | 2007-04-26 | 2009-10-20 | Mediatek Inc. | Frequency synthesizer with a harmonic locked phase/frequency detector |
JP2009296375A (ja) * | 2008-06-05 | 2009-12-17 | Toshiba Corp | デジタル制御発振器及びこれを用いた位相同期回路 |
US7961057B2 (en) * | 2008-08-28 | 2011-06-14 | Mediatek Singapore Pte Ltd | Voltage controlled oscillator |
US7808266B2 (en) * | 2008-12-31 | 2010-10-05 | Texas Instruments Incorporated | Method and apparatus for evaluating the effects of stress on an RF oscillator |
TWI384761B (zh) * | 2009-02-20 | 2013-02-01 | Sunplus Technology Co Ltd | Low jitter, wide operating frequency band and frequency synthesis system suitable for low voltage operation |
TWI473419B (zh) * | 2010-01-19 | 2015-02-11 | Ind Tech Res Inst | 倍頻器 |
US8928417B2 (en) * | 2012-05-07 | 2015-01-06 | Asahi Kasei Microdevices Corporation | High-linearity phase frequency detector |
US9692429B1 (en) | 2012-11-15 | 2017-06-27 | Gsi Technology, Inc. | Systems and methods involving fast-acquisition lock features associated with phase locked loop circuitry |
US9100167B2 (en) * | 2012-11-30 | 2015-08-04 | Broadcom Corporation | Multilane SERDES clock and data skew alignment for multi-standard support |
JP5966986B2 (ja) * | 2013-03-21 | 2016-08-10 | 富士通株式会社 | Pll回路及びpll回路における位相比較方法 |
US9438253B2 (en) * | 2014-06-03 | 2016-09-06 | Texas Instruments Incorporated | High speed current mode latch |
JP6350120B2 (ja) * | 2014-08-27 | 2018-07-04 | 富士通株式会社 | Pll回路、pll回路の制御方法、及び電子機器 |
US10891076B1 (en) | 2016-12-06 | 2021-01-12 | Gsi Technology, Inc. | Results processing circuits and methods associated with computational memory cells |
US10521229B2 (en) | 2016-12-06 | 2019-12-31 | Gsi Technology, Inc. | Computational memory cell and processing array device using memory cells |
US10854284B1 (en) | 2016-12-06 | 2020-12-01 | Gsi Technology, Inc. | Computational memory cell and processing array device with ratioless write port |
US10860320B1 (en) | 2016-12-06 | 2020-12-08 | Gsi Technology, Inc. | Orthogonal data transposition system and method during data transfers to/from a processing array |
US10847212B1 (en) | 2016-12-06 | 2020-11-24 | Gsi Technology, Inc. | Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers |
US11227653B1 (en) | 2016-12-06 | 2022-01-18 | Gsi Technology, Inc. | Storage array circuits and methods for computational memory cells |
US10847213B1 (en) | 2016-12-06 | 2020-11-24 | Gsi Technology, Inc. | Write data processing circuits and methods associated with computational memory cells |
US10770133B1 (en) | 2016-12-06 | 2020-09-08 | Gsi Technology, Inc. | Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits |
US10943648B1 (en) | 2016-12-06 | 2021-03-09 | Gsi Technology, Inc. | Ultra low VDD memory cell with ratioless write port |
US10777262B1 (en) | 2016-12-06 | 2020-09-15 | Gsi Technology, Inc. | Read data processing circuits and methods associated memory cells |
US10249362B2 (en) | 2016-12-06 | 2019-04-02 | Gsi Technology, Inc. | Computational memory cell and processing array device using the memory cells for XOR and XNOR computations |
US11023631B2 (en) * | 2017-09-25 | 2021-06-01 | Rezonent Corporation | Reduced-power dynamic data circuits with wide-band energy recovery |
US10236895B1 (en) * | 2017-12-19 | 2019-03-19 | Analog Bits Inc. | Method and circuits for fine-controlled phase/frequency offsets in phase-locked loops |
US10958272B2 (en) | 2019-06-18 | 2021-03-23 | Gsi Technology, Inc. | Computational memory cell and processing array device using complementary exclusive or memory cells |
US10930341B1 (en) | 2019-06-18 | 2021-02-23 | Gsi Technology, Inc. | Processing array device that performs one cycle full adder operation and bit line read/write logic features |
US10877731B1 (en) | 2019-06-18 | 2020-12-29 | Gsi Technology, Inc. | Processing array device that performs one cycle full adder operation and bit line read/write logic features |
US11362623B2 (en) * | 2019-12-03 | 2022-06-14 | Samsung Electronics Co., Ltd. | Voltage-controlled oscillator |
CN112953518B (zh) * | 2021-03-30 | 2024-05-14 | 南京中科微电子有限公司 | 一种用于超外差两级下变频接收机中的锁相环结构 |
CN113224492B (zh) * | 2021-04-19 | 2021-12-28 | 中国电子科技集团公司第二十九研究所 | 一种基于互感耦合的超宽带功分器芯片 |
CN113193867B (zh) * | 2021-04-22 | 2022-09-16 | 香港中文大学(深圳) | 一种兼容c波段和毫米波频段的本振锁相频率综合器 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3866137A (en) * | 1973-09-14 | 1975-02-11 | Motorola Inc | Phase locked frequency divider circuitry |
DE3171263D1 (en) * | 1980-12-12 | 1985-08-08 | Philips Electronic Associated | Phase sensitive detector |
US5015971A (en) * | 1989-12-22 | 1991-05-14 | Hughes Aircraft Company | Frequency agile microwave signal generator |
US5055800A (en) * | 1990-04-30 | 1991-10-08 | Motorola, Inc. | Fractional n/m synthesis |
US5053722A (en) * | 1990-12-20 | 1991-10-01 | Hughes Aircraft Company | Fault-tolerant, wideband radar microwave signal generator |
US5920235A (en) * | 1997-06-25 | 1999-07-06 | Northern Telecom Limited | Voltage controlled oscillator integrated circuit |
EP0903860A1 (en) * | 1997-09-17 | 1999-03-24 | Matsushita Electric Industrial Co., Ltd. | PLL frequency synthesizer |
US6553089B2 (en) | 2001-03-20 | 2003-04-22 | Gct Semiconductor, Inc. | Fractional-N frequency synthesizer with fractional compensation method |
TWI264876B (en) | 2001-03-21 | 2006-10-21 | Mediatek Inc | PLL frequency synthesizer |
DE10162263A1 (de) * | 2001-12-18 | 2003-07-10 | Infineon Technologies Ag | Induktives Bauteil |
JP4458754B2 (ja) * | 2003-03-04 | 2010-04-28 | 株式会社ルネサステクノロジ | L負荷差動回路 |
US6812802B1 (en) * | 2003-04-22 | 2004-11-02 | Freescale Semiconductor, Inc. | Method and apparatus for controlling a voltage controlled oscillator |
US20040251977A1 (en) * | 2003-06-12 | 2004-12-16 | Abdellatif Bellaouar | Low-current, area-efficient and flicker noise free bias CMOS voltage control oscillator |
US7075379B2 (en) * | 2003-07-23 | 2006-07-11 | Agency For Science, Technology And Research | Low supply-sensitive and wide tuning-range CMOS LC-tank voltage-controlled oscillator monolithic integrated circuit |
US7209017B2 (en) * | 2004-08-04 | 2007-04-24 | Via Technologies, Inc. | Symmetrical linear voltage controlled oscillator |
FI20055402A0 (fi) * | 2005-07-11 | 2005-07-11 | Nokia Corp | Induktorilaite monikaistaista radiotaajuista toimintaa varten |
US20070247237A1 (en) * | 2006-03-31 | 2007-10-25 | Broadcom Corporation | Technique for reducing capacitance of a switched capacitor array |
US7764127B2 (en) * | 2006-11-30 | 2010-07-27 | Qualcomm, Incorporated | High resolution digitally controlled oscillator |
US7605667B2 (en) * | 2007-04-26 | 2009-10-20 | Mediatek Inc. | Frequency synthesizer with a harmonic locked phase/frequency detector |
-
2007
- 2007-12-07 US US11/952,423 patent/US7605667B2/en active Active
-
2008
- 2008-03-07 TW TW097108152A patent/TWI344273B/zh not_active IP Right Cessation
- 2008-03-14 CN CN2008100860411A patent/CN101295982B/zh active Active
-
2009
- 2009-09-10 US US12/556,710 patent/US7965108B2/en active Active
-
2011
- 2011-05-11 US US13/105,131 patent/US20110210799A1/en not_active Abandoned
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102055543B (zh) * | 2009-11-05 | 2013-03-27 | 博通集成电路(上海)有限公司 | 解调广播接收机 |
CN102447467A (zh) * | 2010-10-12 | 2012-05-09 | 上海华虹Nec电子有限公司 | 可下拉电流io电路 |
CN102447467B (zh) * | 2010-10-12 | 2014-02-26 | 上海华虹宏力半导体制造有限公司 | 可下拉电流io电路 |
CN103023484A (zh) * | 2012-12-03 | 2013-04-03 | 无锡海威半导体科技有限公司 | 超低功耗键扫式状态选择电路 |
CN103762978A (zh) * | 2014-01-20 | 2014-04-30 | 东南大学 | 基于谐波混频的无分频器宽带低相噪频率合成器 |
CN107771373A (zh) * | 2015-05-18 | 2018-03-06 | 高通股份有限公司 | 具有副本偏置的高速的ac耦合的基于反相器的缓冲器 |
CN107771373B (zh) * | 2015-05-18 | 2021-02-12 | 高通股份有限公司 | 具有副本偏置的高速的ac耦合的基于反相器的缓冲器 |
CN107306133A (zh) * | 2016-04-18 | 2017-10-31 | 中芯国际集成电路制造(上海)有限公司 | 一种分频器及频率合成器 |
CN107306133B (zh) * | 2016-04-18 | 2021-01-26 | 中芯国际集成电路制造(上海)有限公司 | 一种分频器及频率合成器 |
CN110868207A (zh) * | 2019-10-30 | 2020-03-06 | 西安邮电大学 | 一种延时锁相环及其鉴相器电路 |
CN110868207B (zh) * | 2019-10-30 | 2023-04-28 | 西安邮电大学 | 一种延时锁相环及其鉴相器电路 |
CN111629463A (zh) * | 2020-06-12 | 2020-09-04 | 深圳昂瑞微电子技术有限公司 | 一种振荡电路 |
Also Published As
Publication number | Publication date |
---|---|
TW200843356A (en) | 2008-11-01 |
US7965108B2 (en) | 2011-06-21 |
TWI344273B (en) | 2011-06-21 |
US20090322432A1 (en) | 2009-12-31 |
US20080266002A1 (en) | 2008-10-30 |
US20110210799A1 (en) | 2011-09-01 |
US7605667B2 (en) | 2009-10-20 |
CN101295982B (zh) | 2011-03-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101295982B (zh) | 频率合成器 | |
Ding et al. | A 21-GHz 8-modulus prescaler and a 20-GHz phase-locked loop fabricated in 130-nm CMOS | |
US7961057B2 (en) | Voltage controlled oscillator | |
US8067987B2 (en) | Millimeter-wave wideband voltage controlled oscillator | |
WO2016118936A1 (en) | Phase frequency detector and accurate low jitter high frequency wide-band phase lock loop | |
Moghavvemi et al. | Recent advances in delay cell VCOs [application notes] | |
US8860511B2 (en) | Frequency divider and PLL circuit | |
Lee et al. | A wide-locking-range dual injection-locked frequency divider with an automatic frequency calibration loop in 65-nm CMOS | |
TWI381642B (zh) | 信號源裝置及用以產生一輸出信號之信號源裝置 | |
Krishna et al. | A low power fully programmable 1MHz resolution 2.4 GHz CMOS PLL frequency synthesizer | |
US9059686B2 (en) | Pseudo-CML latch and divider having reduced charge sharing between output nodes | |
Wang et al. | A 66–72 GHz divide-by-3 injection-locked frequency divider in 0.13-μm CMOS technology | |
Peng et al. | A 16-GHz Triple-Modulus Phase-Switching Prescaler and Its Application to a 15-GHz Frequency Synthesizer in 0.18-$\mu $ m CMOS | |
Bagheri et al. | An ultra‐low power and low jitter frequency synthesizer for 5G wireless communication and IoE applications | |
US20130141178A1 (en) | Injection Locked Divider with Injection Point Located at a Tapped Inductor | |
Maity et al. | Design of a Low Power High Speed CML-Based Divide-by-5 Pre-Scaler in 180 nm Process Technology | |
US9397644B2 (en) | Frequency doubler | |
Plessas et al. | A 60-GHz quadrature PLL in 90nm CMOS | |
Chen et al. | A 29.5 to 31.7 GHz PLL in 65 nm CMOS technology | |
US7898304B2 (en) | Multimode millimeter-wave frequency divider circuit with multiple presettable frequency dividing modes | |
Mohamed et al. | A 3.3-mW Low Phase Noise VCDL for Factorial Delay-Locked Loops | |
Akshay et al. | Design and Analysis of Phase Locked Loop for low power wireless applications | |
Li et al. | A 0.7 V 1.6 mW fractional-N synthesizers for BLE RF transceiver in 40nm CMOS | |
Elshazly et al. | 2 GHz 1V sub-mW, fully integrated PLL for clock recovery applications using self-skewing | |
Kang et al. | A 20-GHz integer-N frequency synthesizer for 60-GHz transceivers in 90nm CMOS |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |