CN101295691A - 半导体封装结构 - Google Patents

半导体封装结构 Download PDF

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CN101295691A
CN101295691A CNA2007101488949A CN200710148894A CN101295691A CN 101295691 A CN101295691 A CN 101295691A CN A2007101488949 A CNA2007101488949 A CN A2007101488949A CN 200710148894 A CN200710148894 A CN 200710148894A CN 101295691 A CN101295691 A CN 101295691A
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interpolater
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赵智杰
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Advanced Manufacturing Innovation Co
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体封装结构与其形成方法。半导体封装结构包括：内插器；第一多个接合垫，位于该内插器的一侧；半导体芯片；以及第二多个接合垫，位于该半导体芯片的一侧，其中第一多个接合垫与第二多个接合垫通过金属至金属连接来接合。本发明的优点包括能够减小介于半导体裸片与内插器间的连接间距，减低在半导体裸片上的应力，且由于使用含硅内插器，而增加了在裸片中形成应力敏感元件与零件的可行性。

Description

半导体封装结构
技术领域
本发明涉及一种集成电路工艺，且特别涉及电子封装工艺，尤其是裸片在内插器(interposer)上的连接。
背景技术
在集成电路的封装中，可使用内插器作为半导体裸片与封装零件空间转换的连接路径。例如，半导体裸片上紧密的接合垫会导致封装的困难，因此可用内插器来增加半导体裸片的间距。在此例子中，内插器的第一侧具有第一间距，且其相当于连接于其上的半导体裸片的间距。在第二侧的接合垫具有第二间距，以连接至封装衬底，其中第二间距大于上述第一间距。
图1显示包括内插器10与连接至内插器上的裸片12的传统封装结构。通常内插器包括衬底11，其一般由有机材料或陶瓷形成。金属连接14形成于介电层16中。通过介电层16中的路径，金属连接14将焊料凸块(solderbump)18的较大间距变成为焊料凸块20的较小间距。裸片12中可进一步包括穿透硅通孔(trough-silicon via，TSV)，以形成从焊料凸块20至裸片12的相反面的电性连接裸片。通过焊料凸块20，裸片12以倒装芯片封装(flip-chip)方式连接至内插器。
随着集成电路持续的缩小化(down-scaling)，凸块20的间距优选为与半导体裸片上的接合垫的间距一样小。现有的技术已可将穿透硅通孔22的间距缩小成约20μm。然而，对焊料凸块20间距的微小化来说仍存在瓶颈。目前，通过焊料凸块所制作的连接可达到的最小间距只有130μm，远大于穿透硅通孔22的间距。所以，穿透硅通孔技术的潜力未能得到完全利用。因此目前业界亟需一种新的连接技术。
发明内容
本发明提供一种半导体封装结构及其形成方法。半导体封装结构包括：内插器；第一多个接合垫，位于该内插器的一侧；半导体芯片；以及第二多个接合垫，位于该半导体芯片的一侧，其中该第一与第二多个接合垫通过金属至金属连接来接合。
上述半导体封装结构中，该内插器可包括硅。
上述半导体封装结构中，该内插器可包括多个穿透硅通孔。
上述半导体封装结构中，该第一多个接合垫可具有第一间距，且该穿透硅通孔可具有大于该第一间距的第二间距。
上述半导体封装结构中，该第一间距可小于约130μm。
上述半导体封装结构中，该第一间距可小于约50μm。
上述半导体封装结构中，该第一间距可小于约5μm。
上述半导体封装结构中，该第一与第二多个接合垫可各自包铜、铝或上述金属的组合。
上述半导体封装结构还可包括：界面接合层，介于该第一多个接合垫与该第二多个接合垫之间。
上述半导体封装结构中，该界面接合层的厚度可小于约1μm。
上述半导体封装结构还可包括：界面连接材料，位于该第一与第二多个接合垫的侧壁上，其中该第一多个接合垫与该第二多个接合垫具有物理性接触。
上述半导体封装结构还可包括：额外的芯片，位于该半导体芯片上。
本发明提供另一种半导体封装结构，包括：内插器；第一多个接合垫，位于该内插器的一侧；半导体芯片；以及第二多个接合垫，位于该半导体芯片的一侧。其中该第一与第二多个接合垫连接不需焊料凸块。
本发明又提供另一种半导体封装结构，包括：内插器，其包括含硅衬底；多个穿透硅通孔，位于该含硅衬底中；第一多个接合垫，与该多个穿透硅通孔连接，其中该第一多个接合垫位于内插器的第一侧上，且该第一多个接合垫具有第一间距；第二多个接合垫，位于该内插器的相对于该第一侧的一侧上。该第二多个接合垫具有小于该第一间距的第二间距；该半导体封装结构还包括半导体芯片，该半导体芯片包括连接至该第二多个接合垫的第三多个接合垫，其中该第二与第三多个接合垫通过金属至金属连接来接合。
上述半导体封装结构中，该第二与第三多个接合垫可通过铜至铜连接来接合。
上述半导体封装结构还可包括：界面接合层，介于该第一与第二多个接合垫之间，其中该界面接合层的厚度小于1μm。
本发明还提供一种形成半导体封装结构的方法，包括：提供内插器；在该内插器的一侧形成第一多个接合垫；提供半导体芯片；在该半导体芯片的一侧形成第二多个接合垫；以及通过金属至金属连接来接合该第一与第二多个接合垫。
本发明还提供另一种形成半导体封装结构的方法，包括：提供内插器，其包括含硅衬底；在该含硅衬底中形成多个穿透硅通孔；在该含硅衬底上形成金属图形，其中该金属图形连接至该穿透硅通孔；以及形成第一多个接合垫，该第一多个接合垫连接至该金属图形。该方法还包括：提供半导体芯片；以及连接该第一与第二多个接合垫。该第一与第二多个接合垫之间的连接不需焊料凸块。
本发明的优点包括能够减小介于半导体裸片与内插器间的连接间距，与减低在半导体裸片上的应力，且由于使用含硅内插器，而增加了在裸片中形成应力敏感元件与零件的可行性。
为了让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举优选实施例，并配合附图，进行详细说明。
附图说明
图1显示一传统封装结构，其中裸片通过焊料凸块连接至内插器之上。
图2显示制造本发明一实施例的中间工艺剖面图，其中显示提供内插器。
图3显示制造本发明一实施例的中间工艺剖面图，其中显示形成介电层。
图4显示制造本发明一实施例的中间工艺剖面图，其中显示接合垫的形成。
图5A显示制造本发明一实施例的中间工艺剖面图，其中显示接合垫延伸高出介电层。
图5B显示制造本发明一实施例的中间工艺剖面图，其中显示在露出的接合垫的表面上视需要形成界面接合层。
图6A显示制造本发明一实施例的中间工艺剖面图，其中显示半导体芯片连接至内插器之上。
图6B显示制造本发明一实施例的中间工艺剖面图，其中显示只形成接合垫，而省略穿透硅通孔。
图7A显示制造本发明一实施例的中间工艺剖面图，其中显示半导体芯片连接至内插器之上。
图7B显示制造本发明一实施例的中间工艺剖面图，其中显示半导体芯片堆叠在内插器上。
其中，附图标记说明如下：
10～内插器
11～衬底
12～裸片
14～金属连接
16～介电层
18、20～焊料凸块
22～穿透硅通孔
30～内插器
32～含硅衬底
34、52～穿透硅通孔
36～焊料凸块
P1～穿透硅通孔34与焊料凸块36的间距
38～金属图案
40、44～介电层
41～有源或无源元件
42、54、56～接合垫
46～开口
P2～开口46的间距
48、58～界面接合层
50、60～半导体芯片
P3～接合垫54的间距
具体实施方式
图2显示内插器30。在一优选实施例中，内插器30为含硅内插器，包括含硅衬底32。优选为含硅衬底32的厚度小于约750μm，且更优选为小于150μm。在一实施例中，衬底32包括常用的材料，例如无机材料、有机材料、陶瓷或上述材料的多层材料。被指定连接于内插器30上的半导体芯片(在本技术领域中也称裸片)，通常形成在硅衬底上。含硅内插器30与半导体芯片的热膨胀系数(coefficient of thermal expansion，CTE)差异不大，因此由于热膨胀系数失配(mismatch)而产生的应力可显著减少。更进一步而言，可采取现有的硅工艺技术形成含硅内插器，这不仅可靠度高，且在高容量制造(high volume production)的能力上也成熟。
内插器30包括穿透硅通孔34，或者也称为穿透晶片通孔(through-wafervias)34。在内插器30的一表面上形成焊料凸块36，且焊料凸块36连接至穿透硅通孔34。焊料凸块36的间距P1(其中间距P1也是穿透硅通孔34的间距)优选大于约130μm，虽然其在实际设计中可以较大或是较小。穿透硅通孔34的另一端连接至金属图案38，金属图案38包括金属线与导孔。金属图案38形成在介电层40中。
由于使用含硅衬底32，因此可利用一般在集成电路中形成内连线的方法来形成金属图案38。在一实施例中，金属图案38是由金属，例如铜、铝、钨、钛或上述金属的结合形成的。优选的形成步骤包括沉积金属层，并蚀刻掉不需要的部分后留下金属图案38。或者可使用公知的镶嵌工艺来形成金属图案38。
内插器30可以轻易地定制以配合不同的需求。在一实施例中，将有源或无源元件41嵌入内插器中，其中元件41可包括阻抗匹配(impedancematching)线或板、电容器、电阻器与其类似物。
接下来，形成接合垫42。图3至图5B显示形成接合垫42的一实施例。图3显示形成介电层44。介电层44可为保护层，包括致密的介电材料，例如氧化物或氮化硅。在介电层44中形成开口46，开口46露出下方金属图案38。开口46的间距P2优选小于焊料凸块36的间距P1。在一实施例中，间距P2小于约130μm。在另一实施例中，间距P2小于约100μm。又在另一实施例中，间距P2小于约50μm或更小。
图4显示接合垫42的形成。首先，如图3所示，通过例如电镀，将金属材料填入开口46。若需要的话，可形成扩散阻障层和/或粘着层(图中未示)，其可包括钛、钨、钽或上述金属的氮化物。在一优选实施例中，金属材料包括铜或铜合金。在其他实施例中，可使用铝与钽。之后可执行化学机械研磨(chemical mechanical polish，CMP)来除去多余的金属材料，而留下接合垫42。之后执行回蚀(etch back)以使得介电层44的表面凹陷，从而让接合垫42延伸高出介电层44之上，如图5A所示。
如图5B所示，在露出的接合垫42的表面上视需要形成界面接合层(interfacial bonding layer)48。在一实施例中，界面接合层48包括金属元素材料，例如锡、金或上述金属的合金。在另一实施例中，界面接合层48包括合金，含有例如铟、锡、金、铜、铋或上述金属的组合。界面接合层48的厚度优选为小于约5μm。形成方法包括一般使用的沉积方法，例如化学气相沉积、物理气相沉积、溅射、等离子体增强气相沉积、电镀和/或其他转移技术包括真空、等离子体、电子化学、机械、热与光学辅助的方法。在一优选实施例中，界面接合层48顺应性形成在接合垫42露出的表面，以形成实质上均匀的薄膜。在其他实施例中，界面接合层48并非顺应性形成的，且可具有球形与半球形的形状。
图6A显示半导体芯片50，其连接至内插器30之上。半导体芯片50优选包括集成电路(图中未示)。在半导体芯片50的衬底中形成穿透硅通孔52。穿透硅通孔52的间距小于内插器30中的穿透硅通孔34的间距。在半导体芯片50的相反面上形成接合垫54与56。如图6B所示，在一实施例中只形成接合垫54，而省略穿透硅通孔。
接合垫54实质上与接合垫42包括相同的材料，且可利用实质上相同的方法来形成。接合垫54的间距P3与接合垫42的间距P2相同(见图3与图4)。界面接合层58包括与界面接合层48实质上相同的材料，可在接合垫54之上视需要而形成。
在连接工艺之前，对接合垫42与56或相对应的界面接合层48与58(见图5A至图6B)执行氧化物除去工艺以除去原生金属氧化层。利用一般使用的方法，例如等离子体或溅射蚀刻来执行氧化物除去工艺。或者可使用热工艺，例如低压的热压(thermal compression)工艺。通过增加温度与压力可减少原生金属氧化物层。例如，以约20-50psi的接触压力与约300-400℃的温度可执行铜-铜连接。
图7A中，利用金属-金属直接连接将接合垫42接合至接合垫54，而将半导体芯片50连接至内插器30之上。在金属至金属连接工艺中，可施加高压，例如10-100psi。连接温度优选为约300-500℃，其可通过红外线或电阻加热来提供。通过热-超声波(thermal-ultrasonic)工艺，也可在热-超声波环境下执行连接工艺。可了解的是，所需的压力和温度与接合垫42、54或相对应的界面接合层48、58的材料相关。优选的是，界面接合层48与58中的锡、金或焊接材料可降低所需的连接压力和/或温度。例如在连接工艺中，CuSn共熔合金(eutectic)界面接合层只需约227℃，而以含金的粘合层48和/或58可在室温执行金冷焊接(gold cold weld)。
连接温度低于接合垫42与56的液体温度或熔化温度，但可高于(以将界面接合层回焊(reflow))或低于界面接合层48与58的熔化温度。在此实施例中，在连接工艺中回焊界面接合层48和/或58，由于压力是温和地施加的，熔化的界面粘合材料不会被压向旁边，且位于它们之间的界面合金材料可以作为合金薄层将接合垫42连接至接合垫54。界面接合层48和/或58可能为非常薄的膜层，例如在连接后小于1μm。
图7B显示半导体芯片50与60堆叠在内插器30上。或者，首先将半导体芯片50连接于内插器30之上，之后再将半导体芯片60连接至半导体芯片50之上。本领域技术人员应可了解相对应的连接工艺步骤。若需要的话，可将更多裸片连接于半导体芯片60之上。
虽然在图示的实施例中，半导体芯片50与60为背面至正面(back to face)连接，但本领域技术人员也可使用正面至正面(face to face)连接。
本发明实施例具有许多优点。在半导体芯片与内插器间的连接为金属至金属连接的情况下，与使用焊料凸块的连接间距相比，可大幅减少接合垫的间距。使用焊料凸块的连接间距不会比50μm小太多，但本发明实施例的间距可减少至约5μm或更小。此外，由于使用含硅内插器，所以内插器与位于其上的半导体芯片具有相同的热膨胀系数。且因此可减低甚至消除热膨胀所产生的应力。
虽然本发明已以优选实施例公开如上，然而以上公开内容并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，应可作一定的改动与修改，因此本发明的保护范围应以所附权利要求为准。

Claims (15)

1.一种半导体封装结构，包括：
内插器；
第一多个接合垫，位于所述内插器的一侧；
半导体芯片；以及
第二多个接合垫，位于所述半导体芯片的一侧，其中所述第一与第二多个接合垫是通过金属至金属连接来接合的。
2.如权利要求1所述的半导体封装结构，其中所述内插器包括硅。
3.如权利要求1所述的半导体封装结构，其中所述内插器包括多个穿透硅通孔。
4.如权利要求3所述的半导体封装结构，其中所述第一多个接合垫具有第一间距，且所述穿透硅通孔具有大于所述第一间距的第二间距。
5.如权利要求4所述的半导体封装结构，其中所述第一间距小于约130μm。
6.如权利要求4所述的半导体封装结构，其中所述第一间距小于约50μm。
7.如权利要求4所述的半导体封装结构，其中所述第一间距小于约5μm。
8.如权利要求1所述的半导体封装结构，其中所述第一与第二多个接合垫各自包铜、铝或上述金属的组合。
9.如权利要求1所述的半导体封装结构，还包括：界面接合层，介于所述第一多个接合垫与所述第二多个接合垫之间。
10.如权利要求9所述的半导体封装结构，其中所述界面接合层的厚度小于约1μm。
11.如权利要求10所述的半导体封装结构，还包括：界面连接材料，位于所述第一与第二多个接合垫的侧壁上，其中所述第一多个接合垫与所述第二多个接合垫具有物理性接触。
12.如权利要求1所述的半导体封装结构，还包括：额外的芯片，位于所述半导体芯片上。
13.一种半导体封装结构，包括：
内插器，其包括：
含硅衬底；
多个穿透硅通孔，位于所述含硅衬底中；
第一多个接合垫，与所述多个穿透硅通孔连接，其中所述第一多个接合垫位于所述内插器的第一侧上，且所述第一多个接合垫具有第一间距；
第二多个接合垫，位于所述内插器相对于所述第一侧的一侧上，其中所述第二多个接合垫具有第二间距，所述第二间距小于所述第一间距；以及
半导体芯片，包括第三多个接合垫，所述第三多个接合垫连接至所述第二多个接合垫，其中所述第二与第三多个接合垫是通过金属至金属连接来接合的。
14.如权利要求13所述的半导体封装结构，其中所述第二与第三多个接合垫是通过铜至铜连接来接合的。
15.如权利要求13所述的半导体封装结构，还包括：界面接合层，介于所述第一与第二多个接合垫之间，其中所述界面接合层的厚度小于1μm。
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