CN103094138B - 具有增强的铜对铜接合的三维(3d)集成电路及其形成方法 - Google Patents

具有增强的铜对铜接合的三维(3d)集成电路及其形成方法 Download PDF

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CN103094138B
CN103094138B CN201210433490.5A CN201210433490A CN103094138B CN 103094138 B CN103094138 B CN 103094138B CN 201210433490 A CN201210433490 A CN 201210433490A CN 103094138 B CN103094138 B CN 103094138B
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device wafer
another
bond pad
adhesion layers
metal adhesion
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CN103094138A (zh
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S·V·源
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Core Usa Second LLC
GlobalFoundries Inc
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International Business Machines Corp
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]

Abstract

本发明公开涉及具有增强的铜对铜接合的三维（3D）集成电路及其形成方法。至少在第一器件晶片的Cu表面上形成至少一个金属粘附层。具有另一Cu表面的第二器件晶片被放置在第一器件晶片的Cu表面顶上且在至少一个金属粘附层上面。第一器件晶片和第二器件晶片然后被接合在一起。接合包含在施加或不施加外部施加的压力的情况下在低于400°C的温度下加热器件晶片。在加热期间，两个Cu表面被接合在一起，并且至少一个金属粘附层从两个Cu表面得到氧原子，并且在Cu表面之间形成至少一个金属氧化物接合层。

Description

具有增强的铜对铜接合的三维(3D)集成电路及其形成方法
技术领域
本公开涉及半导体结构及其形成方法。尤其是，本公开涉及实现了改善的Cu-Cu接合的三维（3D）集成电路。
背景技术
为了应对当今的电子器件的规模要求，芯片设计人员和制造商不断尝试设计最佳地使可用的芯片空间最大化的电路设计。得到的设计常常扩展到几个不同平面。例如，一个这样的三维（3D）电路设计可包含按层叠配置取向的多个不同器件层。在另一例子中，3D电路设计可包含由多个器件层和通过层间垂直通路连接在一起的互连层构成的垂直叠层。
在典型的3D集成电路中，以背对背的方式层叠两个有源器件晶片。然后，通过使用出现Cu-Cu接合的热压缩，将两个有源器件晶片接合在一起。接合处理需要合理的高温和压力施加。在这种直接Cu-Cu接合中，在被接合在一起的Cu表面上形成CuO。在Cu表面上存在CuO增加了接合结构的电阻，并且降低了接合结构的可靠性，特别是粘附力(adhesion)。
因而，需要改善的用于将Cu表面接合在一起的方法，其中，避免在接合的Cu-Cu表面上形成CuO。
发明内容
至少在第一器件晶片的Cu表面（一般为Cu接合焊盘）上形成至少一个金属粘附层。具有另一Cu表面（一般为另一Cu接合焊盘）的第二器件晶片被放置在第一器件晶片的Cu表面顶上且在至少一个金属粘附层上。第一器件晶片与第二器件晶片然后被接合在一起。接合(bonding)包含在施加或不施加外部施加压力的情况下将器件晶片加热到低于400°C的温度。在加热期间，两个Cu表面被接合在一起，并且至少一个金属粘附层(metal adhesion layer)从两个Cu表面得到氧原子，并且在Cu表面之间形成至少一个金属氧化物接合层。
在本公开的一个方面中，提供一种形成三维（3D）集成电路的方法。本公开的方法包括提供至少包含Cu表面的第一器件晶片。然后，在Cu表面上形成金属粘附层。在金属粘附层上且在第一器件晶片的Cu表面顶上放置具有另一Cu表面的第二器件晶片。第一器件晶片和第二器件晶片在低于400°C的温度下被接合在一起。在接合期间，金属粘附层从两个Cu表面得到氧原子，并且在Cu表面与另一Cu表面之间形成金属氧化物接合层。
本公开的另一方面涉及一种三维（3D）集成电路。3D集成电路包括具有Cu表面的第一器件晶片和具有另一Cu表面的第二器件晶片的垂直叠层(vertical stack)，其中，金属氧化物接合层位于第一器件晶片的Cu表面与第二器件晶片的另一Cu表面之间。
附图说明
图1是以框图的形式示出可在形成3D集成电路时使用的本公开的各种处理步骤的示意图。
图2是示出可在本公开的一个实施例中使用的包含经构图的Cu接合焊盘的第一器件晶片的图示（通过横截面图）。
图3是示出至少在第一器件晶片的Cu接合焊盘上形成金属粘附层之后的图2的第一器件晶片的图示（通过横截面图）。
图4是示出包含被放置在图3所示的第一器件晶片顶上的至少一个其它Cu接合焊盘的第二器件晶片的图示（通过横截面图）。
图5是示出在低于400°C的温度下进行接合之后的图4的两个器件晶片的图示（通过横截面图）。
图6是示出从第二器件晶片去除把手基板(handle substrate)之后的图5的两个器件晶片的图示（通过横截面图）。
图7是示出可在本公开的一个实施例中使用的包含未经构图的Cu接合焊盘的第一器件晶片的图示（通过横截面图）。
图8是示出在第一器件晶片的未经构图的Cu接合焊盘上形成金属粘附层之后的图7的第一器件晶片的图示（通过横截面图）。
图9是示出包含被放置在图8所示的第一器件晶片顶上的至少一个其它Cu接合焊盘的第二器件晶片的图示（通过横截面图）。
图10是示出在低于400°C的温度下进行接合之后的图9的两个器件晶片的图示（通过横截面图）。
图11是示出从第二器件晶片去除把手基板之后的图10的两个器件晶片的图示（通过横截面图）。
图12是示出可在本公开的另一实施例中使用的均包含经构图的Cu接合焊盘的两个器件晶片的图示（通过横截面图）。
图13是示出在器件晶片中的至少一个的经构图的Cu接合焊盘上形成至少一个金属粘附层之后的图12的两个器件晶片的图示（通过横截面图）。
图14是示出将器件晶片中的一个旋转180°并使器件晶片中的一个的经构图的Cu接合焊盘与另一器件晶片的经构图的Cu接合焊盘对准之后的图13的两个器件晶片的图示（通过横截面图）。
图15是示出在低于400°C的温度下进行接合之后的图14的两个器件晶片的图示（通过横截面图）。
图16是示出除了在形成金属粘附层时使用选择性沉积处理以外可通过使用图2～6所示的基本处理步骤形成的3D集成电路的图示（通过横截面图）。
图17是示出除了在形成金属粘附层时使用选择性沉积处理以外可通过使用图12～15所示的基本处理步骤形成的3D集成电路的图示（通过横截面图）。
具体实施方式
现在，通过参照伴随本申请的以下的讨论和附图，更详细地描述涉及具有改善的Cu-Cu接合(Cu-to-Cu bonding)的三维（3D）集成电路及其形成方法的本公开。注意，提供本申请的附图是出于解释性的目的，因而，它们的绘制没有按比例。
在以下描述中，为了使得能够彻底地理解本发明，阐述大量的特定细节，诸如特定的结构、部件、材料、尺度、处理步骤和技术。但是，本领域技术人员可以理解，可通过没有这些特定细节的可行的替代性的处理选项实施本公开。在其它实例中，为了避免混淆本公开的各种实施例，不详细描述公知的结构或处理步骤。
可以理解，当作为层、区域或基板的要素被称为处于另一要素“上”或“之上”时，它可直接处于其它要素上，或者，也可存在介入的要素。相反，当要素被称为“直接”处于另一要素“上”或“之上”时，则不存在介入的要素。还应理解，当要素被称为处于另一要素“下”或“之下”时，它可直接处于其它要素下或者之下，或者，可存在介入的要素。相反，当要素被称为“直接”处于另一要素“下”或“之下”时，则不存在介入的要素。
如上所述，本公开提供形成三维（3D）集成电路的方法。在图1所示的框图中示意性地表示出本公开的方法。本公开的方法包括提供包含Cu表面的第一器件晶片（步骤100）。然后，至少在第一器件晶片的Cu表面上形成金属粘附层（步骤102）。在金属粘附层上且在第一器件晶片的Cu表面顶上放置具有另一Cu表面的第二器件晶片（步骤104）。第一器件晶片和第二器件晶片在低于400°C的温度下接合在一起（步骤106）。在接合期间，金属粘附层从两个Cu表面得到氧原子，并且在第一器件晶片的Cu表面与第二器件晶片的另一Cu表面之间形成金属氧化物接合层。
本公开的方法提供了包括第一器件晶片和第二器件晶片的垂直叠层的三维（3D）集成电路，第一器件晶片包含Cu表面而第二器件晶片包含另一Cu表面，其中金属氧化物接合层位于第一器件晶片的Cu表面与第二器件晶片的另一Cu表面之间。金属氧化物接合层在不增加Cu-Cu接合表面上的电阻的情况下在不同的器件晶片之间提供改善的Cu-Cu接合。
在本公开中使用的术语“器件晶片(device wafer)”表示包含以下的半导体结构：半导体基板、至少部分地位于半导体基板上的至少一个器件、包含具有嵌入其中的至少一个导电特征件（通路和/或线）的至少一个互连电介质材料的互连级和位于互连级的表面上并与位于至少一个互连电介质材料内的导电特征件中的至少一个接触的Cu接合焊盘(bond pad)。在一些实施例中，Cu接合焊盘可被构图，并由此仅位于互连级的一些部分上。在其它实施例中，Cu接合焊盘可不被构图，并由此位于整个互连级顶上。
至少一个器件可以是场效应晶体管、电阻器、电容器、BiCMOS、二极管、导体、微机电（MEM）器件、热冷却器件或它们的任意组合。器件可具有相同或不同的极性，并且器件可具有相同或不同的功能。例如，器件可被用作存储器、微处理器、微控制器、传感器、热冷却器件或这些功能的任意组合。
首先参照示出本公开的一个实施例的图3～6，该实施例用于通过使用本公开的方法制备3D集成电路。注意，虽然以下的讨论和附图描述和示出了将两个器件晶片垂直层叠和接合在一起，但是，本公开不限于将仅仅两个器件晶片垂直层叠和接合在一起。事实上，本公开可被用于通过使用本公开的方法将n个器件晶片垂直层叠和接合在一起的实施例中，其中，n是大于2的整数。
首先参照图2，示出了包含位于互连级26顶上的经构图的Cu接合焊盘30的第一器件晶片10。第一器件晶片10还包含至少一个第一器件18，第一器件18至少部分地位于具有位于其中的至少一个隔离区域14的半导体基板12的表面上。在附图和以下讨论中，至少一个第一器件18是场效应晶体管，其包含至少栅极电介质20和重叠的栅极导体22的栅极叠层。至少一个间隔件24可位于栅极叠层（20和22）的侧壁上。源极/漏极区域16L和16R被示出在栅极叠层（20和22）的足迹处，并且位于半导体基板12的上部内。
互连级26包含具有位于其中的多个导电特征件28L、28R的至少一个互连电介质材料27。如所示的那样，多个导电特征件中的导电特征件28L中的一个与场效应晶体管的源极/漏极区域16L接触，而多个导电特征件中的导电特征件28R中的另一个与场效应晶体管的源极/漏极区域16R接触。如所示的那样，导电特征件268具有与在互连级26顶上形成的经构图的Cu接合焊盘30中的一个的表面接触的导电区域，即通路29。
可通过利用本领域技术人员公知的技术形成图2所示的第一器件晶片10。并且，第一器件晶片10的各种部件可由本领域技术人员也公知的材料构成。
以下，关于可如何制作第一器件晶片10以及可存在于第一器件晶片10内的部件中的每一个的一些材料提供一些细节。虽然提供这些细节，但是在形成图2所示的第一器件晶片10时，可以使用本领域技术人员公知的其它方法和/或材料。
第一器件晶片10的半导体基板12可包含任何半导体材料，该半导体材料包含但不限于Si、Ge、SiGe、SiC、SiGeC、GaAs、GaN、InAs、InP和所有其它III/V或II/VI化合物半导体。半导体基板12也可包含有机半导体或诸如Si/SiGe、绝缘体上硅（SOI）、绝缘体上的SiGe（SGOI）或绝缘体上锗（GOI）的分层半导体。绝缘体上半导体基板从上到下包含顶部半导体器件层、绝缘体层和底部半导体部分。在本公开的一些实施例中，半导体基板12由含Si半导体材料（即包含硅的半导体材料）构成。半导体基板12可被掺杂、不被掺杂或者在其中包含掺杂或未掺杂的区域。半导体基板12可包含单晶取向，或者它可包含不同的晶体取向。出于解释的目的，第一器件晶片的半导体基板12包含块体半导体(bulk semiconductor)。“块体(bulk)”意味着整个基板由半导体材料构成。
半导体基板12还可包含第一掺杂（n-或p-）区域和第二掺杂（n-或p-）区域。为了清楚，在本申请的附图中的任一个中没有特别示出掺杂区域。第一掺杂区域和第二掺杂区域可以相同，或者它们可具有不同的导电性和/或掺杂浓度。这些掺杂区域被称为“阱”，并且通过利用常规的离子注入过程来形成它们。
至少一个隔离区域14可形成于半导体基板12中。至少一个隔离区域14可以是沟槽隔离区域或场氧化物隔离区域。通过使用本领域技术人员公知的沟槽隔离处理来形成沟槽隔离区域。例如，可在形成沟槽隔离区域时对沟槽的光刻(lithography)、蚀刻和用沟槽电介质对沟槽的填充。任选地，可在沟槽填充之前在沟槽中形成衬里(liner)，可在沟槽填充之后执行致密化步骤，并且平坦化处理也可跟随在沟槽填充之后。可通过使用所谓的局部硅氧化处理来形成场氧化物。本领域技术人员了解，至少一个隔离区域14在相邻的器件之间提供隔离，当相邻的器件具有相反的导电性（即nFET和pFET）时一般需要这种隔离。这里，半导体基板12的位于相邻的隔离区域之间的部分被称为半导体基板12的“有源区域”。半导体基板12的有源区域是器件至少部分地形成在其上的区域。
在限定要形成器件的有源区域之后，至少部分地在半导体基板12的有源区域上形成器件。在附图中，如前面提到的那样，在本示出实施例中形成的至少一个第一器件18是场效应晶体管。场效应晶体管包含至少栅极电介质20和栅极导体22的栅极叠层。
栅极电介质20包含任意绝缘材料。在一个实施例中，栅极电介质20包含半导体氧化物、半导体氮化物和/或半导体氧氮化物。在另一实施例中，栅极电介质20包含介电常数比氧化硅的介电常数（例如，3.9）大的电介质金属氧化物。这里，这种具有比氧化硅大的介电常数的电介质金属氧化物被称为高k电介质材料。一般地，可在本公开中使用的高k栅极电介质具有比4.0大的介电常数，大于8.0的介电常数是更典型的。可用作栅极电介质20的示例性的高k电介质材料包含但不限于HfO2、ZrO2、La2O3、Al2O3、TiO2、SrTiO3、LaAlO3、Y2O3、HfOxNy、ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、SrTiOxNy、LaAlOxNy、Y2OxNy、它们的硅酸盐(silicate)和它们的合金。x的每个值独立地为0.5～3，并且y的每个值独立地为0～2。在一些实施例中，可以使用上述电介质材料中的至少两种的多层叠层。例如，在一个实施例中，栅极电介质20可包含半导体氧化物，即氧化硅，的下层和诸如例如HfO2的高k电介质材料的上层。
栅极电介质20的厚度可根据其形成技术而改变。但是，一般地，栅极电介质20具有0.5nm～10nm的厚度，1.0nm～5nm的厚度是更典型的。在本公开的一些实施例中，使用的栅极电介质20可具有大约1nm或更小的有效氧化物厚度。
可通过包括例如化学气相沉积（CVD）、物理气相沉积（PVD）、分子束沉积（MBD）、脉冲激光沉积（PLD）、液体源模糊化学沉积（LSMCD）、原子层沉积（ALD）和其它类似的沉积处理的在本领域中公知的方法形成栅极电介质20。在一些实施例中，特别是当使用半导体氧化物、氮化物和/或氧氮化物作为栅极电介质20时，可通过诸如例如热氧化和/或热氮化的热工艺形成栅极电介质20。在这种实例中，半导体氧化物、氮化物和/或氧氮化物的半导体部分包含与底层的半导体基板12相同的半导体材料。
在图2中示出的至少一个第一器件18（即场效应晶体管）的栅极叠层的栅极导体22包含任意的导电材料，这些导电材料包含但不限于多晶硅、多晶硅锗、元素金属（例如，钨、钛、钽、铝、镍、钌、钯和铂）、至少两种元素金属的合金、元素金属氮化物（例如，氮化钨、氮化铝和氮化钛）、元素金属硅化物（例如，硅化钨、硅化镍和硅化钛）和它们的多层。在一个实施例中，栅极导体22包含nFET金属。在另一实施例中，栅极导体22包含pFET金属。在又一实施例中，栅极导体22包含具有或不具有底层的导电金属部分的多晶硅。
可利用包括例如化学气相沉积（CVD）、等离子增强化学气相沉积（PECVD）、蒸镀、物理气相沉积（PVD）、溅射、化学溶液沉积、原子层沉积（ALD）和其它类似沉积处理的常规沉积处理来形成栅极导体22。当使用含硅材料作为栅极导体22时，可通过利用原位掺杂沉积处理或通过利用沉积以及随后的诸如将适当的杂质引入含Si材料中的离子注入或气相掺杂的步骤，在适当的杂质内掺杂含Si材料。当形成金属硅化物时，可以使用常规的硅化处理。
在一些实施例中，栅极电介质20和栅极导体22可形成为覆盖层，然后在形成包含它们的栅极叠层时使用构图处理。构图处理包含光刻（在栅极导体22的上表面顶上施加光刻胶，将光刻胶暴露于放射线并且通过使用常规显影剂显影露出的抗蚀剂）。光刻步骤在栅极导体22的覆盖层顶上提供经构图的光刻胶。然后使用蚀刻步骤以将图案从经构图的光刻胶转印到栅极电介质和栅极导体材料的底层覆盖层中。蚀刻可包含诸如例如反应离子蚀刻、等离子蚀刻、离子蚀刻或激光烧蚀的干蚀刻处理。蚀刻还可包含湿化学蚀刻处理，在该处理中使用一种或更多种化学蚀刻剂以去除栅极电介质和栅极导体材料的覆盖层的未被经构图的光刻胶保护的部分。可通过利用灰化处理去除经构图的光刻胶。
在其它实施例中，通过使用替代栅极处理形成包含栅极电介质20和栅极导体22的栅极叠层。在这种处理中，至少包含牺牲栅极材料的叠层形成于存在于平坦化的电介质材料中的开口中。至少牺牲栅极材料被去除，然后被上述的栅极导电材料中的一种替代。在一些实施例中，替代栅极处理也可包含牺牲栅极电介质材料。在这种实施例中，牺牲栅极材料和牺牲栅极电介质均被去除，并且被上述的栅极导体材料中的一种和上述的栅极电介质材料中的一种替代。
示为至少一个第一器件18的场效应晶体管还可包含至少一个间隔件(spacer)24。在一些实施例中，可从至少包含栅极电介质20和栅极导体22的栅极叠层的侧壁省略至少一个间隔件24。当存在时，至少一个间隔件24包含诸如例如氧化硅、氮化硅和/或氧氮化硅的氧不可渗透的电介质材料。可通过氧不可渗透的电介质材料的沉积以及随后通过蚀刻，形成至少一个间隔件24。在一些实施例中，可在形成至少一个间隔件24时使用热处理。
图2所示的场效应晶体管（即，至少一个第一器件18）还包含源极/漏极区域16L和16R。可通过利用离子注入和退火在形成包含栅极电介质20和栅极导体22的栅极叠层之前或之后形成源极/漏极区域16L和16R。用于离子注入处理的条件和掺杂剂对于本领域技术人员来说是公知的。激活被离子注入到半导体基板12中的掺杂剂的退火包含在高于800°C或更高的温度下加热。半导体基板12的位于栅极叠层（20和22）下面并沿横向由源极/漏极区域16L、16R划界的部分是晶体管的沟道区域。
在形成至少一个第一器件18之后，形成互连级(interconnect level)26。互连级26可代表单个互连级，或者它可代表多个垂直层叠且电连接的互连级。互连级26包含具有位于其中的多个导电特征件28L和28R的至少一个互连电介质材料27。多个导电特征件(conductivefeature)中的导电特征件28L中的一个与场效应晶体管的源极/漏极区域16L接触，而多个导电特征件中的导电特征件28L中的另一个与场效应晶体管的源极/漏极区域16R接触。导电特征件28R具有与在互连级26顶上形成的经构图的Cu接合焊盘30中的一个的表面接触的导电区域，即通路29。
通过使用包含例如镶嵌(damascene)处理的在本领域中公知的技术形成互连级26。在镶嵌处理中，首先形成至少一个互连电介质材料27，然后通过使用光刻和蚀刻将多个开口形成于至少一个互连电介质材料27中。多个开口可以是通路开口、线开口或通路开口和线开口的组合。当通过通路开口和线开口的组合限定开口时，可以使用光刻和蚀刻的第二迭代。在开口的这种组合中，通路和线相互连通。
然后用导电材料填充开口以形成导电特征件28L和28R。
在一些实施例中，可与导电特征件28L和28R同时形成导电区域29。在其它实施例中，可在导电特征件28L和28R之后形成导电区域29。在这种实施例中，导电特征件28L和28R每一个都具有基本上与第一互连电介质材料的上表面共面的最高表面。然后形成第二互连电介质材料（与第一互连电介质材料相同或不同），并且通过使用与上述的用于形成导电特征件28L和28R的技术相同的技术形成导电区域29。在该特定实施例中，第一和第二互连电介质材料形成可在本公开的一些实施例中使用的多级(multilevel)互连结构。
互连级26的至少一个互连电介质材料27可包含任何级间或级内电介质，其包含无机电介质或有机电介质。至少一个互连电介质材料27可以是多孔的或非多孔的。多孔电介质材料一般具有比非多孔相对物低的介电常数。可被用作至少一个互连电介质材料27的适当电介质的一些例子包含但不限于SiO2、乙基硅倍半环丙烷(silsesquixoanes)、包含Si、C、O和H原子的C掺杂氧化物（即，有机硅酸盐）、热硬化聚亚芳醚(polyarylene ether)或它们的多层。在本申请中使用术语“聚亚芳基(polyarylene)”以表示芳基部分或惰性替换的芳基部分，这些部分是通过接合、熔环或诸如例如氧、硫、砜、亚砜和碳酰基等的惰性连接基(inert linking group)连接在一起的。在一个实施例中，至少一个互连电介质材料27具有约4.0或更小的介电常数。在另一实施例中，至少一个互连电介质材料27具有约2.8或更小的介电常数。除非另外指出，否则，在本公开中提到的所有介电常数相对于真空的。至少一个互连电介质材料27的厚度可根据使用的电介质材料以及互连级26内的电介质的确切数量而改变。一般地，对于正常的互连结构，至少一个互连电介质材料27具有200nm～450nm的厚度。
导电特征件28L和28R以及导电区域29包含包含例如多晶硅、导电金属、包含至少两种导电金属的合金、导电金属硅化物或它们的组合的导电材料。在一个实施例中，在形成导电特征件28L和28R和导电区域29时使用的导电材料是诸如Cu、W或Al的导电金属。导电特征件28L和28R可包含与导电区域29相同或不同的导电材料。
通过利用包含但不限于CVD、PECVD、溅射、化学溶液沉积或电镀的常规沉积处理，形成在形成导电特征件28L和28R和导电区域29时使用的导电材料。在沉积之后，可以使用诸如例如化学机械抛光（CMP）的常规平坦化处理以提供平坦的互连结构。
首先，通过用以上提到的用于形成导电特征件28L和28R和导电区域29的导电材料的技术中的一种，在互连级26顶上形成Cu或Cu合金的覆盖层，在互连级26顶上形成经构图的Cu接合焊盘30。然后，在形成经构图的Cu接合焊盘30时使用光刻和蚀刻。如所示的那样，经构图的Cu接合焊盘30中的一个与导电区域29的上表面接触。虽然在本实施例中示出和描述了经构图的Cu接合焊盘30，但是，将描述使用未经构图的Cu接合焊盘的实施例。
现在参照图3，该图示出了至少在第一器件晶片10的Cu接合焊盘30上形成金属粘附层32之后的图2的第一器件晶片10。在本实施例中，通过利用诸如例如蒸镀、物理气相沉积、氩溅射、化学气相沉积、等离子增强化学气相沉积或原子层沉积的非选择性沉积处理，形成金属粘附层32。“非选择性”意味着在全部暴露表面上形成金属粘附层32的沉积处理。
金属粘附层32由与Cu或Cu合金相比对于氧具有更高的亲和力的金属或金属合金构成。换句话说，金属粘附层32由与Cu或Cu合金相比更易于起氧反应的金属或金属合金构成。特别地，金属粘附层32包含Mn、Ti、Co、Ta、W、Ru和Ni中的一种。在一个实施例中，金属粘附层32包含Mn或与Ti、Co、Ta、W、Ni和Ru中的至少一种合金化的Mn。在另一实施例中，金属粘附层32包含金属合金，其包含选自Mn、Ti、Co、Ta、W、Ni和Ru中的两种或更多种金属。
金属粘附层32的厚度可根据使用的金属或金属合金及其形成过程中所使用的处理条件而改变。在一个实施例中，金属粘附层32具有0.2nm～20nm的厚度。在另一实施例中，金属粘附层32具有0.5nm～50nm的厚度。在一些实施例中，金属粘附层32是单层材料。在另一实施例中，金属粘附层32包含多层。当使用多层时，多层结构内的每一金属粘附材料可以相同或不同。
现在参照图4，该图示出包含位于图3所示的第一器件晶片10顶上的经构图的Cu接合焊盘72的第二器件晶片50。第二器件晶片50包含半导体基板52，其包含半导体器件层52B和绝缘体层52A。半导体器件层52B包含以上针对半导体基板12提到的半导体材料中的一种。半导体器件层52B的厚度一般处于5nm～5000nm的范围内。在本公开中也可使用高于或低于上述的厚度范围的其它厚度。
绝缘体层52A包含半导体氧化物、半导体氮化物和/或半导体氧氮化物。绝缘体层52A的厚度一般处于5nm～500nm的范围内。在本公开中也可使用高于或低于上述的厚度范围的其它厚度。
在一个实施例中，绝缘体层52A和半导体器件层52B是绝缘体上半导体基板的部件，其中，在图4所示的第二器件晶片50的制造中去除基板的底部半导体部分。在这种实施例中，可通过蚀刻或通过利用诸如例如CMP和/或研磨的平坦化处理去除基板的底部半导体部分。一般在第二器件晶片50顶上形成把手基板(handle substrate)（或把手晶片(handle wafer)）之后进行绝缘体上半导体基板的底部半导体部分的去除。
在一些实施例中，在块体半导体基板被处理以包含至少一个器件、一个互连级或把手基板之后，在块体半导体基板（代表半导体器件层54）的底表面上形成半导体层52B。
半导体器件层52B包含在其中形成的至少一个隔离区域54。至少一个隔离区域54可被形成，并且包含以上针对至少一个隔离区域14描述的材料。
第二器件晶片50还包含至少部分地在半导体器件层52A顶上形成的至少一个第二器件58。在本实施例中，至少一个第二器件58是包含至少栅极电介质60和栅极导体62的栅极叠层的场效应晶体管。栅极电介质60和栅极导体62可被形成，并且包含以上针对栅极电介质20和栅极导体22描述的材料和厚度。
场效应晶体管（即，至少一个第二器件58）还包含位于半导体器件层52B内且在包含栅极电介质60和栅极导体62的栅极叠层的足迹上的源极/漏极区域56L和56R。可如以上针对形成源极/漏极区域16L和16R描述的那样形成源极/漏极区域56L和56R。半导体器件层52A的位于栅极叠层（60和62）下面并且沿横向由源极/漏极区域56L、56R划界的区域是至少一个第二器件58的沟道区域。
可在栅极叠层（即，60和62）的侧壁上存在至少一个间隔件63。至少一个间隔件63可包含以上针对至少一个间隔件24提到的材料中的一种。可通过使用与以上在形成至少一个间隔件24时提到的技术相同的技术形成至少一个间隔件63。
第二器件晶片50还包含互连级64，其包含位于至少一个互连电介质材料65内的多个导电特征件66L和66R。互连电介质材料65可被形成，并且包含以上针对互连电介质材料27提到的材料和厚度。导电特征件66L和66R可被形成，并且包含以上针对导电特征件28L和28R提到的材料。
在形成至少一个第二器件58和互连级64之后，在互连级64的最高表面上形成把手基板68。把手基板68可包含玻璃、Al2O3、SiN或诸如例如碳、旋涂有机/无机聚合物或柔性带的其它容易去除的绝缘材料。可通过利用包含层转印处理的本领域技术人员公知的常规技术形成把手基板68。
然后，如果存在的话，可如上面描述的那样去除绝缘体上半导体的底部部分，并且，如果不存在的话，可通过利用热生长或诸如例如CVD、PECVD或化学溶液沉积的沉积处理来形成绝缘体层52A。
然后，可通过半导体基板52并通过互连电介质材料65的至少一部分形成通路70。通路70的一个端部接触导电特征件中的至少一个，即66R，的水平表面，而另一端部位于基板52的最底表面上。
通路70包含以上针对导电特征件28L和28R提到的导电材料中的一种，并且通过利用光刻和蚀刻以及随后的在通过光刻和蚀刻处理产生的通路开口内形成导电材料来形成通路70。通路70的导电材料可包含以上针对导电特征件28L和28R提到的导电材料中的一种。可通过使用以上针对形成导电特征件28L和28R提到的技术中的一种形成通路70的导电材料。可以使用诸如CMP的平坦化处理以提供平坦的结构。
在形成通路70之后，在绝缘体层52A的表面上形成Cu接合焊盘72。如所示的那样，Cu接合焊盘72中的一个与通路70的端部接触。Cu接合焊盘72在本公开的本实施例中被构图。在一些实施例中，可以使用未经构图的Cu接合焊盘（未示出）。并且，在本公开的另一实施例中，可至少在Cu接合焊盘72的表面上形成另一金属粘附层。本实施例在本公开的附图中没有被示出。当至少在Cu接合焊盘72上形成另一金属粘附层时，另一金属粘附层可被形成，并且包含以上针对金属粘附层32提到的材料。另一金属粘附层可以是与金属粘附层32相同或不同的——一般是相同的——金属或金属合金。
参照图5，该图示出在使两个器件晶片10和50相互紧密接触、使两个晶片对准以使得每个Cu接合焊盘72的Cu表面位于每个Cu接合焊盘30的Cu表面顶上并且与其基本上垂直对准，并在低于400°C的温度下接合之后的图4的两个器件晶片10和50。在另一实施例中，在50°C～375°C的温度下进行接合。
在一些实施例中，可在接合处理期间向两个器件晶片施加外力，诸如由手或钳或其它类似的机构手段供给的力。在另一实施例中，在接合处理期间不向两个器件晶片施加外力。
可在对于两个器件晶片被接合在一起惰性的环境中执行接合。在一个实施例中，在包含例如He、Ar、Ne、Xe和其混合物的惰性气体中执行接合。在另一实施例中，氮气可被用作接合处理期间的环境。可以单独地使用氮气，或者使其与以上提到的惰性气体中的一种混合。在另一实施例中，可以使用形成气体（即，氢气（摩尔分数改变）和氮气的混合物）作为接合期间的环境。
在接合中，金属粘附层32的位于Cu接合焊盘上的部分从两个Cu表面得到氧原子，并且在Cu接合焊盘30的Cu表面与Cu接合焊盘72的另一Cu表面之间形成金属氧化物接合层74。因而，与在接合之前出现Cu接合焊盘相比，接合之后的Cu接合焊盘30和Cu接合焊盘72在其中具有更少的氧。根据使用的金属粘附层的类型和接合处理条件，在本公开中Cu接合焊盘30和Cu接合焊盘72中的每一个中的氧可减少50～99%。
金属氧化物接合层74由此包含金属或金属合金和氧。金属氧化物接合层74被示为位于Cu接合焊盘30的Cu表面与Cu接合焊盘72的Cu表面之间，并且与Cu接合焊盘30和Cu接合焊盘72的边缘垂直对准。金属氧化物接合层74具有一般处于0.3nm～100nm的范围内的厚度，根据初始金属粘附层厚度和初始加入Cu接合焊盘中的氧的数量，1nm～10nm的厚度是更典型的。在本公开中也可使用大于或小于上述的厚度范围的其它厚度。在一些实施例中，金属氧化物接合层74是单层结构。在其它实施例中，金属氧化物接合层74是多层结构。当金属氧化物接合层74是多层结构时，多层结构中的每一层可具有相同或不同的成分。
现在参照图6，该图示出从第二器件晶片50去除把手基板68之后的图5的接合后的两个器件晶片。在一个实施例中，可通过利用选择性蚀刻处理去除把手基板68，上述蚀刻处理诸如，例如，如果把手基板是基于碳氢化合物的，那么利用O2等离子，或者，如果把手基板是SiN，那么利用热磷酸。在另一实施例中，可以使用化学机械平坦化和/或研磨以从接合后的结构去除把手基板68。
可在图6所示的结构顶上层叠其它的器件晶片，并且可通过利用与上述相同的基本处理步骤实现其它器件晶片与接合后的结构之间的接合。因而，可形成包含相互垂直层叠的多个器件晶片的3D集成电路。
现在参照示出本公开的另一实施例的图7～11。除了使用未经构图的Cu接合焊盘以外，在图7～11中示出的本实施例与以上在图2～6中示出的实施例类似。
首先参照示出可在本公开的一个实施例中使用的包含未经构图的Cu接合焊盘80的第一器件晶片10的图7。特别地，除了图1的经构图的Cu接合焊盘30被未经构图的Cu接合焊盘80替代以外，第一器件晶片10包含与图2所示的第一器件晶片10相同的部件。通过利用以上针对形成经构图的Cu接合焊盘30提到的沉积处理，形成未经构图的Cu接合焊盘80。在沉积Cu接合焊盘的覆盖层之后，不进行覆盖Cu接合焊盘的构图。未经构图的Cu接合焊盘80的材料和厚度与以上针对经构图的Cu接合焊盘30提到的那些相同。
现在参照图8，其中示出在第一器件晶片的未经构图的Cu接合焊盘80上形成金属粘附层82之后的图7的第一器件晶片。金属粘附层82可被形成，并且包含以上针对金属粘附层32描述的材料和厚度。
参照图9，其中示出包含放置在图8所示的第一器件晶片10顶上的另一未经构图的Cu接合焊盘84的第二器件晶片50。除了经构图的Cu接合焊盘72被未经构图的Cu接合焊盘84替代以外，第二器件晶片50包含与以上提到的第二器件晶片50相同的元件。通过利用以上针对形成经构图的Cu接合焊盘30提到的沉积处理，形成未经构图的Cu接合焊盘84。在沉积Cu接合焊盘的覆盖层之后，不进行覆盖Cu接合焊盘的构图。未经构图的Cu接合焊盘84的材料和厚度与以上针对经构图的Cu接合焊盘30提到的那些相同。
现在参照图10，其中示出在低于400°C的温度下接合之后的图9的两个器件晶片。这里，对于形成图9所示的接合结构，也可使用结合形成图5所示的接合结构描述的接合处理的其它细节和实施例。与前面的实施例不同，金属氧化物接合层74邻接地存在于未经构图的Cu接合焊盘80与未经构图的Cu接合焊盘84之间。与前面的实施例类似，与接合之前的未经构图的Cu接合焊盘80与未经构图的Cu接合焊盘84相比，接合之后的未经构图的Cu接合焊盘80和未经构图的Cu接合焊盘84在其中具有更少的氧。
现在参照图11，其中示出从第二器件晶片50去除把手基板68之后的图10的两个接合的器件晶片。用于去除把手基板68的细节与在本公开的先前实施例中提到的细节相同。
可在图11所示的接合结构顶上层叠其它器件晶片，并且可通过利用与上述相同的基本处理步骤实现接合结构。因而，可形成包含相互垂直层叠的多个器件晶片的3D集成电路。
现在参照示出本公开的另一实施例的图12～15。本公开的本实施例从首先提供第一器件晶片10和第二器件晶片10′开始。第一器件晶片10的部件与存在于图2所示的第一器件晶片10中的部件类似。第二器件晶片10′的部件与以上针对图2所示的第一器件晶片10提到的部件相同。使用符号′以区分第二器件晶片10′的与第一器件晶片10的部件等同的部件。
现在参照图13，其中示出在器件晶片中的至少一个的经构图的Cu接合焊盘上形成至少一个金属粘附层32之后的图12的两个器件晶片10和10′。在一些实施例中，可在两个器件晶片上形成另一金属粘附层32。至少一个金属粘附层32与以上结合图3所示的结构提到的相同。
现在参照图14，其中示出在翻转(flip)器件晶片中的一个（即，器件晶片10′）并使第一器件晶片10的经构图的Cu接合焊盘30与第二器件晶片10′的经构图的Cu接合焊盘30′对准之后的图13的两个器件晶片10和10′。通过将器件晶片中的一个，即第二器件晶片10′，旋转180°，实现翻转。
参照示出在低于400°C的温度下接合之后的图14的两个器件晶片10和10′的图15。这里，对于形成图9所示的接合结构，也可使用结合形成图5所示的接合结构描述的接合处理的其它细节和实施例。
可在图14所示的接合结构顶上层叠其它器件晶片，并且可通过利用与上述的基本处理步骤相同的基本处理步骤，实现其它器件晶片与接合结构之间的接合。因而，可形成包含相互垂直层叠的多个器件晶片的3D集成电路。
现在参照图16，其中示出除了在形成金属粘附层时使用选择性沉积处理以外可通过使用图2～6所示的基本处理步骤形成的3D集成电路。因而，没有金属粘附层接触第一器件晶片和第二器件晶片任一个的互连电介质材料。可通过化学气相沉积或原子层沉积在Cu/电介质图案的未处理或改性的表面上实现选择性沉积。典型的例子是通过化学气相沉积处理的Mn或Co的选择性沉积。
现在参照图17，其中示出除了在形成金属粘附层时使用选择性沉积处理以外可通过使用图12～15所示的基本处理步骤处理的3D集成电路。因而，没有金属粘附层接触第一器件晶片和第二器件晶片任一个的互连电介质材料。可通过化学气相沉积或原子层沉积在Cu/电介质图案的未处理或改性的表面上实现选择性沉积。典型的例子是通过化学气相沉积处理的Mn或Co的选择性沉积。
在本公开的一些实施例中，以上的处理步骤可被用于接合来自一个器件晶片的未经构图的Cu接合焊盘与来自另一器件晶片的至少一个经构图的Cu接合焊盘。
虽然关于本公开的优选实施例特别表示和描述了本公开，但是本领域技术人员可以理解，在不背离本公开的精神和范围的情况下，可提出形式和细节的以上和其它的变化。因此，本公开不应限于描述和示出的确切的形式和细节，而落入所附的权利要求的范围内。

Claims (25)

1.一种形成三维(3D)集成电路的方法，所述方法包括：
提供包括Cu表面的第一器件晶片；
至少在第一器件晶片的Cu表面上形成金属粘附层；
在金属粘附层上且在第一器件晶片的Cu表面顶上放置包括另一Cu表面的第二器件晶片；和
在低于400℃的温度下将第一器件晶片和第二器件晶片接合在一起，其中，所述金属粘附层从两个Cu表面得到氧原子，并且在第一器件晶片的Cu表面与第二器件晶片的另一Cu表面之间形成金属氧化物接合层。
2.如权利要求1所述的方法，其中，第一器件晶片的所述Cu表面和第二器件晶片的所述另一Cu表面是Cu接合焊盘，并且每一Cu接合焊盘都被构图。
3.如权利要求1所述的方法，其中，第一器件晶片的所述Cu表面和第二器件晶片的所述另一Cu表面是Cu接合焊盘，并且每一Cu接合焊盘都未被构图。
4.如权利要求1所述的方法，其中，所述形成金属粘附层包含非选择性的沉积处理。
5.如权利要求1所述的方法，其中，所述形成金属粘附层包含选择性的沉积处理。
6.根据权利求1的方法，其中，所述形成金属粘附层包含：
选择Mn、Ta、Ti、Co、W、Ru、Ni或包含选自Mn、Ta、Ti、Co、w、Ru和Ni中的两种或更多种金属的组合的合金中的至少一种。
7.如权利要求2所述的方法，其中，所述金属氧化物接合层与所述Cu接合焊盘的侧壁垂直对准。
8.如权利要求1所述的方法，其中，所述第一器件晶片包含场效应晶体管，并且所述第二器件晶片包含另一场效应晶体管。
9.如权利要求1所述的方法，其中，所述Cu表面位于互连级的最高表面顶上，所述互连级包含至少一个互连电介质材料，所述至少一个互连电介质材料具有位于其中的多个导电特征件，其中，导电特征件中的至少一个与第一器件晶片的所述Cu表面的最底部分接触。
10.如权利要求1所述的方法，还包括：
在接合之前翻转器件晶片中的至少一个。
11.如权利要求1所述的方法，其中，金属粘附层的一部分保持在器件晶片中的至少一个顶上。
12.如权利要求1所述的方法，其中，所述金属粘附层包含多层结构，并且所述金属氧化物接合层包含多层结构。
13.一种三维(3D)集成电路，包括：
包含Cu表面的第一器件晶片和包含另一Cu表面的第二器件晶片的垂直叠层，其中，金属氧化物接合层位于第一器件晶片的第一Cu表面与第二器件晶片的另一Cu表面之间。
14.如权利要求13所述的3D集成电路，其中，第一器件晶片的所述Cu表面与第二器件晶片的所述另一Cu表面是Cu接合焊盘，并且每一Cu接合焊盘都被构图。
15.如权利要求13所述的3D集成电路，其中，第一器件晶片的所述Cu表面与第二器件晶片的所述另一Cu表面是Cu接合焊盘，并且每一Cu接合焊盘都未被构图。
16.如权利要求13所述的3D集成电路，其中，所述金属氧化物接合层与所述Cu接合焊盘中的每一个的侧壁垂直对准。
17.如权利要求13所述的3D集成电路，其中，所述金属氧化物接合层由金属粘附层通过从两个Cu表面得到氧原子而形成，金属粘附层的一部分保持在器件晶片中的至少一个顶上。
18.如权利要求17所述的3D集成电路，其中，所述金属粘附层包含Mn、Ti、Ta、Co、w、Ru和Ni中的一种或包含选自Mn、Ta、Ti、Co、w、Ru和Ni中的两种或更多种金属的组合的合金。
19.如权利要求13所述的3D集成电路，其中，所述金属氧化物接合层包含Mn、Ti、Ta、Co、W、Ru和Ni中的至少一种或包含选自Mn、Ta、Ti、Co、w、Ru和Ni中的两种或更多种金属的组合的合金的氧化物。
20.如权利要求13所述的3D集成电路，其中，所述第一器件晶片包含场效应晶体管，并且所述第二器件晶片包含另一场效应晶体管。
21.如权利要求13所述的3D集成电路，其中，所述cu表面位于互连级的最高表面顶上，所述互连级包含至少一个互连电介质材料，所述至少一个互连电介质材料具有位于其中的多个导电特征件，其中，导电特征件中的至少一个与第一器件晶片的cu表面的最底部分接触。
22.如权利要求13所述的3D集成电路，其中，所述第一器件晶片包含半导体基板和互连级，所述半导体基板具有至少部分位于其上的至少一个器件，所述互连级位于半导体基板顶上，并且所述互连级包含嵌入至少一个互连电介质材料内的多个导电特征件，其中导电区域连接所述多个导电特征件中的一个与所述cu表面。
23.如权利要求22所述的3D集成电路，其中，所述第二器件晶片从下到上包含绝缘体层、半导体器件层、至少部分位于所述半导体器件层上的至少一个其它器件和另一互连级，所述另一互连级包含嵌入至少一个其它互连电介质材料内的多个其它导电特征件，其中通路连接其它导电特征件中的至少一个与另一cu表面的最底部分，并且其中，所述第一器件晶片的所述cu表面和所述第二器件晶片的所述另一cu表面是经构图的cu接合焊盘。
24.如权利要求22所述的3D集成电路，其中，所述第二器件晶片包含另一半导体基板和另一互连级，所述另一半导体基板具有至少部分位于其上的至少一个其它器件，所述另一互连级位于另一半导体基板顶上，并且所述另一互连级包含嵌入至少一个其它互连电介质材料内的多个其它导电特征件，其中所述第一器件晶片和所述第二器件晶片中的至少一个被翻转，并且其中，第一器件晶片的所述cu表面和第二器件晶片的所述另一cu表面是经构图的cu接合焊盘。
25.如权利要求17所述的3D集成电路，其中，所述金属氧化物接合层是多层结构。
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