CN101261978A - 半导体元件安装用基板及其制造方法 - Google Patents

半导体元件安装用基板及其制造方法 Download PDF

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Publication number
CN101261978A
CN101261978A CNA2008100817394A CN200810081739A CN101261978A CN 101261978 A CN101261978 A CN 101261978A CN A2008100817394 A CNA2008100817394 A CN A2008100817394A CN 200810081739 A CN200810081739 A CN 200810081739A CN 101261978 A CN101261978 A CN 101261978A
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China
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semiconductor element
pattern
element mounting
mounting substrate
pseudo
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CNA2008100817394A
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野野山茂
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Publication of CN101261978A publication Critical patent/CN101261978A/zh
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Abstract

本发明提供一种半导体元件安装用基板(101)，该半导体元件安装用基板(101)具有：将安装半导体元件(11)的区域(2)设定于一个主面的基板(1)；形成在上述基板(1)上的、用于与半导体元件(11)连接的多个布线图案(3)；以及在安装上述半导体元件(11)的区域(2)内形成为框状的、且不与上述布线图案(3)连接的伪图案(8)。

Description

半导体元件安装用基板及其制造方法
技术领域
本发明涉及一种树脂密封型半导体器件等中所采用的半导体元件安装用基板及其制造方法。
背景技术
在以往的半导体元件安装用基板上，往往在基板的一个主面(下面，称为正面)上设定半导体元件安装区域，并在正反面上形成多个布线图案。
半导体元件安装用基板一般随着半导体器件薄型化要求迫切而变得越来越薄。因此，基板正反面的布线密度差的影响变得明显，弯曲增加，而且难以稳定地在半导体元件安装区域上涂覆粘接剂。而且，粘接剂的涂覆变得不均匀，成为导致半导体元件的粘接强度恶化、并且导致半导体器件的可靠性下降的原因。
为了确保粘接剂均匀地涂覆，提出通过从半导体元件安装部分的中间向着基板外周呈放射状地形成布线图案，以抑制弯曲。对于半导体元件安装部分，通过限制正面的布线图案的形成，使正反面的布线密度均匀，从而抑制弯曲(特开平8-153823号公报)。
近些年，随着对半导体器件的薄型化的要求越来越迫切，半导体元件以及半导体元件安装用基板的薄型化、用于提高组装稳定性的粘接剂的低粘度化等也进一步地发展。另外，伴随着半导体器件的多引脚化、小型化的要求，在半导体元件安装用基板上，即使在半导体元件正下方的位置上也必须形成布线。
如果半导体元件安装用基板向薄型化发展，则弯曲等的变形量将增加。利用放射状地形成布线的上述方法，当在涂覆了粘接剂的上面按压半导体元件时，粘接剂容易通过半导体元件与布线之间的间隙、以及布线彼此之间的间隙向半导体元件外部流出。另外，容易通过这些间隙从周边部分向半导体元件正下方卷入空气。
如果粘接剂向半导体元件外部流出，则半导体元件正下方的粘接剂变薄而变得不均匀，成为导致粘接强度不足的原因。如果向半导体元件的正下方卷入空气，则由于安装基板上安装半导体器件时的热压等将使空气膨胀，成为导致半导体器件的损坏或者可靠性下降的主要原因。
发明内容
本发明鉴于上述问题，目的在于提供一种半导体元件安装用基板，该半导体元件安装用基板在用糊剂状的粘接剂固定半导体元件时，能够抑制半导体元件正下方的粘接剂流出、以及向半导体元件正下方卷入空气的情况。
为了达到上述目的，本发明的半导体元件安装用基板具有：将安装半导体元件的区域设定于一个主面的基板；形成在上述基板上的、与半导体元件连接用的多个布线图案；以及在安装上述半导体元件的区域内形成为框状的、不与上述布线图案连接的伪图案。
如果采用这样的结构，则当用糊剂状粘接剂将半导体元件固定在半导体元件安装区域上时，利用框状的伪图案能够抑制半导体元件正下方的粘接剂流出，并且能够确保粘接剂的用量，同时还能够防止向半导体元件正下方卷入空气。
伪图案可以利用与布线图案该导体材料、与上述布线图案绝缘来形成。伪图案也可以用绝缘材料来形成。
伪图案最好比布线图案要厚。多个伪图案最好互相位于内外的位置来形成。内侧的伪图案最好比较厚。
本发明的半导体元件安装用基板的制造方法，具有：将安装半导体元件的区域设定于一个主面的基板上、使与半导体元件连接用的多个布线图案在需要部位相互连接而形成的工序；形成覆盖上述布线图案的绝缘树脂膜的工序；以及在安装上述半导体元件的区域内、形成不与上述布线图案连接的框状的伪图案的工序。
形成伪图案的工序，能够在形成布线图案的工序内，采用该导体材料来进行。形成伪图案的工序，能够在形成覆盖布线图案的绝缘树脂膜的工序内，采用该树脂材料来进行。
形成布线图案的工序，还可以包括：在基板的一个主面以及另一个面上形成布线图案、以使得在规定位置上具有与半导体元件连接的多个电极端子以及外部连接用电极端子的第1工序；以及在电连接上述多个电极端子和对应的外部连接用电极端子的规定位置上、形成通孔的第2工序。
附图说明
图1是表示本发明的实施形态1中的半导体元件安装用基板以及采用该基板的半导体器件的结构图。
图2是表示制造图1的半导体元件安装用基板、一直到安装半导体元件为止的工序的剖面图。
图3是表示本发明的实施形态2中的半导体元件安装用基板以及采用该基板的半导体器件的结构图。
图4是表示本发明的实施形态3中的半导体元件安装用基板以及采用该基板的半导体器件的结构图。
图5是表示本发明的实施形态4中的半导体元件安装用基板以及采用该基板的半导体器件的结构图。
具体实施方式
下面，参照附图来说明本发明的实施形态。
图1(a)是本发明的实施形态1的半导体元件安装用基板的俯视图，图1(b)(c)分别是放大该半导体元件安装用基板的一部分所表示的俯视图和剖面图，图1(d)是采用该半导体元件安装用基板的半导体器件的剖面图。
在图1(a)中，半导体元件安装用基板101是为了成批制造多个半导体器件而采用的基板，该半导体元件安装用基板101是将玻璃环氧树脂等作为基材(基板)而形成的，纵向横向地配置多个器件区域102，同时夹着狭缝103来配置多组这样的多个器件区域102的排列。
在各器件区域102上，如图1(b)(c)所示，在基板1的一个主面(下面，称为正面)上，设定安装半导体元件的四边形的半导体元件安装区域2(与半导体元件具有相同形状以及尺寸)，在正反面形成多个布线图案3，并且在规定位置形成连接正反面的布线图案3的通孔5。
正面的多个布线图案3这样排列，以使得包围半导体元件安装区域2，分别从划定半导体元件安装区域2的边界线的内侧沿着与该边界线垂直的方向向外侧方向延伸。在各布线图案3的外端部上，形成用于和半导体元件取得电连接的电极部4。形成在反面的多个布线图案3上的外部连接端子6并排呈格子状。在电极部4以外的基板正面形成绝缘树脂膜7。对布线图案3、电极部4、通孔5、外部连接端子6采用铜(Cu)等的金属。对绝缘树脂膜7采用阻焊剂等。
在半导体元件安装区域2内，形成不与布线图案3电连接的框状的伪图案8，以使其与半导体元件的下面对向。总之，形成伪图案8，以使其处于划定半导体元件安装区域2的边界线(即安装的半导体元件的外端边缘)的内侧，并且与上述边界线平行。关于伪图案8在后面还要进行说明。
在图1(d)所示的半导体器件中，在半导体元件安装用基板101A(上述的半导体元件安装用基板101的器件区域102相应的部分)的半导体元件安装区域2上，用由环氧树脂等构成的粘接剂12来固定半导体元件11。利用金(Au)等的接合线13来电连接半导体元件11的多个电极和对应的电极部4。为了在外部环境中保护半导体元件11以及接合线13，用由环氧树脂等构成的密封树脂14覆盖基板正面一侧。在基板反面的外部连接端子6上，形成用于与外部的安装基板等进行连接的由焊锡等构成的球电极15。这样的半导体器件被称为BGA(球栅阵列)封装。
在制造该半导体器件时，在图1(a)所示的半导体元件安装用基板101的各器件区域102上固定半导体元件11，并对其进行电连接，对于多个(在图中为4个)器件区域102的每一个排列，用密封树脂14一下子密封比该排列要大一圈的区域，然后利用切割对每个器件区域102进行分割。在切割之前或者之后安装球电极15。
参照图2，说明半导体元件安装用基板101的制造方法。为了简单起见，只图示一个器件区域102。
首先，如图2(a)所示，在基板1的正反面形成多个布线图案3，同时在半导体元件安装区域2上形成框状的伪图案8。为此，在正面形成铜等的金属箔后所得到的基板1上，将由光致抗蚀剂等构成的树脂薄膜(未图示)形成为所希望的形状，将其作为掩膜来对金属箔进行刻蚀(干法或者湿法)。
接着，如图2(b)所示，对布线图案3以及伪图案8进行刻蚀，直到形成所希望的厚度为止。这里虽然将布线图案3与伪图案8设定为该厚度，但是在使厚度不同的情况下，在形成掩膜(未图示)之后再进行刻蚀。
如图2(c)(d)所示，利用钻头或激光加工等在所规定的位置上形成穿通孔5′，并通过实施铜(Cu)等的金属电镀，从而形成连接正反面的布线图案3的通孔5，同时对布线图案3进行电镀。
如图2(e)所示，为了在外部环境中保护布线图案3，用绝缘树脂膜7来覆盖电极部4以外的部分。也用绝缘树脂膜7来覆盖伪图案8。
假定线表示：当制造图1(d)的半导体器件时，在半导体元件安装区域2上涂覆糊剂状的粘接剂8，并在其上安装了半导体元件11的状态。框状的伪图案10位于半导体元件11的外周端的内侧正下方、与半导体元件11的四边平行的位置上。
由于存在该伪图案10，故通过包围半导体元件11的正下方的粘接剂8来抑制流出，并且能够确保均匀的规定厚度的粘接剂8的量，达到半导体元件11的正下方至少伪图案10的厚度。还能够防止空气卷入半导体元件11的正下方。还起到对实现薄型化且增加布线密度后的半导体元件安装用基板101抑制弯曲的效果。
如上所述，半导体元件安装用基板101，在成为半导体元件11的正下方的位置上也具有布线图案3，由于近些年采用低粘度的粘接剂8，所以存在着粘接剂8容易排出的情况。另外，由于近些年半导体元件安装用基板101的薄型化，所以存在着整体容易弯曲、且向半导体元件11正下方容易卷入空气的状况。总之，虽然半导体元件安装用基板101是放置在扁平的平板上来安装半导体元件11的基板，但是由于安装时的按压而暂时变得扁平，在这样的状态下与半导体元件11之间形成一定的粘接剂层8，在放开按压时就返回原本的弯曲状态。在返回弯曲状态时，通过布线图案3之间的间隙，向半导体元件11正下方进入空气，容易形成卷入气孔。利用伪图案10的存在，能够抑制这些情况。
因此，在半导体器件的组装中，提高半导体元件11的粘接强度，并且能够确保稳定的生产。另外，能够防止由于半导体器件安装时的热压等而引起的损坏，能够提高可靠性。
在半导体器件的薄型化、多引脚化、小型化发展的近些年来，在要求半导体元件以及半导体元件安装用基板的更加薄型化、以及半导体元件安装用基板的布线密度的增加的现状下，这是非常有效的。换而言之，本发明的半导体元件安装用基板对于薄型、多引脚、小型的半导体器件的制造特别有用。
图3(a)是本发明的实施形态2的半导体元件安装用基板的俯视图，图3(b)(c)是分别放大该半导体元件安装用基板的一部分所表示的俯视图以及剖面图，图3(d)是采用该半导体元件安装用基板的半导体器件的剖面图。
在该实施形态2的半导体元件安装用基板101上，以与实施形态1的伪图案8相同形状和厚度来形成框状的伪图案8a。另外，在其内侧以同心形状且相同厚度来形成伪图案8b。通过这样，半导体元件11正下方的粘接剂12更难被排出到半导体元件11之外。
图4(a)是本发明的实施形态3的半导体元件安装用基板的俯视图，图4(b)(c)是分别放大该半导体元件安装用基板的一部分所表示的俯视图以及剖面图，图4(d)是采用该半导体元件安装用基板的半导体器件的剖面图。
在该实施形态3的半导体元件安装用基板101上，以与实施形态1的伪图案8相同的形状、但更厚的厚度来形成框状的伪图案8c。通过这样，半导体元件11正下方的粘接剂12更难被排出到半导体元件11之外，而且能够更有效地防止向半导体元件11的正下方卷入空气。
图5(a)是本发明的实施形态4的半导体元件安装用基板的俯视图，图5(b)(c)是分别放大该半导体元件安装用基板的一部分所表示的俯视图以及剖面图，图5(d)是采用该半导体元件安装用基板的半导体器件的剖面图。
在该实施形态4的半导体元件安装用基板101上，以与实施形态1的伪图案8相同的形状、但更厚的厚度来形成框状的伪图案8d。另外，在其内侧以同心形状且更厚的厚度来形成伪图案8e。通过这样，半导体元件11正下方的粘接剂12更难被排出到半导体元件11之外，而且能够更有效地防止向半导体元件正下方卷入空气。
上面，虽然是作为在形成布线图案3的工序内、采用该材料形成伪图案8、8a～8e来进行说明的，但是也可以在形成绝缘树脂膜7的工序内采用该树脂材料来形成伪图案8、8a～8e。
另外，虽然是作为利用接合线13连接半导体元件11与布线图案3来进行说明的，但是也可以形成使半导体元件11能够进行倒装芯片安装的布线图案3以及电极部4。
另外，本发明所述的半导体元件安装用基板是指：上述的、为了成批制造多个半导体器件而采用的半导体元件安装用基板101、与1个半导体器件对应的半导体元件安装用基板101A这两者。

Claims (9)

1.一种半导体元件安装用基板，其特征在于，
具有：
将安装半导体元件的区域设定于一个主面的基板；
形成在所述基板上的、且用于与半导体元件连接的多个布线图案；以及
在安装所述半导体元件的区域内形成为框状的、不与所述布线图案连接的伪图案。
2.如权利要求1中所述的半导体元件安装用基板，其特征在于，
伪图案是利用与布线图案相同的导体材料、与所述布线图案绝缘而形成的。
3.如权利要求1中所述的半导体元件安装用基板，其特征在于，
伪图案利用绝缘材料来形成。
4.如权利要求1中所述的半导体元件安装用基板，其特征在于，
伪图案比布线图案要厚。
5.如权利要求1中所述的半导体元件安装用基板，其特征在于，
多个伪图案互相位于内外的位置而形成。
6.如权利要求5中所述的半导体元件安装用基板，其特征在于，
内侧的伪图案比较厚。
7.一种半导体元件安装用基板的制造方法，其特征在于，
具有：
在将安装半导体元件的区域设定于一个主面的基板上，使与半导体元件连接用的多个布线图案在需要部位互相连接而形成的工序；
形成覆盖所述布线图案的绝缘树脂膜的工序；以及
在安装所述半导体元件的区域内、形成不与所述布线图案连接的框状的伪图案的工序。
8.如权利要求7中所述的半导体元件安装用基板的制造方法，其特征在于，
在形成布线图案的工序内，采用该导体材料来进行形成伪图案的工序。
9.如权利要求7中所述的半导体元件安装用基板的制造方法，其特征在于，
在形成覆盖布线图案的绝缘树脂膜的工序内，采用该树脂材料来进行形成伪图案的工序。
CNA2008100817394A 2007-03-08 2008-03-06 半导体元件安装用基板及其制造方法 Pending CN101261978A (zh)

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