CN101233612B - 金属-陶瓷复合基板及其制造方法 - Google Patents

金属-陶瓷复合基板及其制造方法 Download PDF

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CN101233612B
CN101233612B CN2006800278824A CN200680027882A CN101233612B CN 101233612 B CN101233612 B CN 101233612B CN 2006800278824 A CN2006800278824 A CN 2006800278824A CN 200680027882 A CN200680027882 A CN 200680027882A CN 101233612 B CN101233612 B CN 101233612B
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metal
layer
ceramic
substrate
composite substrate
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CN101233612A (zh
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大鹿嘉和
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Dowa Electronics Materials Co Ltd
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Dowa Electronics Materials Co Ltd
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Abstract

提供一种具备良好的散热性的金属-陶瓷复合基板、和以低成本制造该复合基板的方法。是由金属基板(11)、形成在金属基板(11)上的陶瓷层(12)、形成在陶瓷层(12)上的电极层(13)、和形成在电极层(13)上的钎焊层(14)构成的金属-陶瓷复合基板(10)，陶瓷层(12)由陶瓷薄膜构成。如果将陶瓷层(12)用氮化铝薄膜形成，则能够得到散热特性良好的电子电路用金属-陶瓷复合基板(10)。

Description

金属-陶瓷复合基板及其制造方法
技术领域
本发明涉及在电子电路用基板中使用的金属-陶瓷复合基板及其制造方法。
背景技术
通常，各种电子部件被搭载、焊接在形成于印刷基板上的铜配线图案上的规定部位上，进行电子电路的连线。但是，作为印刷基板的材料，由于使用纸酚醛树脂、环氧树脂、玻璃环氧树脂等各种树脂，所以虽然是低成本，但散热性不好。
在特许文献1中，公开了为了实现半导体搭载用电路基板的高密度安装化而在Al、Cu等的布图的金属基础基板上流入绝缘填料而形成电路的半导体搭载用电路基板。在该文献中，作为绝缘填料使用厚度为100μm的含硅环氧树脂，在该树脂的上表面上作为配线层而形成有由铝及铜构成的箔。
在特许文献2中，公开了在由AlN构成的陶瓷基板上通过粘贴等设置Cu等导电层、通过布图该导电层而形成电路的能够在IC封装等中使用的金属薄膜层叠陶瓷基板。
然而，在上述特许文献1的半导体搭载用电路基板中，由于使用金属基础基板，所以与印刷基板相比散热性变好，但由于配线层形成在0.1mm的较厚的含硅环氧树脂上，所以有散热性变得较低的问题。此外，虽然比印刷基板昂贵，但能够以较低的成本制造。
在特许文献2的陶瓷基板中，在使用AlN之类的热传导率较高的陶瓷基板的情况下，散热性比印刷基板及特许文献1的金属基础基板好。但是，有需要陶瓷基板自身的烧结工序等、工序较复杂、并且成品率较差、比印刷基板及特许文献1的金属基础基板成本高的问题。
此外，如果电路构造微细化，则终归与以Cu、Al为基板的金属基板相比，热传导率较小的陶瓷基板的每单位体积的热阻较大。因而，在搭载半导体元件那样的微小电路、例如热沉(submount)上，热沉整体的AlN基板的热阻为90％以上，散热性变差，在散热性方面并不能说是适合的。
相对于此，在作为电子设备的半导体元件搭载用电路基板中，虽然有低成本的要求，但使散热性为最优先。因此，希望有热阻更小的基板。
特许文献1：日本特许第3156798号
特许文献2：日本特许第2762007号
发明内容
本发明的一个目的是提供一种具备良好的散热性的金属-陶瓷复合基板。
本发明的另一目的是提供一种能够以低成本制造上述金属-陶瓷复合基板的方法。
为了达到上述一个目的，本发明是由金属基板、形成在金属基板上的陶瓷层、形成在陶瓷层上的电极层、和形成在电极层上的钎焊层构成的金属-陶瓷复合基板，其特征在于，陶瓷层由陶瓷薄膜构成。
在上述结构中，优选的是，还在陶瓷层上直接形成有与上述铅焊层不同的钎焊层。进而，也可以在陶瓷层与电极层之间插入有陶瓷层保护膜。
优选的是，金属基板由铜或铝构成。陶瓷层优选地由氮化物类陶瓷构成。该氮化物类陶瓷优选为氮化铝。
根据本发明，通过作为金属基板而优选地使用铜、铝等金属，并且在该金属基板的表面上形成陶瓷薄膜、优选地形成氮化物类陶瓷、特别是由氮化铝构成的较薄的陶瓷层，陶瓷薄膜自身的热阻变小，能够降低金属基板的表面的热阻。因而，降低了金属基板表面的热阻，金属-陶瓷复合基板的散热性提高。这样，由于增大了热传导率较大的金属基板的体积，并且能够形成电路，所以能够提供热阻比陶瓷基板小的金属-陶瓷复合基板。
为了达到上述另一个目的，本发明是由金属基板、形成在金属基板上的陶瓷层、形成在陶瓷层上的电极层、和形成在电极层上的钎焊层构成的金属-陶瓷复合基板的制造方法，其特征在于，包括：在金属基板的表面上形成陶瓷薄膜作为陶瓷层的工序；在陶瓷层上形成规定的图案的电极层的工序。
在本发明的制造方法中，也可以包括还在陶瓷层上直接形成其它钎焊层的工序。此外，也可以包括在陶瓷层的形成后再形成陶瓷层保护膜的工序。陶瓷层优选地由氮化物类陶瓷构成，特别优选为氮化铝。
根据本发明的方法，通过使用金属作为基板并且在该金属基板的表面上形成陶瓷薄膜，能够增大热传导率较大的金属基板的体积并且能够形成电路，所以能够制造热阻比陶瓷基板小的金属-陶瓷复合基板。进而，金属基板能够与金属基础基板的情况大致同样地以低成本制造，并且作为陶瓷层的陶瓷薄膜能够通过例如PVD法等形成，所以陶瓷薄膜不需要烧结工序等复杂的工序，整体上能够以较低的成本制造。
根据本发明的金属-陶瓷复合基板，例如在搭载半导体装置时，来自半导体装置的热经过热阻较低的陶瓷薄膜后再通过金属基板被散热，散热性提高，所以能够得到热阻较小的金属-陶瓷复合基板。因而，使用本发明的金属-陶瓷复合基板的半导体装置的温度上升变小，能够提高半导体装置的性能及寿命。
此外，根据本发明的方法，由于使用金属基板及在该金属基板的表面上使用陶瓷薄膜，所以整体上能够低成本地制造。
附图说明
图1是示意地表示本发明的金属-陶瓷复合基板的构造的剖视图。
图2是示意地表示本发明的金属-陶瓷复合基板的构造的剖视图。
图3是示意地表示在本发明的金属-陶瓷复合基板上搭载有半导体装置的构造的剖视图。
图4是示意地表示本发明的金属-陶瓷复合基板的变形例的构造的剖视图。
图5是示意地表示本发明的金属-陶瓷复合基板的变形例的构造的剖视图。
图6是示意地表示本发明的金属-陶瓷复合基板的另一变形例的构造的剖视图。
图7是示意地表示本发明的金属-陶瓷复合基板的另一变形例的构造的剖视图。
图8是示意地表示比较例1的构成的剖视图。
图9是示意地表示比较例2的构成的剖视图。
符号说明
10、10A、20、20A、30、30A：金属-陶瓷复合基板
11、61：金属基板
12：陶瓷层(陶瓷薄膜)
13、52、63：电极层
14、53、64：钎焊层
15：半导体装置
15A：上部电极
15B：下部电极
16：Au线
22：钎焊层(形成在陶瓷层上的钎焊层)
24：陶瓷层保护膜
具体实施方式
以下，通过附图更详细地说明本发明的实施方式。在各图中，在相同或对应的部件中使用相同的符号。
图1及图2是示意地表示本发明的金属-陶瓷复合基板的构造的剖视图。在图1中，金属-陶瓷复合基板10由金属基板11、形成为使其在该金属基板11的单面覆盖该金属基板11的整体的陶瓷层12、和形成在陶瓷层12的表面上以使其覆盖该陶瓷层12的一部分或整面的电极层13、和形成在该电极层13表面的规定部位13A上的钎焊层14构成。
这里，作为电极层13的规定部位13A，在发光二极管等的情况下也可以是整面。也可以存在没有形成钎焊层的电极层13B。在该电极层13B上也可以形成图案，并且，也可以在电极层13B的一部分上连接金属线，形成电路。
也可以在金属基板11的背面侧也设置电极层13及钎焊层14。也可以在金属基板11的背面侧与电极层13及钎焊层14之间插入陶瓷层12。在图2所示的金属-陶瓷复合基板10A的情况下，表示了在金属基板11的背面侧依次层叠陶瓷层12、电极层13和钎焊层14的例子。
作为上述金属基板11，可以使用由铜、铝等的金属构成的金属基础基板。这样的金属基础基板优选地具有例如200W/mK以上的热传导率。
作为上述陶瓷层12，可以使用与金属基板11密接性良好的陶瓷薄膜，优选地使用热阻较小的氮化铝(AlN)等的氮化物类陶瓷薄膜。
作为电极层13，优选为金属，特别是可以使用金(Au)、白金(Pt)、银(Ag)、铜(Cu)、铁(Fe)、铝(Al)、钛(Ti)、钨(W)的任一种。也可以是包含这些金属的任一种的合金。
关于钎焊层14，优选为不使用铅(Pb)的、即无铅钎焊。进而，优选地使用含有银、金、铜、锌(Zn)、镍(Ni)、铟(In)、镓(Ga)、铋(Bi)、铝、锡(Sn)中的两种以上的元素的钎焊。
此外，在上述金属基板11与陶瓷层12之间和/或上述电极层13与钎焊层14之间也可以为了提高成膜时的密接性而配置密接层。作为密接层，可以优选地使用钛。
接着，说明本发明的金属-陶瓷复合基板的半导体装置的安装例。
图3是示意地表示在本发明的金属-陶瓷复合基板上搭载有半导体装置的构造的剖视图。如图3所示，在本发明的金属-陶瓷复合基板10中，半导体装置15的下部电极15A可以通过钎焊层14向金属-陶瓷复合基板10进行钎焊接合。此外，在使用由Au-Sn合金构成的钎焊层14的情况下，半导体装置15能够无焊剂地进行钎焊接合。
另一方面，如图所示，在与右侧的电极层13A绝缘、并且没有形成钎焊层的左侧的电极层13B上，可以通过Au线16等引线接合并连接半导体装置15的上部电极15B。
这里，所谓的半导体装置15，有激光二极管或发光二极管之类的发光元件、二极管、在高频放大及交换中使用的晶体管或晶闸管之类的主动元件、集成电路等。在图2中，作为搭载的电子部件而表示了半导体装置15，但也可以是包括受动元件及各种主动元件的电子电路。
接着，对搭载有半导体装置的金属-陶瓷复合基板10的热阻进行说明。金属基板11的背面侧被搭载在封装或散热体上，在金属-陶瓷复合基板10是能够搭载半导体装置15的程度的面积时，金属-陶瓷复合基板10的热阻RT可以通过下述(1)式计算。
[式1]
R T = 1 A ( t M k M + t C k C + t E k E + t S k S ) + t D Ak D + 1 4 π k h - - - ( 1 )
这里，第1项是金属-陶瓷复合基板10的热阻成分。tM、tC、tE、tS及kM、kC、kE、kS分别是金属基板11、陶瓷层12、电极层13A、钎焊层14的厚度及热传导率，A是半导体装置15的面积。第2项是半导体装置15的热阻成分，接合深度是tD，热传导率是kD。第3项是热传导率为kh的封装及散热体的热阻成分。
金属基板11的厚度如果考虑到其处理的容易程度，则为100m～1mm左右，在陶瓷层12、电极层13A、以及钎焊层14的任一个中，它们的厚度都大致为10μm左右以下。因而，上述(1)式近似于下述(2)式。
[式2]
R T = 1 A ( t M k M ) + t D Ak D + 1 4 π k h - - - ( 2 )
例如，金属基板11由铜(kM＝300W/mK)构成，使其厚度tM为500μm。陶瓷层12由氮化铝(kC＝200W/mK)构成，使其厚度tC为10μm。电极层13A由Au(kE＝315W/mK)构成，使其厚度tE为0.1μm。并且，钎焊层14由Au-Sn(kS＝50W/mK)构成，使其厚度tS为5μm。
在此情况下，在由上述(1)式的第1项表示的金属-陶瓷复合基板10中，如果使金属基板11的热阻为1，则陶瓷层12、电极层13A、钎焊层14的热阻分别为0.03、0.0002、0.06左右。在它们的各层中，按照钎焊层14、陶瓷层12、电极层13A的顺序热阻较大。即使这样，可知它们的各层的热阻的合计也为金属基板11的热阻的约1/15，本发明的金属-陶瓷复合基板10的热阻可以用上述(2)近似。
接着，对金属-陶瓷复合基板10A的热阻进行说明。在此情况下，在金属基板11的背面上也与其表面侧同样地设有陶瓷层12、电极层13A、钎焊层14，使金属基板11的背面侧的各层的材质和厚度与表面侧的值相同。金属-陶瓷复合基板10A的热阻RT′可以通过在上述(1)式中再加上设于金属基板11的背面侧的陶瓷层12、电极层13A、钎焊层14的热阻成分的下述(3)式计算。
[式3]
R T ′ = 1 A ( t M k M + 2 t C k C + 2 t E k E + 2 t S k S ) + t D Ak D + 1 4 π k h - - - ( 3 )
热阻RT′与在金属-陶瓷复合基板10中说明的同样，与金属基板11的热阻相比，设在金属基板11的两面侧的陶瓷层12、电极层13A、钎焊层14的热阻成分足够小。因而，在金属基板11的表面及背面上设有陶瓷层12、电极层13A、钎焊层14的金属-陶瓷复合基板10A的热阻RT′也可以用上述(2)式近似。
由此，根据本发明的金属-陶瓷复合基板10及10A，如果使作为绝缘物的陶瓷层12的厚度比金属基板11足够薄，则热阻由最厚的金属基板11决定。因而，本发明的金属-陶瓷复合基板10的热阻成为与金属基板11大致相同的值。
对本发明的金属-陶瓷复合基板的变形例进行说明。
图4及图5是示意地表示本发明的金属-陶瓷复合基板的变形例的构造的剖视图。图4所示的金属-陶瓷复合基板20与图1所示的金属-陶瓷复合基板10不同的是：在陶瓷层12上直接与上述钎焊层14不同地形成有钎焊层22。该钎焊层22也可以与电极层13连接而构成电路。也可以作为用来搭载其它电子电路部件的配线图案。钎焊层22可以在设于电极层13上的钎焊层14的形成时同时形成。
在金属基板11的背面侧也可以设置电极层13及钎焊层14。在金属基板11的背面侧与电极层13及钎焊层14之间也可以插入陶瓷层12。在图5所示的金属-陶瓷复合基板20A的情况下，表示了在金属基板11的背面侧依次层叠有陶瓷层12、电极层13和钎焊层14的例子。
说明本发明的金属-陶瓷复合基板的另一变形例30。
图6及图7是示意地表示本发明的金属-陶瓷复合基板的另一变形例的构造的剖视图。图6所示的金属-陶瓷复合基板30与图1所示的金属-陶瓷复合基板10不同的是：在陶瓷层12与电极层13之间插入了陶瓷层保护膜24。
陶瓷层保护膜24是在制造本发明的金属-陶瓷复合基板30时，最先覆盖在陶瓷层12的整面上的层，是为了在形成电极层13及钎焊层14的图案时的工序中通过蚀刻使陶瓷层12被蚀刻、或者其表面粗糙度变大而设置的。该陶瓷层保护膜24可以在形成钎焊层14后、通过将不需要的区域除去，进行与形成在金属-陶瓷复合基板30上的电极层13的绝缘分离。
这里，陶瓷层保护膜24优选为与陶瓷层12的密接性良好、与电极层14不同的金属，可以使用钛、白金、镍、钨、钼(Mo)、银、铜、铁、铝、金的任一种。也可以含有两种以上的这些金属。例如，可以在陶瓷层12上层叠形成钛。
也可以在金属基板11的背面侧设置电极层13及钎焊层14。也可以在金属基板11的背面侧与电极层13及钎焊层14之间插入陶瓷层12。在图7所示的金属-陶瓷复合基板30A的情况下，表示了在金属基板11的背面上依次层叠了陶瓷层12、电极层13和钎焊层14的例子。
在本发明的金属-陶瓷复合基板10、20、30中，上述陶瓷层12也可以形成在金属基板11的表面整体上。根据需要，也可以仅形成在金属基板11的表面的规定部分上。在此情况下，在陶瓷层12的沉积之前，在通过光刻法实施布图后沉积陶瓷层12，然后，利用对布图中使用的抗蚀剂膜进行蚀刻的所谓提离(lift off)法，能够仅在规定的区域形成陶瓷层12。也可以在将规定部分开口的金属掩模载置于金属基板11上的状态下沉积陶瓷层12。在此情况下，仅在金属掩模的开口部形成陶瓷层12。
如本发明的金属-陶瓷复合基板10A、20A、30A所示，也可以不仅在金属基板11的表面侧的单面上、而且在背面侧、即在两面上设置陶瓷层12、电极层13、钎焊层14。根据需要，也可以在陶瓷层12与电极层13之间插入陶瓷层保护膜24。
本发明的金属-陶瓷复合基板10、10A、20、20A、30、30A的特征在于，在低成本的金属基板11的表面上形成了散热性良好的陶瓷薄膜的陶瓷层12。根据本发明的金属-陶瓷复合基板10、10A、20、20A、30、30A，由于能够形成热阻较小的接合，所以使用金属-陶瓷复合基板10、10A、20、20A、30、30A的半导体装置的热阻变小，能够提高半导体装置的性能及寿命。
接着，对本发明的金属-陶瓷复合基板的制造方法进行说明。
首先，准备金属基板11，在将其两面研磨后，清洗研磨后的金属基板11，进行表面清洁化，在金属基板11的表面上形成作为陶瓷层12的AlN薄膜。该陶瓷层12例如可以通过PVD法(物理气相沉积法：physical vapor deposition)或CVD法(化学气相沉积法：chemicalvapor deposition)形成。
接着，进行光刻法的布图。具体而言，在利用旋涂机于金属基板11的表面整体上均匀地涂布抗蚀剂后，通过烘烤炉进行规定的烘烤，利用掩模对准器装置进行伽玛线接触曝光。
在曝光后，通过四甲胺类的显影液将作为电极层13的部分的抗蚀剂溶解，使陶瓷层12露出。
接着，通过提离工序在陶瓷层12的上表面上进行电极层13的形成。具体而言，通过抗蚀剂剥离液将在上述布图工序中形成的抗蚀剂膜与蒸镀在抗蚀剂膜该的金属层一起利用抗蚀剂膜的膨润而除去。由此，能够在陶瓷层12上形成具有规定的图案的电极层13。作为抗蚀剂剥离液，可以使用丙酮、异丙醇或其它抗蚀剂剥离液。
与上述电极层13同样，进行利用光刻法及真空蒸镀装置的提离工序，在形成于金属基板11的表面上形成的电极层13的一部分上形成钎焊层14。
将得到的金属基板11利用切片装置等分割为规定的热沉10的尺寸。以上，金属-陶瓷复合基板10便告完成。
在上述金属-陶瓷复合基板20的情况下，只要与电极层13上的钎焊层14的形成同时形成在陶瓷层12上形成的钎焊层22就可以。
在上述金属-陶瓷复合基板30的情况下，在陶瓷层12的形成后，在陶瓷层12的表面的整面上形成作为陶瓷层保护膜24的金属膜。然后的工序可以与金属-陶瓷复合基板10的情况同样地进行。在钎焊层14的形成后，只要根据需要将不需要的陶瓷层保护膜24通过蚀刻除去就可以。
此外，在本发明的金属-陶瓷复合基板10A、20A、30A的情况下，可以通过不仅在基板表面侧、还用与金属基板11的表面侧同样的工序在其背面侧也设置陶瓷层12、电极层13、钎焊层14来制造。根据需要，也可以在陶瓷层12与电极层13之间插入陶瓷层保护膜24。
本发明的金属-陶瓷复合基板10、10A、20、20A、30、30A的制造方法的特征在于，在Cu、Al等的金属基板11的表面、或者表面及背面、即两面上形成AlN等的陶瓷层12。根据本发明的金属-陶瓷复合基板10、10A、10、20A、30、30A的制造方法，与半导体装置15的热阻较小，能够低成本、成品率较高地制造散热性良好的金属-陶瓷复合基板。
实施例
以下，基于实施例更详细地说明本发明。
首先，对实施例的金属-陶瓷复合基板30A的制造方法进行说明。
清洗由大小为50mm×50mm、厚度为300μm、热传导率为300W/mK的Cu构成的金属基板11的两面而进行表面清洁化，在该金属基板11的表面及背面整体上，通过PVD法形成由厚度为10μm的AlN构成的陶瓷层12。作为PVD法，使用溅镀装置。作为靶而使用Al，进而，通过同时供给氮气而沉积AlN薄膜12。该AlN薄膜的热传导率为200W/mK。
接着，在AlN薄膜12的表面及背面的整面上，通过真空蒸镀装置沉积0.05μm的作为陶瓷层保护膜24的、热传导率为20W/mK的Ti。
为了进行光刻法的布图，在利用旋涂机将抗蚀剂均匀地涂布在形成有AlN薄膜12及陶瓷层保护膜24的金属基板11的表面整体上后，通过烘烤炉进行规定的烘烤，利用掩模对准器装置进行伽玛线接触曝光。曝光用的掩模将掩模设计为，使其能够以1mm见方的热沉尺寸同时布图2500个。
在曝光后，通过四甲胺类显影液，将作为电极层13的部分的抗蚀剂溶解，使陶瓷层保护膜24露出。此时，在金属基板11的背面侧的陶瓷层保护膜24上没有实施布图。
在通过真空蒸镀装置在金属基板11的表面及背面侧形成的陶瓷层保护膜24上蒸镀热传导率为315W/mK的金，对形成于金属基板11的表面侧的陶瓷层保护膜24上的抗蚀剂图案实施提离工序。具体而言，通过利用丙酮使抗蚀剂整体溶解，将电极层13以外的Au除去，形成规定的电极层13。电极层13的厚度是0.1μm，其尺寸在两面上都是800μm见方。
与电极层13同样，利用光刻法及真空蒸镀装置，在形成于金属基板11的表面上的电极层13的一部分上，通过提离工序形成厚度为5μm的钎焊层14。作为钎焊层14，使用热传导率为50W/mK的Au0.8Sn0.2(元素比)。钎焊层14的尺寸是半导体元件接合面为500μm见方、热沉接合面为800μm见方。此时，在设于金属基板11的背面侧的Au层上的钎焊层14上没有实施布图。
将得到的金属基板11利用切片装置切断为1mm见方，从而制造出实施例的金属-陶瓷复合基板30A。
接着，对比较例进行说明。
(比较例1)
如图8所示，在由热传导率为200W/mK、厚度为520μm的AlN构成的陶瓷基板51的表面及背面上，通过蒸镀法形成由厚度为0.05μm的Ti及厚度为0.1μm的Au构成的电极层52及厚度为5μm的Au0.8Sn0.2(元素比)构成的钎焊层53，制造陶瓷基板的电路基板50。陶瓷基板51的大小与设在其表面侧的电极层52及钎焊层53的图案尺寸与实施例相同。
(比较例2)
如图9所示，在由热传导率为300W/mK、厚度为500μm的Cu构成的金属基板61的两面上，形成厚度为10μm的填料(10W/mK)的绝缘层62，从其上方通过蒸镀法形成由厚度为0.05μm的Ti及厚度0.1μm的Au构成的电极层63及由厚度为5μm的Au0.8Sn0.2(元素比)构成的钎焊层64，制造电路基板60。金属基板61的大小与设在其表面侧的电极层63及钎焊层64的图案尺寸与实施例相同。
在下述中，对实施例的金属-陶瓷复合基板30A及比较例1、2的电路基板50、60的各特性进行说明。
对于在实施例中制造的金属-陶瓷复合基板30A及在比较例1、2中制造的电路基板50、60，分别对钎焊层接合发光二极管，测量通电后的温度上升及热阻(参照表1)。
表1
Figure S2006800278824D00131
在实施例的金属-陶瓷复合基板30A中，热阻是2.0℃/W，芯片侧温度与散热侧温度的温度差是3.0℃。相对于此，在比较例1的电路基板50中，热阻是2.8℃/W，芯片侧温度与散热侧温度的温度差是4.2℃。在比较例2的电路基板60中，热阻是3.9℃/W，芯片侧温度与散热侧温度的温度差是5.8℃。
根据上述实施例及比较例，在搭载实施例的半导体装置15的金属-陶瓷复合基板30A中，通过在金属基板11的表面上形成陶瓷薄膜的陶瓷层12，能够得到低成本并且热阻较小的金属-陶瓷复合基板30A。
本发明并不限于上述实施例所述的发光二极管，只要是具有背面电极的半导体装置或电路部件就能够使用，在权利要求书所述的发明的范围内能够进行各种变形，这些变形当然也包含在本发明的范围内。例如，半导体装置并不限于发光二极管等。作为金属基板11，对使用Cu、Al的情况进行了说明，但本发明并不局限于此，金属基板11也可以由其它金属构成。
在上述实施方式中，陶瓷层12由AlN构成，但并不限于此，也可以由其它陶瓷材料构成。电极层13及钎焊层14的图案只要适当地设计以使其成为目的的电路结构就可以。

Claims (11)

1.一种金属-陶瓷复合基板，其特征在于，其具备：金属基板、形成在该金属基板上的陶瓷层、形成在该陶瓷层上的陶瓷层保护膜、形成在该陶瓷层保护膜上的电极层、和形成在该电极层上的钎焊层；
其中，所述陶瓷层由陶瓷薄膜构成。
2.如权利要求1所述的金属-陶瓷复合基板，其特征在于，还在没有形成所述陶瓷层保护膜的区域的所述陶瓷层上直接形成有另外的钎焊层。
3.如权利要求1所述的金属-陶瓷复合基板，其特征在于，所述陶瓷层、所述陶瓷层保护膜、所述电极层和所述钎焊层分别层叠在所述金属基板的表面和背面这两面上。
4.如权利要求1所述的金属-陶瓷复合基板，其特征在于，所述金属基板由铜或铝构成。
5.如权利要求1～3中任一项所述的金属-陶瓷复合基板，其特征在于，所述陶瓷层由氮化物类陶瓷构成。
6.如权利要求5所述的金属-陶瓷复合基板，其特征在于，所述氮化物类陶瓷是氮化铝。
7.一种金属-陶瓷复合基板的制造方法，其特征在于，其是由金属基板、形成在该金属基板上的陶瓷层、形成在该陶瓷层上的陶瓷层保护膜、形成在该陶瓷层保护膜上的电极层、和形成在该电极层上的钎焊层构成的金属-陶瓷复合基板的制造方法，其包括：
在所述金属基板的表面上形成陶瓷薄膜作为所述陶瓷层的工序；
在所述陶瓷薄膜上的整面上形成陶瓷层保护膜的工序；
在所述陶瓷层保护膜上形成规定的图案的所述电极层和所述钎焊层的工序；
在形成所述规定的图案的所述电极层和所述钎焊层后，将没有形成该规定的图案的区域的不需要的陶瓷层保护膜除去的工序。
8.如权利要求7所述的金属-陶瓷复合基板的制造方法，其特征在于，还包括在没有形成所述陶瓷层保护膜的区域的所述陶瓷层上直接形成另外的钎焊层的工序。
9.如权利要求7所述的金属-陶瓷复合基板的制造方法，其特征在于，在所述金属基板的表面和背面这两面上分别形成所述陶瓷层、所述陶瓷层保护膜、所述电极层和所述钎焊层。
10.如权利要求7～9中任一项所述的金属-陶瓷复合基板的制造方法，其特征在于，所述陶瓷层由氮化物类陶瓷构成。
11.如权利要求10所述的金属-陶瓷复合基板的制造方法，其特征在于，所述氮化物类陶瓷是氮化铝。
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Publication number Priority date Publication date Assignee Title
CN101298659B (zh) * 2007-04-30 2010-12-01 汉达精密电子(昆山)有限公司 绝缘导热金属基板的制造方法
CN101572998B (zh) * 2008-04-29 2012-07-18 汉达精密电子(昆山)有限公司 绝缘导热金属基板上真空溅镀形成导电线路的方法
CN101572993B (zh) * 2008-04-29 2012-10-03 汉达精密电子(昆山)有限公司 绝缘导热金属基板上真空溅镀形成导电线路的方法
CN101573001B (zh) * 2008-04-29 2012-07-04 汉达精密电子(昆山)有限公司 绝缘导热金属基板上真空溅镀形成导电线路的方法
CN101572996B (zh) * 2008-04-29 2011-12-07 汉达精密电子(昆山)有限公司 绝缘导热金属基板上真空溅镀形成导电线路的方法
US9387532B2 (en) * 2009-02-13 2016-07-12 Denka Company Limited Composite substrate for LED light emitting element, method of production of same, and LED light emitting element
DE102009014993B4 (de) * 2009-03-26 2011-07-14 Continental Automotive GmbH, 30165 Verfahren zum elektrischen Kontaktieren eines elektronischen Bauelements
DE102009017434A1 (de) * 2009-04-15 2010-10-28 Continental Automotive Gmbh Elektronisches Bauelement und Verfahren zum elektrischen Kontaktieren eines elektronischen Bauelements als Stapel
KR101039771B1 (ko) 2009-05-20 2011-06-09 권오국 고방열 금속판을 이용한 피씨비 제조방법
KR101045847B1 (ko) * 2009-06-12 2011-07-01 (주)솔라원 열 계면층을 갖는 메탈 인쇄회로기판
KR101167425B1 (ko) * 2010-09-16 2012-07-23 삼성전기주식회사 방열기판 및 그 제조방법
CN102054713A (zh) * 2010-09-26 2011-05-11 浙江大学 金属基氮化铝板绝缘基板制备方法
US8803183B2 (en) 2010-10-13 2014-08-12 Ho Cheng Industrial Co., Ltd. LED heat-conducting substrate and its thermal module
CN103117335A (zh) * 2011-11-16 2013-05-22 和淞科技股份有限公司 具有电路的复合式金属陶瓷基板的制法及其结构
CN103114261A (zh) * 2011-11-16 2013-05-22 和淞科技股份有限公司 复合式金属陶瓷基板的制法及其结构
WO2014073038A1 (ja) * 2012-11-06 2014-05-15 日本碍子株式会社 発光ダイオード用基板
JP6125528B2 (ja) * 2012-11-06 2017-05-10 日本碍子株式会社 発光ダイオード用基板および発光ダイオード用基板の製造方法
US9726357B2 (en) * 2013-02-06 2017-08-08 Sharp Kabushiki Kaisha Light-emitting device
CN103166103A (zh) * 2013-03-18 2013-06-19 中国工程物理研究院应用电子学研究所 一种水电绝缘的半导体激光器线阵的封装方法
DE102014116529A1 (de) 2014-11-12 2016-05-12 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauteil und Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils
JP6311887B2 (ja) * 2015-05-15 2018-04-18 豊田合成株式会社 発光素子用基板および発光装置
WO2018060231A1 (en) 2016-09-27 2018-04-05 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Highly thermally conductive dielectric structure for heat spreading in component carrier
JP2018142569A (ja) * 2017-02-27 2018-09-13 株式会社アカネ 放熱基板
CN107708296A (zh) * 2017-10-19 2018-02-16 深圳职业技术学院 一种高导热的金属基电路板及其制作方法
TWI656231B (zh) * 2017-12-05 2019-04-11 國家中山科學研究院 Method for preparing polycrystalline aluminum nitride high reflection mirror
DE102018104521B4 (de) 2018-02-28 2022-11-17 Rogers Germany Gmbh Metall-Keramik-Substrate
CN109390843A (zh) * 2018-12-10 2019-02-26 业成科技（成都）有限公司 发射模组及其制作方法
CN111490018A (zh) * 2019-01-29 2020-08-04 瑷司柏电子股份有限公司 具有金属导热凸块接垫的陶瓷基板元件、组件及制法
CN114727504A (zh) * 2022-03-16 2022-07-08 景旺电子科技(龙川)有限公司 金属陶瓷复合基板及其制作方法
TWI822346B (zh) * 2022-09-20 2023-11-11 健策精密工業股份有限公司 電子裝置及其製造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57122592A (en) * 1981-01-23 1982-07-30 Tokyo Shibaura Electric Co Method of producing hybrid integrated circuit
JPH0697663B2 (ja) * 1986-01-10 1994-11-30 沖電気工業株式会社 半導体素子の製造方法
JP2664744B2 (ja) * 1988-11-02 1997-10-22 株式会社東芝 窒化アルミニウム薄膜回路基板
JP3156798B2 (ja) 1991-07-24 2001-04-16 電気化学工業株式会社 半導体搭載用回路基板
JP2762007B2 (ja) 1992-12-04 1998-06-04 住友金属工業株式会社 金属薄膜積層セラミックス基板
US5965193A (en) * 1994-04-11 1999-10-12 Dowa Mining Co., Ltd. Process for preparing a ceramic electronic circuit board and process for preparing aluminum or aluminum alloy bonded ceramic material
JP2000077583A (ja) * 1998-09-03 2000-03-14 Sumitomo Metal Electronics Devices Inc 電子部品用パッケージおよびその製造方法
JP3092603B2 (ja) * 1998-11-02 2000-09-25 日本電気株式会社 半導体素子実装基板又は放熱板とその製造方法及び該基板又は放熱板と半導体素子との接合体
JP3648189B2 (ja) * 2001-09-28 2005-05-18 同和鉱業株式会社 金属−セラミックス回路基板
JP2004031485A (ja) * 2002-06-24 2004-01-29 Nissan Motor Co Ltd 半導体装置
JP2004119515A (ja) * 2002-09-24 2004-04-15 Neo Led Technology Co Ltd 高い放熱性を有する発光ダイオード表示モジュール及びその基板
US6854636B2 (en) * 2002-12-06 2005-02-15 International Business Machines Corporation Structure and method for lead free solder electronic package interconnections
JP4132038B2 (ja) * 2003-03-24 2008-08-13 京セラ株式会社 発光装置
SG162619A1 (en) * 2003-04-15 2010-07-29 Denki Kagaku Kogyo Kk Metal base circuit board and its production process
JP2005116621A (ja) * 2003-10-03 2005-04-28 Nissan Motor Co Ltd 半導体装置
US7193838B2 (en) * 2003-12-23 2007-03-20 Motorola, Inc. Printed circuit dielectric foil and embedded capacitors
JP2006269966A (ja) * 2005-03-25 2006-10-05 Toyota Industries Corp 配線基板およびその製造方法

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
JP特开2004-119515A 2004.04.15
JP特开2004-288935A 2004.10.14
JP特开2004-31485A 2004.01.29

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