CN101227797A - 电子器件的制造方法 - Google Patents

电子器件的制造方法 Download PDF

Info

Publication number
CN101227797A
CN101227797A CNA2007101959646A CN200710195964A CN101227797A CN 101227797 A CN101227797 A CN 101227797A CN A2007101959646 A CNA2007101959646 A CN A2007101959646A CN 200710195964 A CN200710195964 A CN 200710195964A CN 101227797 A CN101227797 A CN 101227797A
Authority
CN
China
Prior art keywords
matrix
film
circuit chip
resinoid
electronic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2007101959646A
Other languages
English (en)
Other versions
CN100584152C (zh
Inventor
小林弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of CN101227797A publication Critical patent/CN101227797A/zh
Application granted granted Critical
Publication of CN100584152C publication Critical patent/CN100584152C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • G06K19/07754—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna the connection being galvanic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75703—Mechanical holding means
    • H01L2224/75704—Mechanical holding means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9221—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0271—Mechanical force other than pressure, e.g. shearing or pulling
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Credit Cards Or The Like (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

一种制造电子器件的制造方法，包括下列步骤：在基体表面上涂敷热固性粘合剂，所述基体具有膜上形成的导体图案；通过热固性粘合剂将电路芯片安装在基体上；在由对热固性粘合剂进行加热的加热设备对基体的电路芯片侧和基体的膜侧挤压的同时夹持基体；向安装了电路芯片的基体施加张力；以及由加热设备对热固性粘合剂加热以使热固性粘合剂固化，从而将电路芯片固定到导体图案。

Description

电子器件的制造方法
技术领域
本发明涉及电子器件的制造方法，特别是电路芯片安装在膜状基体上的电子器件的制造方法。
背景技术
传统上，公知一种电子器件，在该器件中，电路芯片安装在基体(例如印刷电路板)上。这样的电子器件用在例如下述应用中：布置在电子设备中来控制该电子设备，或者单独使用来与外部设备交换信息。例如，作为这样的电子器件，已有各种RFID(射频识别)标签，它们用无线电波以非接触方式与以读取器/写入器为代表的外部设备交换信息。作为这些RFID标签中的一种，已提出的一种RFID标签具有这样的结构：其中，用于射频通信的导体图案和IC芯片安装在基体板上。这种RFID标签的一种可想到的应用形式是将该RFID标签附装到物体上并与外部设备交换信息来执行物体的识别。
RFID需要小型化和减轻重量，具体地说，希望更薄、更灵活和更低成本。响应于这种需求，例如已经提出了一种RFID标签，其中，由例如聚对苯二甲酸乙二酯(PET)的树脂制成的膜用作安装IC芯片的基体(例如参见日本专利申请公开No.2001-156110)的材料。
图9是示出根据传统技术制造RFID标签的方法的示意图。
在图9的部分(a)至部分(d)中，依次示出了制造RFID标签的各个步骤。
在制造RFID标签时，首先，如图9的部分(a)所示来预备基体，在基体中，导体图案912形成于膜911上，并将加热固化的热固性粘合剂93p粘附到基体91，其中导体图案912用作RFID标签的天线。
接着，如图9的部分(b)所示，将IC芯片92安装在基体91的涂覆有热固性粘合剂93p的那部分上。IC芯片92上形成有连接到导体图案912的突起921。如图9的部分(c)所示，将IC芯片92以这样的方式安装在基体91上：突起921与导体图案912的位置匹配。
接着，如图9的部分(d)所示，将安装有IC芯片92的基体91从两侧(即基体91的膜911那侧和IC芯片92那侧)夹在加热设备8的部分81与82之间。接着，由与加热设备8的IC芯片92那侧抵靠的加热头81对热固性粘合剂93进行加热使之硬化。这样，以突起921接触导体图案912的状态将IC芯片92固定到基体91上。因此完成了小型化的轻便RFID标签。
但是，在对热固性粘合剂93p进行固化时，用于膜911的材料容易因受热而发生形变，因为PET的玻璃化转变温度约为67摄氏度，PET的耐热温度较低。
图10是对图9的部分(d)中的加热步骤中的基体状态进行说明的示意图。
如图10的部分(a)所示，在IC芯片92安装在基体91上的状态下执行加热时，基体91的温度升高，如图9的部分(b)所示，膜911发生形变。在热固性粘合剂93p由于膜911的形变而流动时，有气泡产生于热固性粘合剂93p内部并在热固性粘合剂93p固化之后以空洞931的形式留下来。由于固化的热固性粘合剂93p中的空洞931降低了IC芯片92与基体91之间的粘附性，所以降低了RFID标签的可靠性。
由于这种空洞而造成的可靠性降低问题不限于RFID标签，而是对于其中电路芯片安装在膜状基体上的电子器件所共有的。
发明内容
考虑到上述情况，本发明的一个目的是提供一种电子器件的制造方法，通过防止空洞产生而具有更高的可靠性。
根据本发明，一种制造电子器件的制造方法，包括下列步骤：
在基体的表面上涂敷热固性粘合剂，所述基体形成为使导体图案形成于由树脂制成的膜上，所述基体的所述表面是所述基体中形成有所述导体图案的那侧；
通过所述热固性粘合剂把将要与所述导体图案连接的电路芯片安装在所述基体上；
由对所述热固性粘合剂进行加热的加热设备在对所述基体的电路芯片侧和所述基体的膜侧挤压的同时夹持所述基体，所述加热设备包括施压部分和支撑部分，所述施压部分通过与所述基体的所述电路芯片侧抵靠来对所述基体施压，所述支撑部分通过与所述基体的所述膜侧抵靠而支撑所述基体；
沿所述膜伸展的方向对安装了所述电路芯片的所述基体施加张力；和
由所述加热设备对所述热固性粘合剂加热以使所述热固性粘合剂固化，从而将所述电路芯片固定到所述导体图案。
在根据本发明制造电子器件的制造方法中，由于沿膜伸展的方向向基体施加了张力，所以在膜受热熔融时抑制了膜的形变。因而，在热固性粘合剂中抑制了由膜的形变造成的空洞产生。另外，电子器件的产品成品率提高，从而降低了制造成本。
这里，在上述发明的制造电子器件的制造方法中，优选地，制造电子器件的制造方法还包括在所述膜的安装区域两侧设置成对保持突起的步骤，所述安装区域中安装有所述电路芯片，其中，所述施加张力的步骤是沿着使所述成对保持突起彼此分离的方向对所述成对保持突起进行牵引的步骤。
在施加张力的步骤中，设置成对保持突起，并沿使成对保持突起彼此远离运动的方向牵引它们，从而可以容易地沿膜伸展的方向施加张力。
另外，在上述发明的制造电子器件的制造方法中，所述施加张力的步骤可以是对所述膜的所述安装区域两侧的所述膜的部分进行夹持、并沿着使所述部分彼此远离运动的方向对所述部分进行牵引的步骤，所述安装区域中安装有所述电路芯片。
此外，在上述发明的的制造电子器件的制造方法中，优选地，其中，
所述基体被形成为使得多个导体图案并排布置在膜的片上，
所述涂敷步骤是向所述基体上的所述多个导体图案中每一者涂敷热固性粘合剂的步骤，
所述安装步骤是将多个电路芯片中每一者安装在所述基体上的步骤，其使每个所述电路芯片与所述多个导体图案中每一者相连，
所述夹持步骤是对所述多个导体图案中每一者进行夹持的步骤，其使得所述基体上的所述多个导体图案中位于彼此相邻的导体图案之间的所述膜的部分保持不被夹持，
所述施加张力步骤是通过由固定装置对所述夹持步骤中保持不被夹持的所述膜的所述部分进行牵引，来对所述基体施加张力的步骤，
所述制造方法还包括对所述基体进行切割以形成多个电子器件的步骤。
在通过对安装了多个电路芯片的基体进行切割来形成多个电子器件的情况下，在夹持步骤中，使导体图案之间的膜部分保持不被夹持，并对该部分进行牵引，从而容易对基体施加张力。
如上所述，根据本发明，抑制了空洞产生，从而可以获得具有高可靠性的电子器件的制造方法。
附图说明
图1是示出根据本发明一种实施例制造的RFID标签的立体图。
图2是对作为本发明一种实施例、制造如图1所示RFID的制造方法中的各个步骤进行说明的示意图。
图3是示出图2的部分(a)至(e)所示步骤之后的制造步骤的示意图。
图4是示出图3的部分(f)和(g)所示步骤之后的制造步骤的示意图。
图5是示出基体的俯视图，所述基体设有图2的部分(b)所示设置突起步骤中的保持销。
图6是对作为本发明的第二实施例、制造RFID的制造方法中各个步骤进行说明的示意图。
图7是对作为本发明的第三实施例、制造RFID的制造方法中各个步骤进行说明的示意图。
图8是示出图7所示步骤之后的制造步骤的示意图。
图9是对传统技术中RFID的制造方法进行说明的示意图。
图10是对图9所示加热步骤中基体状态进行说明的示意图。
具体实施方式
下面将参考附图对本发明的实施例进行说明。
图1的立体图示出了根据本发明一种实施例制造的RFID标签。
图1所示RFID标签1包括：基体11，其中，金属制成的天线图案112形成于PET材料制成的膜111上；IC芯片12，安装在基体11上；以及热固性粘合剂13，将IC芯片12粘合到基体11。
RFID标签1是电子器件，其以非接触的方式与读取写入器交换信息。RFID标签1通过天线图案112以电能的形式接收由读取写入器发射的电磁能量，该电能驱动IC芯片12以实现通信操作。
这里，RFID标签1、天线图案112和IC芯片12分别对应于根据本发明的电子器件、导体图案和电路芯片的示例。
在某些情况下，对于与本发明对应的技术领域的技术人员，说明中所用的“RFID标签”也可以称为“RFID标签嵌体(inlay)”，作为“RFID标签”的内部组件(嵌体)。在某些其他情况下，这种“RFID标签”也称为“无线IC标签”。另外，这种“RFID标签”也包括非接触式的IC卡。
下面将说明制造这种RFID标签1的方法。
图2、图3和图4是对作为本发明的一种实施例、制造图1所示RFID的制造方法进行说明的示意图。
图2中在部分(a)至部分(e)依次示出了RFID标签1的制造方法中包括的各个处理。图3中在部分(f)和(g)依次示出了图2所示步骤之后的各个步骤。图4的部分(h)和(i)依次示出了图3所示步骤之后的各个步骤。为了方便观看，与图1所示的尺寸相比，以夸大方式表示出了RFID标签1以及IC芯片12在IC芯片厚度方向上的尺寸。
为了制造RFID标签1，首先，在图2的部分(a)所示的导体形成步骤中，在膜111的安装表面11a上形成天线图案112。天线图案112是通过下述方式形成的：在膜111上形成由铜制成的层，再形成抗蚀层并执行刻蚀。具体地说，也可以通过印刷银膏或其他方法来形成天线图案112。在导体形成步骤中，获得了基体11，其中天线图案112形成于膜111上。在随后的步骤中，IC芯片将被安装在基体11的安装表面11a那侧的安装区域11c上。膜111被形成为比天线图案112更长。
接着，在图2的部分(b)所示设置突起的步骤中，在膜111的安装区域11c的两侧设置保持销16，安装区域11c位于它们之间。
图5是示出基体的俯视图，其中，在图2的部分(b)所示的设定突起的步骤中设置了保持销。在本实施例中，两对保持销16由树脂材料制成并具有柱形形状，设在膜111的端部111s上，端部111s位于其间的安装区域11c两侧，天线图案112朝向这些端部延伸。保持销16对应于根据本发明的保持突起的一种示例。
接着，在图2的部分(c)所示的粘附步骤中，将液态的热固性粘合剂13p涂覆到基体11上。热固性粘合剂13p具有流动性，并被涂到基体11的安装表面11a的安装区域11c及其周边，安装区域11c中安装IC芯片12。
接着，在图2的部分(d)和(e)所示的安装步骤中，IC芯片12被安装在基体11的安装区域11c上。用倒装芯片技术将IC芯片12安装在基体11上。即，通过热固性粘合剂13p在下述位置将IC芯片12安装在基体11上：在所述位置，形成有电路的表面12a面向基体11。在IC芯片12上形成有电路的表面12a上，形成要与天线图案112相连的突起121。如图2的部分(e)所示，IC芯片12以下述状态安装在基体11上：所述状态是突起121与天线图案112的位置对准。
接着，在图3的部分(f)所示的夹持步骤中，安装有IC芯片12的基体被加热设备2夹持，同时从两侧(即，基体11的膜侧111和IC芯片12侧)受压。加热设备2具有加热头21和加热台22，二者用于夹住基体11。加热头容纳有未示出的加热器。在夹持步骤中，加热头21抵靠IC芯片12，加热台22抵靠膜111。通过图3的部分(f)所示的夹持步骤，使突起121与天线图案112可靠接触。加热设备2、加热头21和加热台22分别对应于根据本发明的制造电子器件的制造设备、加热部分和支撑部分的示例。
接着，在图3的部分(g)所示的施加张力步骤中，对成对的保持销16进行牵引。根据本实施例的加热设备2设有成对的牵引部分23，用于牵引保持销16。在施加张力步骤中，牵引部分23与保持销16抵靠并沿与安装区域11c相反的方向牵引成对保持销，以使成对保持销16彼此远离地运动。由此，沿膜111伸展的方向赋予基体11张力。
接着，在图4的部分(h)所示的加热步骤中，使加热头21产生热量，从而使热固性粘合剂13p受热并固化。通过对热固性粘合剂13p进行固化，IC芯片12以突起12与天线图案112接触的状态固定到基体11。由于在沿膜111伸展的方向赋予基体11张力的状态下执行加热步骤，所以虽然膜111受热要熔融，但膜111的膨胀被吸收，从而抑制了膜111的形变。因此，防止了由于膜的形变而在热固性粘合剂13p中产生空洞。
接着，在图4的部分(i)所示的去除步骤中，将膜111两侧的端部111s与保持销16一起去除。
在图4的部分(i)的去除步骤完成时，获得了RFID标签1(参见图1)。
接下来将说明根据本发明的第二实施例，与上述实施例中不同的制造方法。在对第二实施例的下述说明中，与上述实施例中相同的各个元件将用与上述实施例中相同的符号来标记，并将主要说明第二实施例与上述实施例之间的不同之处。下面，上述实施例可以称为第一实施例。
第二实施例的RFID标签具有与图1所示根据第一实施例的RFID标签1类似的构造。
在制造第二实施例的RFID标签时，不执行图2的部分(b)所示设置突起的步骤，RFID标签没有保持销。在制造第二实施例的RFID标签时，施加张力步骤的具体情况与图3的部分(g)所示步骤不同。图2的部分(a)所示导体形成步骤、图2的部分(c)至图3的部分(f)所示的粘附步骤、安装步骤和夹持步骤以类似于第一实施例的方式执行。
图6是对本发明第二实施例制造RFID的制造方法中各个步骤进行说明的示意图。
如图6所示，在用于制造第二实施例的RFID标签的加热设备6中未设置参考图3的部分(g)所述的牵引部分，而是设置了夹持部分63，夹持部分63具有夹住膜511的部分。
在图6的部分(a)所示的施加张力步骤中，一对夹持部分63分别在膜511的两侧夹持端部511s，使得安装有IC芯片12的安装区域11c位于其间并沿使端部511彼此远离运动的方向牵引两个端部511。由此，沿着膜511伸展的方向对基体51施加张力。
接着，在图6的部分(b)所示的加热步骤中，使加热设备6的加热头21对要固化的热固性粘合剂13p进行加热。与第一实施例的情况类似，由于在沿膜511伸展方向对基体51施加了张力的状态下执行加热步骤，所以虽然膜51受热熔融，但抑制了膜511的形变。
在图6的部分(b)所示施加张力步骤之后，类似于第一实施例，通过在图4的部分(i)所示去除步骤中去除膜的端部511s，完成与如图1所示根据第一实施例的RFID标签类似的RFID标签。
接着将说明根据本发明的第三实施例。在下面对第三实施例的说明中，与上述实施例分别相同的各个元件将用与上述实施例相同的符号来标记，并将主要说明第三实施例与上述实施例之间的差别。
第三实施例的RFID标签也具有与图1所示根据第一实施例的RFID标签1类似的构造。但是，第三实施例的RFID标签是在与根据第一实施例的RFID标签1不同的制造处理中制造的。根据第三实施例的RFID标签的制造是所谓的多芯片键合(multi-chip-bonding)，其中，在基体上一起形成要分别成为RFID标签的多个部分，然后将这些部分最终彼此分开以获得多个RFID标签。具体情况是：形成基体，使膜的片上并排形成与多个RFID标签对应的多个导体图案；在涂覆步骤中，将热固性粘合剂涂在多个导体图案的每一者上；在安装步骤中，在基体上安装多个IC芯片。但是，由于通过导体形成步骤、与图2的部分(a)和图2的部分(c)至图3的部分(e)所示的第一实施例的步骤类似的粘附步骤和安装步骤，所以对于这些步骤，省略了整个基体的附图。
图7和图8是对作为本发明第三实施例制造RFID的制造方法的各个步骤进行说明的示意图。
图7中一起示出了制造步骤的夹持步骤、施加张力步骤和加热步骤。在制造步骤中，图7所示步骤之后的切割步骤示于图8。
如图7所示，两个加热器件60A和60B布置在加热设备60中，加热设备60将用于制造根据第三实施例的RFID标签。两个加热器件60A和60B每一者包括加热头21和加热台22的组合。另外，用于对膜进行牵引的辊子67布置在加热器件60A与60B之间。一对夹持部分63布置在其间的辊子67两侧。辊子67对应于根据本发明的固定装置的一种示例。
在夹持步骤中，加热设备60用两个加热器件60A和60B将与多个RFID标签对应的彼此相邻的两个天线图案各自的部分夹持在膜711的片上形成的基体71上。在此情况下，加热设备60的加热器件60A和60B使两个天线图案112之间的部分711b保持原状。
接着，在施加张力步骤中，夹持部分63夹持膜711的端部711s，同时辊子67钩住膜711的两个天线图案112之间未被加热器件60A和60B夹持的剩余部分711b并将其向下牵引。由此向基体71施加张力。
接着，在加热步骤中，使加热设备60的加热头21产生热量并加热要固化的热固性粘合剂13p。由于加热步骤是在沿膜711伸展的方向施加了张力的状态下执行的，所以即使膜711受热熔融，也抑制了膜711的形变。
接着，在图8所示的切割步骤中，通过对基体71进行切割来形成多个RFID标签。在此情况下，未被加热器件60A和60B夹持的剩余部分711b以及端部711s被除去，从而完成与图1所示第一实施例类似的两个RFID标签。
另外，在上述实施例中，已经说明了制造RFID标签的方法和加热设备的示例。但是，本发明不限于针对RFID标签的方法，本发明可以应用于任何方法，只要该方法是用于制造有电路芯片安装在膜状基体上的电子器件。例如，本发明可以应用于例如下述制造方法：制造超薄膜IC卡或印刷电路板的方法，其中，电路芯片通过热固性粘合剂固定在作为基体的柔性印刷电路板(FPC)上。
另外，在上述实施例中，RFID标签的基体中包括的膜被描述为由PET材料制成。但是可应用本发明的电子器件的膜不限于这种示例。材料可以选自例如聚酯、聚烯烃、聚碳酸酯、或丙烯酸。
在上述实施例中，加热台被描述为非加热元件。但是，本发明不限于这样的示例。支撑部分也可以与加热部分一起进行加热。
此外，在上述第一实施例中，说明了这样的示例：两对具有柱形形状的保持销16设在膜111上。但是，本发明不限于这种示例。保持销的形状可以是例如长方体。保持销的数目可以是一对、三对或更多。保持销的材料可以是金属等。
此外，在上述第三实施例中，描述了这样的示例：由一个膜片形成两个RFID标签。但是，本发明不限于这种示例。可以由一个膜片形成三个或更多个RFID标签。另外，也可以在一个膜片上以矩阵形式布置多个RFID标签。

Claims (4)

1.一种制造电子器件的制造方法，包括下列步骤：
在基体的表面上涂敷热固性粘合剂，所述基体形成为使导体图案形成于由树脂制成的膜上，所述基体的所述表面是所述基体中形成有所述导体图案的那侧；
通过所述热固性粘合剂把将要与所述导体图案连接的电路芯片安装在所述基体上；
由对所述热固性粘合剂进行加热的加热设备在对所述基体的电路芯片侧和所述基体的膜侧挤压的同时夹持所述基体，所述加热设备包括施压部分和支撑部分，所述施压部分通过与所述基体的所述电路芯片侧抵靠来对所述基体施压，所述支撑部分通过与所述基体的所述膜侧抵靠而支撑所述基体；
沿所述膜伸展的方向对安装了所述电路芯片的所述基体施加张力；和
由所述加热设备对所述热固性粘合剂加热以使所述热固性粘合剂固化，从而将所述电路芯片固定到所述导体图案。
2.根据权利要求1所述的制造电子器件的制造方法，还包括在所述膜的安装区域两侧设置成对保持突起的步骤，所述安装区域中安装有所述电路芯片，其中，所述施加张力的步骤是沿着使所述成对保持突起彼此分离的方向对所述成对保持突起进行牵引的步骤。
3.根据权利要求1所述的制造电子器件的制造方法，其中，所述施加张力的步骤是对所述膜的所述安装区域两侧的所述膜的部分进行夹持、并沿着使所述部分彼此远离运动的方向对所述部分进行牵引的步骤，所述安装区域中安装有所述电路芯片。
4.根据权利要求1所述的制造电子器件的制造方法，其中，
所述基体被形成为使得多个导体图案并排布置在膜的片上，
所述涂敷步骤是向所述基体上的所述多个导体图案中每一者涂敷热固性粘合剂的步骤，
所述安装步骤是将多个电路芯片中每一者安装在所述基体上的步骤，其使每个所述电路芯片与所述多个导体图案中每一者相连，
所述夹持步骤是对所述多个导体图案中每一者进行夹持的步骤，其使得所述基体上的所述多个导体图案中位于彼此相邻的导体图案之间的所述膜的部分保持不被夹持，
所述施加张力步骤是通过由固定装置对所述夹持步骤中保持不被夹持的所述膜的所述部分进行牵引，来对所述基体施加张力的步骤，以及
所述制造方法还包括对所述基体进行切割以形成多个电子器件的步骤。
CN200710195964A 2007-01-18 2007-12-07 电子器件的制造方法 Expired - Fee Related CN100584152C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007009264 2007-01-18
JP2007009264A JP4860494B2 (ja) 2007-01-18 2007-01-18 電子装置の製造方法

Publications (2)

Publication Number Publication Date
CN101227797A true CN101227797A (zh) 2008-07-23
CN100584152C CN100584152C (zh) 2010-01-20

Family

ID=39322541

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200710195964A Expired - Fee Related CN100584152C (zh) 2007-01-18 2007-12-07 电子器件的制造方法

Country Status (7)

Country Link
US (1) US7605021B2 (zh)
EP (1) EP1947917B1 (zh)
JP (1) JP4860494B2 (zh)
KR (1) KR100945771B1 (zh)
CN (1) CN100584152C (zh)
DE (1) DE602007011881D1 (zh)
TW (1) TWI351243B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111612118A (zh) * 2019-02-26 2020-09-01 法国圣-戈班玻璃公司 具有改进的可读性的镀膜窗玻璃及其制造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5029026B2 (ja) * 2007-01-18 2012-09-19 富士通株式会社 電子装置の製造方法
CN102738055B (zh) * 2011-04-13 2015-07-01 颀中科技（苏州）有限公司 一种覆晶封装系统及其挑高夹具
WO2013172847A1 (en) * 2012-05-17 2013-11-21 Intel Corporation Film insert molding for device manufacture
JP6679244B2 (ja) 2015-08-27 2020-04-15 富士通株式会社 Ｒｆｉｄタグ

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5261155A (en) * 1991-08-12 1993-11-16 International Business Machines Corporation Method for bonding flexible circuit to circuitized substrate to provide electrical connection therebetween using different solders
JP3030201B2 (ja) * 1994-04-26 2000-04-10 富士通株式会社 半導体装置の製造方法及び半導体装置の製造装置
US6870272B2 (en) * 1994-09-20 2005-03-22 Tessera, Inc. Methods of making microelectronic assemblies including compliant interfaces
US6099678A (en) * 1995-12-26 2000-08-08 Hitachi Chemical Company Ltd. Laminating method of film-shaped organic die-bonding material, die-bonding method, laminating machine and die-bonding apparatus, semiconductor device, and fabrication process of semiconductor device
JP3402232B2 (ja) 1998-12-25 2003-05-06 株式会社デンソー Ｉｃカード製造方法
JP3447602B2 (ja) * 1999-02-05 2003-09-16 シャープ株式会社 半導体装置の製造方法
JP2000357859A (ja) * 1999-06-14 2000-12-26 Seiko Epson Corp 導電膜貼着装置及び導電膜貼着方法
JP2001044239A (ja) * 1999-07-29 2001-02-16 Matsushita Electric Ind Co Ltd 電子部品の混載実装方法及びその混載実装工程に用いる部材
JP3451373B2 (ja) 1999-11-24 2003-09-29 オムロン株式会社 電磁波読み取り可能なデータキャリアの製造方法
JP4445624B2 (ja) * 1999-12-28 2010-04-07 パナソニック株式会社 Ｉｃチップのフィルム状回路基板への接合方法及びｉｃチップ接合体
JP3659133B2 (ja) * 2000-06-23 2005-06-15 セイコーエプソン株式会社 半導体装置の製造方法
JP2004221334A (ja) * 2003-01-15 2004-08-05 Seiko Epson Corp 金属素子形成方法、半導体装置の製造方法及び電子デバイスの製造方法、半導体装置及び電子デバイス、並びに電子機器
JP4010962B2 (ja) * 2003-02-20 2007-11-21 三井金属鉱業株式会社 電子部品実装用フィルムキャリアテープの搬送装置および搬送方法
JP2006049591A (ja) * 2004-08-05 2006-02-16 Disco Abrasive Syst Ltd ウエーハに貼着された接着フィルムの破断方法および破断装置
JP3992038B2 (ja) * 2004-11-16 2007-10-17 セイコーエプソン株式会社 電子素子の実装方法、電子装置の製造方法、回路基板、電子機器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111612118A (zh) * 2019-02-26 2020-09-01 法国圣-戈班玻璃公司 具有改进的可读性的镀膜窗玻璃及其制造方法

Also Published As

Publication number Publication date
CN100584152C (zh) 2010-01-20
KR100945771B1 (ko) 2010-03-08
EP1947917A2 (en) 2008-07-23
TW200833204A (en) 2008-08-01
EP1947917A3 (en) 2009-11-11
JP4860494B2 (ja) 2012-01-25
US20080176361A1 (en) 2008-07-24
JP2008177352A (ja) 2008-07-31
DE602007011881D1 (de) 2011-02-24
TWI351243B (en) 2011-10-21
KR20080068530A (ko) 2008-07-23
US7605021B2 (en) 2009-10-20
EP1947917B1 (en) 2011-01-12

Similar Documents

Publication Publication Date Title
JP4479209B2 (ja) 電子回路装置およびその製造方法並びに電子回路装置の製造装置
CN100584152C (zh) 电子器件的制造方法
KR100712576B1 (ko) Ｒｆｉｄ 태그의 제조 방법
CN100584153C (zh) 电子器件及其制造方法
JP2007042087A (ja) Ｒｆｉｄタグ及びその製造方法
JP2007115249A (ja) プレアプライド接着材を有するｒｆｉｄアンテナ
AU2005234764B2 (en) Method of forming RFID circuit assembly
JP7154288B2 (ja) 無線周波数識別トランスポンダを製造するための方法及び装置
CN101226886A (zh) 用于制造电子器件的方法和装置
KR100923943B1 (ko) 전자 장치 및 전자 장치의 제조 방법
EP4104101B1 (en) Transfer of rfid inlays from a first substrate to a second substrate
JP2010141275A (ja) 半導体チップの実装方法
JP2002312749A (ja) コンビ型ｉｃカードの製造方法
US20060261957A1 (en) Method for producing bridge modules
JP2006114771A (ja) 回路基板、回路素子実装基板、及び回路素子実装基板製造方法
JP2004031580A (ja) 液晶表示装置
JP2003337929A (ja) 外部端子を有する非接触通信媒体

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100120

Termination date: 20141207

EXPY Termination of patent right or utility model