CN101211798B - 焊料凸块结构及其制作方法 - Google Patents

焊料凸块结构及其制作方法 Download PDF

Info

Publication number
CN101211798B
CN101211798B CN2007101120227A CN200710112022A CN101211798B CN 101211798 B CN101211798 B CN 101211798B CN 2007101120227 A CN2007101120227 A CN 2007101120227A CN 200710112022 A CN200710112022 A CN 200710112022A CN 101211798 B CN101211798 B CN 101211798B
Authority
CN
China
Prior art keywords
underlying metal
projection underlying
layer
projection
mask layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2007101120227A
Other languages
English (en)
Other versions
CN101211798A (zh
Inventor
张碧兰
游秀美
黄志恭
邱颂盛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN101211798A publication Critical patent/CN101211798A/zh
Application granted granted Critical
Publication of CN101211798B publication Critical patent/CN101211798B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/11831—Reworking, e.g. shaping involving a chemical process, e.g. etching the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明揭示一种焊料凸块结构以及在半导体元件上制作焊料凸块结构的方法。在一实施例中，首先提供半导体衬底，其上具有接合垫以及位于接合垫上的保护层，其具有露出部分接合垫的开口。在接合垫与保护层上形成第一凸块底层金属。在第一凸块底层金属上设置掩模层，其具有露出部分第一凸块底层金属的开口。蚀刻掩模层，以在第一凸块底层金属与掩模层之间的边缘形成凹陷。在掩模层的开口中形成第二凸块底层金属，使第二凸块底层金属填入凹陷与部分的掩模层开口。本发明能够减少焊料凸块结构的底切程度，因此凸块底层金属之间相对不易受损，由此提高了焊料凸块结构的可靠度。

Description

焊料凸块结构及其制作方法
技术领域
本发明涉及半导体元件的制作，且特别涉及一种在半导体元件上制作焊料凸块结构(solder bump structure)的方法。
背景技术
凸块底层金属(UBM，under bump metallization)已广泛用在半导体制造工艺上。半导体制造工艺通常包含在半导体晶圆上进行薄膜沉积、图案化、掺杂、热处理等步骤。当半导体元件制作完毕后，还包括将晶圆上的半导体集成电路芯片(IC chip)进行测试、封装及组装。芯片倒装(flip chip)封装是一种先进的半导体封装技术，其特色是将芯片倒置后，直接让芯片上的导电凸块(conductive bump)或接合垫(bonding pads)与外部元件(例如基板)连接，如此即可达成传导接触。
芯片倒装的接合垫通常包含最上层金属，例如铝，用于IC芯片的电性传导。接合垫上通常还包括焊料凸块，以电性连接接合垫与封装体的接脚，其中封装体例如是陶瓷基板、印刷电路板、承载基板(carrier)等。焊料凸块的材料通常是金属合金，例如铅-锡合金，且通常是在半导体晶圆尚未切割成独立的芯片之前形成的。
然而，焊料凸块通常不会直接设置在接合垫上，主要原因是因为最上层金属(例如铝)暴露在空气中会快速氧化，从而造成导电性能不良。再者，铝对大部分焊料的接合能力与润湿能力并非特别突出。为解决上述问题，可在焊料凸块与接合垫之间设置凸块底层金属结构，以形成低电阻的电性连接、并抵挡各种外来的应力。
凸块底层金属结构通常包括一层或数层例如钛与铜制成的金属层，沉积在IC芯片的接合垫上。然后，将焊料沉积在凸块底层金属结构上，回焊后形成球形的焊料凸块。然而，传统的焊料凸块结构因为凸块底层金属的底切现象，具有可靠度与性能不佳的缺点。
图1A-图1D显示上述凸块底层金属的底切现象。请先参照图1A，其显示制作中的传统焊料凸块结构，其中接合垫4设置在半导体衬底2上。接合垫4上具有图案化的保护层6，且保护层6露出部分的接合垫4。第一凸块底层金属8A(例如钛)形成在保护层6与露出的接合垫4上。第二凸块底层金属8B(例如铜)形成在第一凸块底层金属8A上。掩模层10(例如光致抗蚀剂)形成在第二凸块底层金属8B上，且掩模层10中具有开口12，开口12露出部分的第二凸块底层金属8B。
一般而言，掩模层10的开口12中会沉积额外的凸块底层金属。如图1B所示，沉积额外的铜层8B’与镍层8C填入部分的开口12。去除掩模层10后，如图1C所示，对凸块底层金属进行蚀刻，例如以湿法蚀刻方式对镍层8C、铜层8B’、第二凸块底层金属8B、第一凸块底层金属8A(例如钛)依序进行蚀刻。由于湿法蚀刻为各向同性(isotropic)的蚀刻，每一个方向的蚀刻速率相同，使得被蚀刻的材料形成底切(undercut)，造成不必要的线宽损失。蚀刻铜层8B’和第二凸块底层金属8B造成如图1D所示的底切14。由于铜层的厚度，需要将铜层暴露在蚀刻液中较长时间，因此形成了底切14，而蚀刻钛层8A时则形成底切16。铜底切14可达到每边6μm，而钛底切16可达到每边4μm，因此总共造成焊料凸块结构中每边10μm的底切。虽然底切是蚀刻步骤的必然结果，但底切会影响接线的长期可靠度，因为底切会减弱接合垫与焊料凸块之间的结合力，降低焊料凸块结构的整合度(integrity)，使得芯片提早失效。
由上述说明可知，业界亟需提出一种改良的焊料凸块结构来解决上述底切问题，以提高焊料凸块结构的可靠度与性能。
发明内容
鉴于上述问题，本发明提供一种在半导体元件上制作焊料凸块结构的方法。在一实施例中，首先提供半导体衬底，其上具有接合垫以及位于接合垫上的保护层，其具有开口露出部分的接合垫。在接合垫与保护层上形成第一凸块底层金属。在第一凸块底层金属上设置掩模层，其具有开口以露出部分的第一凸块底层金属。以溅击蚀刻、变压耦合式等离子体蚀刻或反应性离子蚀刻的方式蚀刻掩模层以在第一凸块底层金属与掩模层之间的边缘形成凹陷。形成第二凸块底层金属于掩模层的开口中，使第二凸块底层金属填入凹陷与部分的掩模层开口。
上述在半导体元件上制作焊料凸块结构的方法中，该第一凸块底层金属可包含钛。
上述在半导体元件上制作焊料凸块结构的方法中，该第一凸块底层金属可包含铜。
上述在半导体元件上制作焊料凸块结构的方法还可包括：形成聚亚酰胺层，该聚亚酰胺层邻接并接触该保护层、该接合垫、及该第一凸块底层金属。
上述在半导体元件上制作焊料凸块结构的方法中，该掩模层可为光致抗蚀剂层，且形成该掩模层的开口的步骤可包括：图案化并显影该光致抗蚀剂层。
上述在半导体元件上制作焊料凸块结构的方法中，该第二凸块底层金属可包含铜。
上述在半导体元件上制作焊料凸块结构的方法中，该第二凸块底层金属可包含镍。
上述在半导体元件上制作焊料凸块结构的方法还可包括：蚀刻该第二凸块底层金属，使得该第二凸块底层金属每一边的底切小于约3μm。
上述在半导体元件上制作焊料凸块结构的方法中还可包括：将焊料填入该掩模层的开口；去除该掩模层；以及将该焊料回焊以形成焊料凸块。
本发明还提供了一种焊料凸块结构，该焊料凸块结构是通过上述在半导体元件上制作焊料凸块结构的方法形成的。
本发明能够减少焊料凸块结构的底切程度，因此凸块底层金属之间相对不易受损，由此提高了焊料凸块结构的可靠度。
为让本发明的上述和其它目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合附图，作详细说明如下：
附图说明
图1A～图1D为一系列剖面图，用以说明现有技术制作焊料凸块结构的流程。
图2A～图2E为一系列剖面图，用以说明本发明一实施例制作焊料凸块结构的流程。
其中，附图标记说明如下：
2～半导体衬底   4～接合垫
6～保护层       8A-8F～凸块底层金属
10～掩模层      12～开口
14～底切        16～底切
18～凹陷        19～足部
20～焊料        22～底切
24～底切        8B’～铜层
具体实施方式
请参照图2A，其显示依照本发明实施例制作中的焊料凸块结构剖面图，其中接合垫4设置在半导体衬底2上。接合垫4上具有图案化的保护层6，且保护层6露出部分的接合垫4。接合垫或接触垫通常通过多层金属内连线与芯片形成电性连接。接合垫4可由传统的化学气相沉积法(CVD，chemicalvapor deposition)形成，材料例如是铜、铝、或其它导电金属。形成接合垫4之后，沉积一层作为保护与电性隔离用的保护层6覆盖在接合垫4表面上。保护层6可隔绝芯片表面并保护芯片免于湿气或污染物的伤害，以及免于在组装时受到机械力伤害。保护层6可用传统的CVD法沉积在衬底2与接合垫4上，然后经过图案化蚀刻出对应于接合垫4的开口。保护层6中的开口在后续工艺中用来让焊料凸块形成电性接触。保护层6的材料可包括氮化硅、氧化硅、氮氧化硅、和/或其它任何材料。在一实施例中，保护层6的厚度约为在另一实施例中可进一步沉积各种聚亚酰胺(polyimide)，以在保护层6上形成聚亚酰胺层(未示出)，对芯片作进一步的保护。聚亚酰胺层可邻接并接触保护层6、接合垫4、及第一凸块底层金属8A。
之后，通常以电镀法或气相沉积法，将一层或数层的凸块底层金属(厚度约
Figure GSB00000141175700042
)沉积在接合垫4与保护层6上。最上层的凸块底层金属可以增加对焊料的接合力与润湿性，而最下层的凸块底层金属可以增加对接合垫4的保护。在一实施例中，将包含钛的第一凸块底层金属8A沉积在接合垫4与保护层6上。第一凸块底层金属8A的厚度约为
Figure GSB00000141175700043
。之后，将包含铜的第二凸块底层金属8D沉积在第一凸块底层金属8A上。第二凸块底层金属8D的厚度约为
Figure GSB00000141175700051
。接着，将掩模层或光致抗蚀剂层10形成在凸块底层金属上。在一实施例中，光致抗蚀剂层10形成在第二凸块底层金属8D上。光致抗蚀剂层10的高度约为10-120μm。如图2A所示，光致抗蚀剂层10经过曝光图案化与显影从而形成开口12，露出接合垫4上部分的第二凸块底层金属8D。
依照本发明的特征之一，接下来对图案化的光致抗蚀剂层10进行选择性的蚀刻，以在第二凸块底层金属8D与光致抗蚀剂层10之间的边缘或角落处形成凹陷18，如图2B所示。整体而言，第二凸块底层金属8D并未被蚀刻剂严重蚀刻。由以下可知，凹陷18可使后续沉积在光致抗蚀剂开口中的凸块底层金属形成较厚的足部(footing)，以抵挡后续的蚀刻，避免造成底切。现有技术中有许多方法可形成凹陷18，例如溅击蚀刻(sputter etch)、变压耦合式等离子体蚀刻(TCP，transformer coupled plasma)、反应性离子蚀刻(reactive ion etch)、和/或其它在含有氯、氧、氩、和/或其它化学品环境下的蚀刻技术。在一实施例中，凹陷18是以每分钟大于的蚀刻速率蚀刻形成的。
请参照图2C，例如以电镀或气相沉积法，在光致抗蚀剂层10的开口12中形成额外的凸块底层金属。在本发明一实施例中，在开口12中形成第三凸块底层金属8E与第四凸块底层金属8F，其中第三凸块底层金属8E填入凹陷18而形成足部19。在一实施例中，第三凸块底层金属8E的材料可为铜，高度约为4-5μm，而足部19的宽度约为3-4μm。第四凸块底层金属8F的材料可为镍，高度约为2-3μm。之后，沉积柱状的焊料20，例如先沉积一层铅，再沉积一层锡，然后将之回焊(reflow)从而成为均质(homogeneous)的焊料。在另一实施例中，可利用第四凸块底层金属8F当作籽晶层(seed layer)，以电镀或气相沉积法形成均质的焊料。
去除光致抗蚀剂层10后，如图2D所示，对凸块底层金属8F、8E、8D、8A进行蚀刻以露出底下的保护层6，此工艺例如以湿法蚀刻或反应性离子蚀刻进行。在蚀刻过程中，焊料20可作为蚀刻掩模保护底下的凸块底层金属。与现有技术相比，第三凸块底层金属8E具有较厚的足部19，因此凸块底层金属8F、8E、8D、8A较能够阻挡蚀刻，从而避免形成严重的底切。在一实施例中，在蚀刻凸块底层金属8E、8D(铜)时形成底切22，而在蚀刻凸块底层金属8A(钛)时形成底切24。铜底切22的每一边约为3μm，钛底切24的每一边约为2μm，因此总共造成焊料凸块结构中每边约5μm的底切。由以上可知，虽然底切是蚀刻所造成的必然现象，但借助本发明的方法可减少焊料凸块结构的底切程度，因此凸块底层金属之间较不容易受损，由此提高了焊料凸块结构的可靠度。
蚀刻完凸块底层金属后，将焊料20短暂加热至熔点(回焊)，利用其表面张力的作用在凸块底层金属8F上形成大体呈球形的焊料凸块(未显示)。
应注意的是，上述形成焊料凸块结构的方法仅为举例说明，因此，本领域技术人员在不脱离本发明的精神和范围内也可使用其它各种方法形成前述的焊料凸块结构，例如可使用光致抗蚀剂以外的制造工艺。此外，虽然在前述实施例中凸块底层金属8F为镍，但本领域技术人员也可使用其它材料。另外，在不脱离本发明的精神和范围内，本领域技术人员也可调整保护层与聚亚酰胺层，甚至加以去除。
虽然本说明书已通过较佳实施例揭示了各种形成凸块底层金属的方法，然而以上说明并非用以限定本发明，任何所属技术领域中的普通技术人员，在不脱离本发明的精神和范围内，应可作任意的改动与修改，因此本发明的保护范围应以所附权利要求范围为准。

Claims (9)

1.一种在半导体元件上制作焊料凸块结构的方法，包括下列步骤：
提供半导体衬底，其上具有接合垫以及位于该接合垫上的保护层，该保护层具有露出部分该接合垫的开口；
在该接合垫与该保护层上形成第一凸块底层金属；
在该第一凸块底层金属上设置掩模层，该掩模层具有露出部分该第一凸块底层金属的开口；
以溅击蚀刻、变压耦合式等离子体蚀刻或反应性离子蚀刻的方式蚀刻该掩模层，以在该第一凸块底层金属与该掩模层之间的边缘形成凹陷；以及
在该掩模层的开口中形成第二凸块底层金属，该第二凸块底层金属填入该凹陷与部分的该掩模层的开口。
2.如权利要求1所述的在半导体元件上制作焊料凸块结构的方法，其中该第一凸块底层金属包含钛。
3.如权利要求1所述的在半导体元件上制作焊料凸块结构的方法，其中该第一凸块底层金属包含铜。
4.如权利要求1所述的在半导体元件上制作焊料凸块结构的方法，还包括：形成聚亚酰胺层，该聚亚酰胺层邻接并接触该保护层、该接合垫、及该第一凸块底层金属。
5.如权利要求1所述的在半导体元件上制作焊料凸块结构的方法，其中该掩模层为光致抗蚀剂层，且形成该掩模层的开口的步骤包括：图案化并显影该光致抗蚀剂层。
6.如权利要求1所述的在半导体元件上制作焊料凸块结构的方法，其中该第二凸块底层金属包含铜。
7.如权利要求1所述的在半导体元件上制作焊料凸块结构的方法，其中该第二凸块底层金属包含镍。
8.如权利要求1所述的在半导体元件上制作焊料凸块结构的方法，还包括：蚀刻该第二凸块底层金属，使得该第二凸块底层金属每一边的底切小于3μm。
9.如权利要求1所述的在半导体元件上制作焊料凸块结构的方法，还包括：
将焊料填入该掩模层的开口；
去除该掩模层；以及
将该焊料回焊以形成焊料凸块。
CN2007101120227A 2006-12-29 2007-06-21 焊料凸块结构及其制作方法 Active CN101211798B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/647,473 US7456090B2 (en) 2006-12-29 2006-12-29 Method to reduce UBM undercut
US11/647,473 2006-12-29

Publications (2)

Publication Number Publication Date
CN101211798A CN101211798A (zh) 2008-07-02
CN101211798B true CN101211798B (zh) 2010-12-08

Family

ID=39582742

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007101120227A Active CN101211798B (zh) 2006-12-29 2007-06-21 焊料凸块结构及其制作方法

Country Status (2)

Country Link
US (1) US7456090B2 (zh)
CN (1) CN101211798B (zh)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5162851B2 (ja) * 2006-07-14 2013-03-13 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP4724192B2 (ja) * 2008-02-28 2011-07-13 株式会社東芝 電子部品の製造方法
US9543262B1 (en) * 2009-08-18 2017-01-10 Cypress Semiconductor Corporation Self aligned bump passivation
US8759209B2 (en) * 2010-03-25 2014-06-24 Stats Chippac, Ltd. Semiconductor device and method of forming a dual UBM structure for lead free bump connections
US9598772B2 (en) 2010-04-16 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating bump structure without UBM undercut
US8993431B2 (en) 2010-05-12 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating bump structure
JP2011249564A (ja) * 2010-05-27 2011-12-08 Renesas Electronics Corp 半導体装置の製造方法及び実装構造
US8258055B2 (en) * 2010-07-08 2012-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor die
US8872341B2 (en) 2010-09-29 2014-10-28 Infineon Technologies Ag Semiconductor structure having metal oxide or nirtride passivation layer on fill layer and method for making same
US9064875B2 (en) 2010-09-29 2015-06-23 Infineon Technologies Ag Semiconductor structure and method for making same
US8298930B2 (en) 2010-12-03 2012-10-30 International Business Machines Corporation Undercut-repair of barrier layer metallurgy for solder bumps and methods thereof
US8729699B2 (en) 2011-10-18 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Connector structures of integrated circuits
TWI449141B (zh) * 2011-10-19 2014-08-11 Richtek Technology Corp 晶圓級晶片尺度封裝元件以及其製造方法
US9111817B2 (en) * 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
CN103311131B (zh) * 2013-05-15 2016-03-16 华进半导体封装先导技术研发中心有限公司 一种微凸点制造过程中防止微凸点侧向钻蚀的方法
US9214436B2 (en) * 2014-02-04 2015-12-15 Globalfoundries Inc. Etching of under bump mettallization layer and resulting device
US9773736B2 (en) * 2015-01-28 2017-09-26 Infineon Technologies Ag Intermediate layer for copper structuring and methods of formation thereof
KR102410018B1 (ko) 2015-09-18 2022-06-16 삼성전자주식회사 반도체 패키지
KR102578794B1 (ko) * 2016-06-14 2023-09-18 삼성전자주식회사 반도체 장치 및 그 제조 방법
US20190295979A1 (en) * 2018-03-23 2019-09-26 Nanya Technology Corporation Solder bump, flip chip structure and method for preparing the same
US10734348B2 (en) * 2018-09-21 2020-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded semiconductor devices and methods of forming the same
TWI678743B (zh) * 2018-12-10 2019-12-01 南茂科技股份有限公司 半導體線路結構及其製作方法
KR20210126188A (ko) 2020-04-09 2021-10-20 삼성전자주식회사 반도체 소자

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6293457B1 (en) * 2000-06-08 2001-09-25 International Business Machines Corporation Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization
CN1630038A (zh) * 2003-12-18 2005-06-22 悠立半导体股份有限公司 蚀刻液及应用该蚀刻液选择性去除阻障层的导电凸块制造方法
CN1886828A (zh) * 2003-11-29 2006-12-27 英飞凌科技股份公司 电镀方法和接触凸起装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6372545B1 (en) * 2001-03-22 2002-04-16 Taiwan Semiconductor Manufacturing Company Method for under bump metal patterning of bumping process
TW521361B (en) * 2002-02-27 2003-02-21 Advanced Semiconductor Eng Bump process
TW577158B (en) * 2002-11-29 2004-02-21 Advanced Semiconductor Eng Method for forming UBM pads and bumps on wafer
TW591782B (en) * 2003-06-19 2004-06-11 Advanced Semiconductor Eng Formation method for conductive bump
TWI298204B (en) * 2005-11-21 2008-06-21 Advanced Semiconductor Eng Structure of bumps forming on an under metallurgy layer and method for making the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6293457B1 (en) * 2000-06-08 2001-09-25 International Business Machines Corporation Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization
CN1886828A (zh) * 2003-11-29 2006-12-27 英飞凌科技股份公司 电镀方法和接触凸起装置
CN1630038A (zh) * 2003-12-18 2005-06-22 悠立半导体股份有限公司 蚀刻液及应用该蚀刻液选择性去除阻障层的导电凸块制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP昭63-308352A 1988.12.15

Also Published As

Publication number Publication date
US7456090B2 (en) 2008-11-25
US20080157362A1 (en) 2008-07-03
CN101211798A (zh) 2008-07-02

Similar Documents

Publication Publication Date Title
CN101211798B (zh) 焊料凸块结构及其制作方法
US8497584B2 (en) Method to improve bump reliability for flip chip device
US6790759B1 (en) Semiconductor device with strain relieving bump design
TWI225899B (en) Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer
US5736456A (en) Method of forming conductive bumps on die for flip chip applications
KR100884238B1 (ko) 앵커형 결합 구조를 갖는 반도체 패키지 및 그 제조 방법
US5698465A (en) Process for manufacturing an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
US9165898B2 (en) Method of manufacturing semiconductor device with through hole
US6521970B1 (en) Chip scale package with compliant leads
EP1239514A2 (en) Low fabrication cost, fine pitch and high reliability solder bump
JP5064632B2 (ja) 相互接続構造を形成するための方法及び装置
JP2003203940A (ja) 半導体チップ及び配線基板並びにこれらの製造方法、半導体ウエハ、半導体装置、回路基板並びに電子機器
US7309924B2 (en) UBM for fine pitch solder ball and flip-chip packaging method using the same
KR20050039230A (ko) 초박형 플립칩 패키지의 제조방법
TWI273639B (en) Etchant and method for forming bumps
TW200910557A (en) Under bump metallization structure having a seed layer for electroless nickel deposition
US6429046B1 (en) Flip chip device and method of manufacture
WO1990015438A1 (en) Beam lead and semiconductor device structure and method for fabricating integrated structure
KR20040022178A (ko) 땜납 정지 구조물화하는 방법
WO2021103489A1 (zh) 半导体结构及其制造方法
KR100336769B1 (ko) 웨이퍼 레벨의 칩 사이즈 패키지 및 그 제조방법
US7541273B2 (en) Method for forming bumps
TWM589366U (zh) 具有增強互連的晶片封裝組件
JP2021501459A (ja) 半導体パッケージングのための構造及び方法
JPH11186309A (ja) 半導体装置および半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant