CN101176195B - 用于混合取向衬底的改进非晶化/模板化再结晶方法 - Google Patents

用于混合取向衬底的改进非晶化/模板化再结晶方法 Download PDF

Info

Publication number
CN101176195B
CN101176195B CN2006800167944A CN200680016794A CN101176195B CN 101176195 B CN101176195 B CN 101176195B CN 2006800167944 A CN2006800167944 A CN 2006800167944A CN 200680016794 A CN200680016794 A CN 200680016794A CN 101176195 B CN101176195 B CN 101176195B
Authority
CN
China
Prior art keywords
orientation
layer
semiconductor
temperature
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2006800167944A
Other languages
English (en)
Chinese (zh)
Other versions
CN101176195A (zh
Inventor
凯斯·E.·弗格尔
凯瑟琳·L.·萨恩格尔
宋均镛
尹海洲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN101176195A publication Critical patent/CN101176195A/zh
Application granted granted Critical
Publication of CN101176195B publication Critical patent/CN101176195B/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H10P14/3808Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167Manufacturing their channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901Materials
    • H10P14/2902Materials being Group IVA materials
    • H10P14/2905Silicon, silicon germanium or germanium
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2926Crystal orientations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3402Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411Silicon, silicon germanium or germanium
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3466Crystal orientation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/011Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/17Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
CN2006800167944A 2005-06-01 2006-05-18 用于混合取向衬底的改进非晶化/模板化再结晶方法 Expired - Fee Related CN101176195B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/142,646 2005-06-01
US11/142,646 US7291539B2 (en) 2005-06-01 2005-06-01 Amorphization/templated recrystallization method for hybrid orientation substrates
PCT/US2006/019417 WO2006130360A2 (en) 2005-06-01 2006-05-18 Improved amorphization/templated recrystallization method for hybrid orientation substrates

Publications (2)

Publication Number Publication Date
CN101176195A CN101176195A (zh) 2008-05-07
CN101176195B true CN101176195B (zh) 2010-06-02

Family

ID=37482138

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2006800167944A Expired - Fee Related CN101176195B (zh) 2005-06-01 2006-05-18 用于混合取向衬底的改进非晶化/模板化再结晶方法

Country Status (6)

Country Link
US (5) US7291539B2 (https=)
EP (1) EP1886342A4 (https=)
JP (1) JP4959690B2 (https=)
CN (1) CN101176195B (https=)
TW (1) TW200710997A (https=)
WO (1) WO2006130360A2 (https=)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7057256B2 (en) 2001-05-25 2006-06-06 President & Fellows Of Harvard College Silicon-based visible and near-infrared optoelectric devices
US7442629B2 (en) 2004-09-24 2008-10-28 President & Fellows Of Harvard College Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate
US7291539B2 (en) * 2005-06-01 2007-11-06 International Business Machines Corporation Amorphization/templated recrystallization method for hybrid orientation substrates
US7396407B2 (en) * 2006-04-18 2008-07-08 International Business Machines Corporation Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates
KR100782497B1 (ko) * 2006-11-20 2007-12-05 삼성전자주식회사 얇은 응력이완 버퍼패턴을 갖는 반도체소자의 제조방법 및관련된 소자
US9034102B2 (en) * 2007-03-29 2015-05-19 United Microelectronics Corp. Method of fabricating hybrid orientation substrate and structure of the same
US20080248626A1 (en) * 2007-04-05 2008-10-09 International Business Machines Corporation Shallow trench isolation self-aligned to templated recrystallization boundary
US7846803B2 (en) * 2007-05-31 2010-12-07 Freescale Semiconductor, Inc. Multiple millisecond anneals for semiconductor device fabrication
US7642197B2 (en) * 2007-07-09 2010-01-05 Texas Instruments Incorporated Method to improve performance of secondary active components in an esige CMOS technology
FR2918792B1 (fr) * 2007-07-10 2010-04-23 Soitec Silicon On Insulator Procede de traitement de defauts d'interface dans un substrat.
US20090057816A1 (en) * 2007-08-29 2009-03-05 Angelo Pinto Method to reduce residual sti corner defects generated during spe in the fabrication of nano-scale cmos transistors using dsb substrate and hot technology
JP2009111074A (ja) * 2007-10-29 2009-05-21 Toshiba Corp 半導体基板
US8043947B2 (en) * 2007-11-16 2011-10-25 Texas Instruments Incorporated Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a DSB substrate
EP2065921A1 (en) * 2007-11-29 2009-06-03 S.O.I.T.E.C. Silicon on Insulator Technologies Method for fabricating a semiconductor substrate with areas with different crystal orienation
ATE521986T1 (de) * 2008-01-28 2011-09-15 Nxp Bv Verfahren zur herstellung eines gruppe-iv- halbleitersubstrats mit zweifacher ausrichtung
US8211786B2 (en) 2008-02-28 2012-07-03 International Business Machines Corporation CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication
US7541629B1 (en) 2008-04-21 2009-06-02 International Business Machines Corporation Embedded insulating band for controlling short-channel effect and leakage reduction for DSB process
US7943479B2 (en) * 2008-08-19 2011-05-17 Texas Instruments Incorporated Integration of high-k metal gate stack into direct silicon bonding (DSB) hybrid orientation technology (HOT) pMOS process flow
US20100200896A1 (en) * 2009-02-09 2010-08-12 International Business Machines Corporation Embedded stress elements on surface thin direct silicon bond substrates
US7897447B2 (en) * 2009-02-24 2011-03-01 Texas Instruments Incorporated Use of in-situ HCL etch to eliminate by oxidation recrystallization border defects generated during solid phase epitaxy (SPE) in the fabrication of nano-scale CMOS transistors using direct silicon bond substrate (DSB) and hybrid orientation technology (HOT)
FR2942674B1 (fr) * 2009-02-27 2011-12-16 Commissariat Energie Atomique Procede d'elaboration d'un substrat hybride par recristallisation partielle d'une couche mixte
US8193616B2 (en) * 2009-06-29 2012-06-05 Kabushiki Kaisha Toshiba Semiconductor device on direct silicon bonded substrate with different layer thickness
CN102473642B (zh) * 2009-07-08 2014-11-12 株式会社东芝 半导体装置及其制造方法
US9911781B2 (en) 2009-09-17 2018-03-06 Sionyx, Llc Photosensitive imaging devices and associated methods
US9673243B2 (en) 2009-09-17 2017-06-06 Sionyx, Llc Photosensitive imaging devices and associated methods
US8741394B2 (en) 2010-03-25 2014-06-03 Novellus Systems, Inc. In-situ deposition of film stacks
US9028924B2 (en) 2010-03-25 2015-05-12 Novellus Systems, Inc. In-situ deposition of film stacks
US8692198B2 (en) 2010-04-21 2014-04-08 Sionyx, Inc. Photosensitive imaging devices and associated methods
WO2011160130A2 (en) 2010-06-18 2011-12-22 Sionyx, Inc High speed photosensitive devices and associated methods
CN102569394B (zh) * 2010-12-29 2014-12-03 中芯国际集成电路制造(北京)有限公司 晶体管及其制作方法
JPWO2012111616A1 (ja) * 2011-02-15 2014-07-07 住友電気工業株式会社 保護膜付複合基板、および半導体デバイスの製造方法
US9496308B2 (en) 2011-06-09 2016-11-15 Sionyx, Llc Process module for increasing the response of backside illuminated photosensitive imagers and associated methods
WO2013010127A2 (en) 2011-07-13 2013-01-17 Sionyx, Inc. Biometric imaging devices and associated methods
WO2013120093A1 (en) * 2012-02-10 2013-08-15 Sionyx, Inc. Low damage laser-textured devices and associated methods
WO2013123004A1 (en) * 2012-02-13 2013-08-22 Applied Materials, Inc. Selective epitaxial germanium growth on silicon-trench fill and in situ doping
US9064764B2 (en) 2012-03-22 2015-06-23 Sionyx, Inc. Pixel isolation elements, devices, and associated methods
US9165788B2 (en) * 2012-04-06 2015-10-20 Novellus Systems, Inc. Post-deposition soft annealing
US9117668B2 (en) 2012-05-23 2015-08-25 Novellus Systems, Inc. PECVD deposition of smooth silicon films
US9388491B2 (en) 2012-07-23 2016-07-12 Novellus Systems, Inc. Method for deposition of conformal films with catalysis assisted low temperature CVD
KR20150130303A (ko) 2013-02-15 2015-11-23 사이오닉스, 아이엔씨. 안티 블루밍 특성 및 관련 방법을 가지는 높은 동적 범위의 cmos 이미지 센서
US9939251B2 (en) 2013-03-15 2018-04-10 Sionyx, Llc Three dimensional imaging utilizing stacked imager devices and associated methods
US8895415B1 (en) 2013-05-31 2014-11-25 Novellus Systems, Inc. Tensile stressed doped amorphous silicon
US9209345B2 (en) 2013-06-29 2015-12-08 Sionyx, Inc. Shallow trench textured regions and associated methods
US9490161B2 (en) * 2014-04-29 2016-11-08 International Business Machines Corporation Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same
US9666493B2 (en) 2015-06-24 2017-05-30 International Business Machines Corporation Semiconductor device structure with 110-PFET and 111-NFET curent flow direction
RU2641508C2 (ru) * 2016-07-01 2018-01-17 федеральное государственное автономное образовательное учреждение высшего образования "Санкт-Петербургский национальный исследовательский университет информационных технологий, механики и оптики" (Университет ИТМО) Способ изготовления устройства микротехники в объеме пластины фоточувствительного стекла
JP6547702B2 (ja) * 2016-07-26 2019-07-24 信越半導体株式会社 半導体装置の製造方法及び半導体装置の評価方法
US10147609B2 (en) * 2016-12-15 2018-12-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor epitaxy bordering isolation structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1319252A (zh) * 1998-09-25 2001-10-24 旭化成株式会社 半导体衬底及其制造方法、和使用它的半导体器件及其制造方法
US6825102B1 (en) * 2003-09-18 2004-11-30 International Business Machines Corporation Method of improving the quality of defective semiconductor material

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4385937A (en) * 1980-05-20 1983-05-31 Tokyo Shibaura Denki Kabushiki Kaisha Regrowing selectively formed ion amorphosized regions by thermal gradient
JPS60154548A (ja) 1984-01-24 1985-08-14 Fujitsu Ltd 半導体装置の製造方法
US4768076A (en) * 1984-09-14 1988-08-30 Hitachi, Ltd. Recrystallized CMOS with different crystal planes
US4816893A (en) * 1987-02-24 1989-03-28 Hughes Aircraft Company Low leakage CMOS/insulator substrate devices and method of forming the same
JPS63311718A (ja) * 1987-06-15 1988-12-20 Hitachi Ltd ヘテロ構造単結晶半導体薄膜の製造方法
JPH01162376A (ja) 1987-12-18 1989-06-26 Fujitsu Ltd 半導体装置の製造方法
JPH01162362A (ja) 1987-12-18 1989-06-26 Fujitsu Ltd 半導体装置の製造方法
JPH02170577A (ja) * 1988-12-23 1990-07-02 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH04188612A (ja) * 1990-11-19 1992-07-07 Canon Inc 結晶成長方法及び該方法によって得られた結晶物品
JP3017860B2 (ja) 1991-10-01 2000-03-13 株式会社東芝 半導体基体およびその製造方法とその半導体基体を用いた半導体装置
US5888872A (en) * 1997-06-20 1999-03-30 Advanced Micro Devices, Inc. Method for forming source drain junction areas self-aligned between a sidewall spacer and an etched lateral sidewall
JP4521542B2 (ja) 1999-03-30 2010-08-11 ルネサスエレクトロニクス株式会社 半導体装置および半導体基板
US6214653B1 (en) * 1999-06-04 2001-04-10 International Business Machines Corporation Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate
US6404038B1 (en) * 2000-03-02 2002-06-11 The United States Of America As Represented By The Secretary Of The Navy Complementary vertical bipolar junction transistors fabricated of silicon-on-sapphire utilizing wide base PNP transistors
JP2003092399A (ja) * 2001-09-18 2003-03-28 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP3782021B2 (ja) * 2002-02-22 2006-06-07 株式会社東芝 半導体装置、半導体装置の製造方法、半導体基板の製造方法
US6902962B2 (en) * 2003-04-04 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon-on-insulator chip with multiple crystal orientations
US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US20050116290A1 (en) * 2003-12-02 2005-06-02 De Souza Joel P. Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers
US7285473B2 (en) * 2005-01-07 2007-10-23 International Business Machines Corporation Method for fabricating low-defect-density changed orientation Si
US7060585B1 (en) 2005-02-16 2006-06-13 International Business Machines Corporation Hybrid orientation substrates by in-place bonding and amorphization/templated recrystallization
US7291539B2 (en) * 2005-06-01 2007-11-06 International Business Machines Corporation Amorphization/templated recrystallization method for hybrid orientation substrates

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1319252A (zh) * 1998-09-25 2001-10-24 旭化成株式会社 半导体衬底及其制造方法、和使用它的半导体器件及其制造方法
US6825102B1 (en) * 2003-09-18 2004-11-30 International Business Machines Corporation Method of improving the quality of defective semiconductor material

Also Published As

Publication number Publication date
CN101176195A (zh) 2008-05-07
JP2008543081A (ja) 2008-11-27
US20080286917A1 (en) 2008-11-20
US20100203708A1 (en) 2010-08-12
US7291539B2 (en) 2007-11-06
JP4959690B2 (ja) 2012-06-27
US20060276011A1 (en) 2006-12-07
US7704852B2 (en) 2010-04-27
WO2006130360A2 (en) 2006-12-07
US20080108204A1 (en) 2008-05-08
US7547616B2 (en) 2009-06-16
US20060275971A1 (en) 2006-12-07
TW200710997A (en) 2007-03-16
US7691733B2 (en) 2010-04-06
EP1886342A4 (en) 2011-06-15
US7960263B2 (en) 2011-06-14
WO2006130360A3 (en) 2007-06-14
EP1886342A2 (en) 2008-02-13

Similar Documents

Publication Publication Date Title
CN101176195B (zh) 用于混合取向衬底的改进非晶化/模板化再结晶方法
KR100961800B1 (ko) 적층형 템플레이트 층의 국부적 무결정 및 재결정으로형성된 선택적 반도체 결정 배향을 갖는 평면 기판
US7060585B1 (en) Hybrid orientation substrates by in-place bonding and amorphization/templated recrystallization
US7393730B2 (en) Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same
CN100370601C (zh) 一种形成集成半导体结构的方法
US7999319B2 (en) Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates
JP2006005245A (ja) 半導体基板の製造方法、及び半導体基板
WO2009084311A1 (ja) 半導体装置、単結晶半導体薄膜付き基板及びそれらの製造方法
US7863712B2 (en) Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same
WO2009084312A1 (ja) 半導体装置、単結晶半導体薄膜付き基板及びそれらの製造方法
KR20090107492A (ko) 반도체 구조체 및 그 제조 방법 및 컴퓨터 판독가능한 기록 매체
KR100703033B1 (ko) 반도체 장치 및 그 제조 방법
US9034102B2 (en) Method of fabricating hybrid orientation substrate and structure of the same
KR20240116473A (ko) 공유 재결정화 및 도펀트 활성화 단계들을 구비하는 3차원 회로 생성 방법
EP2065921A1 (en) Method for fabricating a semiconductor substrate with areas with different crystal orienation

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100602

Termination date: 20110518