CN101171681A - 活性碳的选择性外延工艺 - Google Patents

活性碳的选择性外延工艺 Download PDF

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CN101171681A
CN101171681A CNA2006800149880A CN200680014988A CN101171681A CN 101171681 A CN101171681 A CN 101171681A CN A2006800149880 A CNA2006800149880 A CN A2006800149880A CN 200680014988 A CN200680014988 A CN 200680014988A CN 101171681 A CN101171681 A CN 101171681A
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drain region
groove
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P·R·丘德博莱姆
S·切克莱奥塞
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Texas Instruments Inc
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Abstract

半导体器件包括成形在碳衬底(104)上的栅极(114)、通过掺杂邻近所述栅极的有源区(111)的第一部分和第二部分而形成的源极区(140)和漏极区(140)、以及形成在部分源极区(140)中的第一凹槽(162)和在部分漏极区(140)中的第二凹槽(160)。源极区和漏极区(140)中的掺杂剂通过加热有源区被激活，并且在激活所述源极区和所述漏极区(140)中的掺杂剂之后将半导体材料(165)沉积到所述第一凹槽(162)和所述第二凹槽(160)中。

Description

活性碳的选择性外延工艺
技术领域
【0001】本发明总体涉及半导体器件，并且更具体地涉及晶体管及其相关的制造方法，其具有因沟道应变的改善的迁移率。
发明背景
【0002】常规的金属氧化物半导体(MOS)晶体管一般包括半导体衬底比如硅，其具有源极、漏极以及位于源极和漏极之间的沟道。包含导电材料(栅导体)、氧化物层(栅氧化物)和侧壁隔离层的栅叠层(gate stack)一般位于沟道之上。栅氧化物一般直接位于沟道之上，而栅导体，通常包含多晶体的硅(多晶硅)材料，位于栅氧化物上。侧壁隔离层保护栅导体的侧壁。
【0003】通常而言，对于穿过MOS晶体管的沟道的特定电场，流经沟道的电流量与沟道中的载流子的迁移率成正比。因此，沟道中的载流子的迁移率越高，则电流可以流过更多并且电路可以工作得更快。一种提高MOS晶体管的沟道中的载流子的迁移率的方式是在沟道中产生一种机械应力。
【0004】压应变的沟道对于常规器件显著增强了空穴迁移率。拉应变的沟道比如在松散(relaxed)硅锗上生长的薄硅层实现了电子迁移率的显著增强。在硅沟道中引入拉应变的最普通方法是在松散硅锗(SiGe)层或衬底上外延生长硅沟道层。形成松散SiGe层的能力对于获得处于双轴拉应变下的上覆的、外延生长的硅层而言是重要的。然而，松散SiGe层的获得可能是昂贵的并且很难实现。
【0005】因此，需要克服现有技术的这些和其它问题并提供具有提高的沟道迁移率的晶体管。
发明内容
【0006】根据本发明，提供了一种形成半导体器件的方法，所述方法包括在衬底上形成栅极；通过掺杂邻近所述栅极的有源区的第一部分和第二部分，形成源极区和漏极区；以及形成在部分所述源极区中的第一凹槽和在部分所述漏极区中的第二凹槽。该方法还包括通过加热所述有源区来激活所述源极区和所述漏极区中的掺杂剂以及在激活所述源极区和所述漏极区中的掺杂剂之后将半导体材料沉积到所述第一凹槽和所述第二凹槽中。
【0007】根据另一实施方式，提供了一种形成半导体器件的方法，所述方法包括在衬底上形成栅极；在邻近所述栅极结构的有源区中形成轻掺杂的源极区和轻掺杂的漏极区；以及掺杂所述有源区以形成源极区和漏极区，其中轻掺杂的源极区和轻掺杂的漏极区的深度小于源极区和漏极区的深度。该方法还包括形成所述源极区中的第一凹槽和所述漏极区中的第二凹槽一源极区和漏极区中的凹槽；加热源极区和漏极区以便形成被激活的源极区和漏极区；以及用半导体材料填充被激活的源极区和漏极区中的第一和第二凹槽。
【0008】根据又一实施方式，提供了一种形成半导体器件的方法，所述方法包括在衬底中形成栅极结构；在邻近所述栅极结构的有源区中形成第一掺杂区和第二掺杂区；以及在有源区中形成第三掺杂区和第四掺杂区以便分别形成源极区和漏极区，其中第一掺杂区和第二掺杂区的深度分别小于第三掺杂区和第四掺杂区的深度。该方法还包括在部分源极区和部分漏极区中形成凹槽；加热有源区以形成被激活的源极和被激活的漏极；以及用半导体材料填充被激活的源极区和漏极区中的凹槽。
【0009】根据另一实施方式，提供了一种形成半导体器件的方法，所述方法包括在衬底上形成栅极；形成邻近所述栅极的源极区和漏极区；以及在源极区和漏极区中形成凹槽。该方法还包括加热源极区和漏极区以形成被激活的源极和被激活的漏极；以及用包括掺杂剂的半导体材料填充被激活的源极区和被激活的漏极区中的凹槽。
【0010】根据另一实施方式，提供了一种半导体器件，其包括衬底上的栅极结构；邻近所述栅极结构的源极区和漏极区。该半导体器件还包括半导体材料和硅化物，所述半导体材料包含在所述源极区和漏极区中形成的至少1％活性碳，所述硅化物接触所述源极区和漏极区的一部分。
附图说明
【0011】图1A-1K是根据本发明的各个实施方式说明了形成NMOS和PMOS晶体管的各个步骤的不连续的横截面图；
【0012】图2A-2B是各种材料经受不同退火温度的说明性的X射线衍射图。
具体实施方式
【0013】图1A-1N说明了根据本发明的原理所形成的示例性晶体管器件。在图1A中，提供了一晶体管器件102，其中半导体主体104比如衬底具有许多成形于其中的阱，例如分别限定NMOS晶体管器件区的P阱106和限定PMOS晶体管器件区的N阱108。此外，隔离区110比如场氧化物(FOX)区和STI区可以成形于该半导体主体中以限定有源区111。在图1B中，说明了晶体管器件102，其中栅电介质112例如通过热生长SiO2形成于有源区111上。然而，根据各个实施方式可以形成和考虑其它种类的栅电介质(例如高k电介质)。
【0014】参照图1C和图1D，导电的栅电极材料比如多晶硅可以通过蚀刻工艺115进行沉积并图案化，从而形成覆盖在栅氧化物112上的栅电极114。然后，偏移隔离层116可以成形于栅电极的侧面边缘114a上，如图1D所示，其中该偏移隔离层可以具有大约10-50纳米的宽度116a。
【0015】然后，如图1E所示，PMOS区可以用诸如光刻胶的掩模材料126进行遮蔽，并且可以执行延伸区注入128从而在NMOS区形成n型延伸区130。根据各个实施方式，热处理比如快速热退火接着可以被执行以激活掺杂剂，其中延伸区130的横向扩散到偏移隔离层116之下得以实现。用于激活掺杂剂的示例性温度是从大约650度到大约1050度。在特定实施方式中，该温度可以是大约950度；而在另一些实施方式中，此温度可以是大约1050度。在这些温度下，存在非晶层的再生长。
【0016】然后，p型延伸区掩模126可以被去除，而n型延伸区掩模132可以被沉积并图案化以覆盖NMOS区，如图1F所示。然后，可以执行p型延伸区注入工艺134从而在PMOS区形成P型延伸区136，如图所示。
【0017】掩模132接着可以被去除，并且伪(dummy)侧壁隔离层138可以邻近栅结构的侧面边缘上的偏移隔离层116被形成。例如，绝缘侧壁材料可以用通常共形或一致的方式沉积到器件上，并且随后经各向异性蚀刻以去除栅顶部上和有源区上的绝缘材料，留下NMOS区和PMOS区中的伪侧壁隔离层138，如图1G所示。用于伪侧壁隔离层138的示例性材料包括各种氧化物和氮化物，例如氧化硅、氮化硅和氮氧化硅。然而，也可以使用其它可接受的材料。
【0018】然后，源极区140和漏极区142分别成形于NMOS区和PMOS区，如图1H所示。如上结合延伸区注入所讨论的，源极/漏极注入可以用n源极/漏极掩模(未示出)和p源极/漏极掩模(未示出)来执行，以便分别单独地用n型和p型掺杂剂来注入NMOS区和PMOS区。如图1H所看到的，源极区140和漏极区142相对于伪侧壁隔离层被自对准，因而分别与延伸区130和延伸区136横向隔开。
【0019】然后，热处理比如快速热退火可以用来激活源极区140和漏极区142。而且，在各个实施方式中，单一热处理可以用来激活源极区140和漏极区142以及延伸区130和延伸区136。热处理使得延伸区130和延伸区136朝沟道横向扩散略微扩散到偏移隔离层之下。用于激活源极区和漏极区的示例性温度是从大约650度到大约1050度。在特定实施方式中，该温度可以是大约950度；而在另一些实施方式中，此温度可以是大约1050度。
【0020】如图1I所示，伪侧壁隔离层138可以凭借已知的蚀刻技术被去除。接着，凹槽160可以成形于在栅结构和隔离区之间的区域中，如图1J所示。凹槽成形的区域可以包括硅主体的有源区，其中延伸区130和延伸区136以及源极区140和漏极区142被形成。凹槽160可以利用例如干法蚀刻技术来形成，所述干法蚀刻技术比如在形成隔离区时蚀刻半导体主体中的STI沟槽所用的化学反应。根据各个实施方式，凹槽可以延伸到半导体主体中的深度162达大约10纳米到大约90纳米，并更特别地，深度为大约30纳米到大约70纳米。根据各个实施方式，凹槽160的深度小于源极区140和漏极区142的深度。在某些实施方式中，栅结构在凹槽成形过程中不被掩盖/掩模。如此，当栅电极包含多晶硅时，凹槽成形过程也可能导致成形于电极材料的顶部部分上的凹槽(未显示)。
【0021】根据各个实施方式，凹槽160可以延伸跨越源极区和漏极区的各个部分以及穿过延伸区130和延伸区136的各个部分。例如，凹槽160可以延伸跨越整个源极区和漏极区和/或整个延伸区130和延伸区136。替代地，凹槽160可以延伸跨越源极区和漏极区的一部分和/或延伸区130和延伸区136的一部分。
【0022】如图1K所示，凹槽160然后可以填充半导体材料165。根据各个实施方式，半导体材料165可以包括硅和碳(Si:C)、锗硅或者具有与周围材料的晶格间距不同的晶格间距的半导体。例如，应变的Si:C层可以成形于凹槽160中。硅可以通过各种技术选择性地沉积在凹槽160中，并且碳可以通过掩模和离子注入或高剂量气体团簇离子束沉积而引入到沉积在凹槽160中的硅内。由于硅是被选择性地沉积，所以在诸如场氧化物的不需要的区域上没有硅。
【0023】尽管不想受限于任何一种理论，但是人们相信凹槽内诸如Si:C或锗硅的半导体材料165形成的合金具有与硅体晶格相同结构的晶格，不过半导体材料165具有更大的间距。因此，人们相信凹槽内的半导体材料165在半导体沟道内在沟道下产生压应力。
【0024】根据各个实施方式，半导体材料165可以在源极和漏极的掺杂剂被激活后沉积到凹槽160中。因而，半导体材料165不会经受高温退火。虽然不想受限于任何一种理论，但是人们相信在Si:C填充凹槽160的情况下，高温退火将会影响Si:C晶格参数。例如，在所成形的Si:C中，相对较大百分比的碳在硅中的替代位置(substitutional site)占位。然而，由于碳在硅中的低溶解度，将碳保留在活性位中是很难的。
【0025】例如，碳在硅中一般未活化超过大约0.2％。此外，用传统流程的非晶化和再生长将硅中的碳激活/活化至最多大约0.7％。然而，当所成形的Si:C经过比如低于大约700度的低温退火时，碳可以被激活至≥1％。因此，人们相信将所成形的Si:C经受高温退火或高热预算(例如激活源极和漏极所用的)会造成碳在硅中从替代位置向间隙位置移动。高温退火释放了应变并且所沉积或沉积态的系统中的附加迁移率被显著地减少。
【0026】晶格参数分析已经用来确定半导体材料中的掺杂浓度。该分析的结果可以参见图2A和图2B。图2A和图2B示出了硅和Si:C经过不同退火温度的X射线衍射图。图2A所示的Si:C被形成并随后经受1050度温度，该温度类似于源极/漏极激活温度。如图2A所示，测量了不同注入方案和不同退火条件下Si:C中碳的激活。如在图2A中的曲线(a)和(b)可见的，最大碳激活只有0.7％。此外，如2A中的曲线(c)所示，对于更高退火温度，碳激活少于0.7％。
【0027】相比而言，图2B的Si:C被形成并随后经受700度温度，该温度表示器件在源极/漏极激活后要经受的温度。如图2B的曲线(a)所示，图2B的Si:C中的碳被激活至1.1％。
【0028】如图1L所示，在凹槽中填充半导体材料165之后，侧壁隔离层170可以被形成。侧壁隔离层170包括绝缘材料，例如氧化物、氮化物或这些层的组合。通过将一层此类隔离层材料以通常共形的方式沉积到器件上，接着各向异性蚀刻，因此从栅电极114的顶部和有源区111去除此类隔离层材料并留下栅电极的侧面边缘上的区域(该区域覆盖在偏移隔离层116上)，从而形成所述侧壁隔离层。侧壁隔离层170可以大体上比偏移隔离层116更厚，并且可以形成在部分半导体材料165上。
【0029】根据各个实施方式，例如图1M所示，硅化物180可以接着被形成。例如，金属层可以例如通过溅射继之以热处理进行沉积。在热处理过程中，金属接触硅的那些区域反应以形成金属硅化物。更具体地，硅化物可以形成在源极/漏极区上和栅的顶部上。然后，未反应的金属被剥离，并且后端处理比如层间绝缘和金属化层被形成以结束器件成形。
【0030】本文所述的方法形成了靠近晶体管器件的沟道区的半导体材料，其离栅电极114的侧面边缘的偏移量只有大约5纳米到大约20纳米。通过将半导体材料165更接近沟道设置，半导体材料165将所期望的应力更有效地转移到沟道中。常规工艺在激活源极/漏极掺杂剂之前形成应力诱发(inducing)材料，从而减少了在半导体材料中诸如碳的被激活材料的量。
【0031】现在参看图1N，说明了根据本发明的各个实施方式所制造的结果PMOS晶体管的放大图。在该实施方式中，注意半导体材料165与沟道隔开一段距离190，该距离不大于偏移隔离层116的厚度。让半导体材料更接近沟道提供了对现有技术的显著改进，因为压应力被引到沟道中。
【0032】根据各个替代的实施方式，CMOS器件可以用PMOS晶体管或NMOS晶体管中的仅一个晶体管进行制造，所述晶体管具有邻近沟道成形的半导体材料165。例如，CMOS器件可以被制造，以致只有NMOS晶体管使凹槽160填充半导体材料165以便将应力引到沟道中。替代地，CMOS器件可以被制造，以致只有NMOS晶体管使凹槽160填充半导体材料165以便将应力引到沟道中。
【0033】另外，虽然以上是参照碳和锗的使用以形成SiC和硅锗晶格结构对本发明进行描述的。然而，本发明预期可以使用会与硅产生合金并用来将压应力引到MOS器件(例如PMOS器件)的沟道中的任何元素，并且这些替换物预期都落在本发明的范围之内。
【0034】本发明所涉及的本领域技术人员会明白，对所述的实施方式可以进行各种添加、删除、替换和其它修改，而这不偏离本发明要求保护的范围。

Claims (9)

1.一种形成半导体器件的方法，包括：
在衬底上形成栅极；
通过掺杂邻近所述栅极的有源区的第一部分和第二部分，形成源极区和漏极区；
形成所述源极区中的第一凹槽和所述漏极区中的第二凹槽；
通过加热所述有源区，激活所述源极区和所述漏极区中的掺杂剂；和
在激活所述源极区和所述漏极区中的掺杂剂之后，将半导体材料沉积到所述第一凹槽和所述第二凹槽中。
2.根据权利要求1所述的方法，进一步包括：
掺杂所述有源区的第三部分和第四部分，其中所述第三部分和所述第四部分的深度小于第一和第二被掺杂的部分。
3.根据权利要求1或2所述的方法，其中所述半导体材料包含至少1％被激活的碳。
4.根据权利要求3所述的方法，其中所述器件是CMOS器件；其中所述第一和第二凹槽离栅极的侧壁偏移5纳米到30纳米；且其中所述第一和第二凹槽具有在所述衬底的表面之下30纳米到60纳米的深度。
5.根据权利要求1或2所述的方法，其中沉积在所述第一和第二凹槽中的所述半导体材料形成分别相对于周围源极区和漏极区的应变区。
6.一种半导体器件，包括：
衬底上的栅极结构；
邻近所述栅极结构的源极区和漏极区；
半导体材料，其包含在所述源极区和漏极区中形成的至少1％被激活的碳；和
硅化物，其接触所述源极区和漏极区的一部分。
7.根据权利要求6所述的器件，其中所述器件是CMOS器件。
8.根据权利要求6或7所述的器件，其中所述半导体材料填充源极中的第一凹槽和漏极中的第二凹槽。
9.根据权利要求6或7所述的器件，进一步包括设在所述栅极结构的第一和第二部分下的第一和第二被掺杂区，其中所述第一和第二被掺杂区包括与所述源极和漏极的掺杂分布不同的掺杂分布。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103545255A (zh) * 2012-07-11 2014-01-29 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN108695258A (zh) * 2017-04-11 2018-10-23 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005041225B3 (de) * 2005-08-31 2007-04-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung vertiefter verformter Drain/Source-Gebiete in NMOS- und PMOS-Transistoren
DE102006015090B4 (de) * 2006-03-31 2008-03-13 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung unterschiedlicher eingebetteter Verformungsschichten in Transistoren
US7410875B2 (en) * 2006-04-06 2008-08-12 United Microelectronics Corp. Semiconductor structure and fabrication thereof
US7473594B2 (en) 2006-07-25 2009-01-06 International Business Machines Corporation Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon
US7998821B2 (en) * 2006-10-05 2011-08-16 United Microelectronics Corp. Method of manufacturing complementary metal oxide semiconductor transistor
US7732285B2 (en) * 2007-03-28 2010-06-08 Intel Corporation Semiconductor device having self-aligned epitaxial source and drain extensions
US20080290416A1 (en) * 2007-05-21 2008-11-27 Taiwan Semiconductor Manufacturing Co., Ltd. High-k metal gate devices and methods for making the same
US20080293192A1 (en) * 2007-05-22 2008-11-27 Stefan Zollner Semiconductor device with stressors and methods thereof
US8293631B2 (en) * 2008-03-13 2012-10-23 International Business Machines Corporation Semiconductor devices having tensile and/or compressive stress and methods of manufacturing
US7902009B2 (en) * 2008-12-11 2011-03-08 Intel Corporation Graded high germanium compound films for strained semiconductor devices
US8187971B2 (en) 2009-11-16 2012-05-29 Tel Epion Inc. Method to alter silicide properties using GCIB treatment
US8304840B2 (en) * 2010-07-29 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Spacer structures of a semiconductor device
US9263342B2 (en) * 2012-03-02 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a strained region

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5956590A (en) * 1995-05-25 1999-09-21 United Microelectronics Corp. Process of forming a field effect transistor without spacer mask edge defects
US6187641B1 (en) * 1997-12-05 2001-02-13 Texas Instruments Incorporated Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region
US5994747A (en) * 1998-02-13 1999-11-30 Texas Instruments-Acer Incorporated MOSFETs with recessed self-aligned silicide gradual S/D junction
US6621131B2 (en) 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
US6902980B2 (en) * 2003-06-05 2005-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating a high performance MOSFET device featuring formation of an elevated source/drain region
US6787864B2 (en) * 2002-09-30 2004-09-07 Advanced Micro Devices, Inc. Mosfets incorporating nickel germanosilicided gate and methods for their formation
US6921913B2 (en) * 2003-03-04 2005-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone
US7208362B2 (en) * 2003-06-25 2007-04-24 Texas Instruments Incorporated Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel
US7132338B2 (en) * 2003-10-10 2006-11-07 Applied Materials, Inc. Methods to fabricate MOSFET devices using selective deposition process
US6946350B2 (en) * 2003-12-31 2005-09-20 Intel Corporation Controlled faceting of source/drain regions

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103545255A (zh) * 2012-07-11 2014-01-29 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN103545255B (zh) * 2012-07-11 2016-02-03 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN108695258A (zh) * 2017-04-11 2018-10-23 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN108695258B (zh) * 2017-04-11 2020-11-03 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

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