CN101127347A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN101127347A
CN101127347A CNA200710101059XA CN200710101059A CN101127347A CN 101127347 A CN101127347 A CN 101127347A CN A200710101059X A CNA200710101059X A CN A200710101059XA CN 200710101059 A CN200710101059 A CN 200710101059A CN 101127347 A CN101127347 A CN 101127347A
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film
conductive component
scolder
semiconductor device
metal film
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CN100541791C (zh
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副岛康志
栗田洋一郎
川野连也
山道新太郎
菊池克
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NEC Electronics Corp
NEC Corp
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Abstract

第一电子电路组件以及第二电子电路组件分别通过第一焊料以及第二焊料电连接到导电部件。导电部件形成在树脂膜中。导电部件被配置为包括第二扩散阻挡金属膜。第二扩散阻挡金属膜防止第二焊料的扩散。在导电部件以及第一焊料之间配置第一扩散阻挡金属膜。第一扩散阻挡金属膜防止第一焊料的扩散。在树脂膜的第一表面上以及在导电部件上,形成粘合金属膜使其与树脂膜以及导电部件相接触。与第一焊料以及第一扩散阻挡金属膜的任何一个相比,粘合金属膜具有与树脂膜的更强的粘合性。

Description

半导体器件及其制造方法
本申请基于日本专利申请No.2006-121575,其内容通过引用并入此处。
技术领域
本发明涉及半导体器件及其制造方法,特别涉及一种具有焊料凸点电极的半导体器件及其制造方法。
背景技术
可以在日本未决公开专利公开No.H6-140465(专利文献1)中找到现有公知的半导体器件的一个实例。在该文献中描述的半导体器件包括通常由聚酰亚胺膜构成的绝缘基底材料,在其两个表面上贴装有具有焊料凸点电极的IC芯片,以及具有焊料凸点电极的电路布线板。Cu膜与绝缘基底材料紧密接触。除了专利文献1之外的与本发明相关的现有技术文献包括日本未决公开专利公开No.H11-345933(专利文献2)以及No.2001-217388(专利文献3)。
发明内容
然而,在专利文献1中描述的半导体器件中,组成焊料凸点电极的焊料材料通过Cu膜扩散,到达了绝缘基底材料和Cu膜之间的界面,并且因此绝缘基底材料和Cu膜变得更易于彼此分离。
根据本发明,提供了一种半导体器件,包括:绝缘膜;配置在该绝缘膜中的导电部件;第一电子电路组件,其配置在该绝缘膜的第一表面侧上并且通过第一焊料电连接到该导电部件;第二电子电路组件,其配置在该绝缘膜的与第一表面侧相对的第二表面侧上,并且通过第二焊料电连接到该导电部件;第一扩散阻挡金属膜,其配置在导电部件以及第一焊料之间,且防止第一焊料的扩散;第二扩散阻挡金属膜,其构成至少部分导电部件,且防止第二焊料的扩散;以及粘合金属膜,其配置在该绝缘膜的第一表面上以及导电部件上,与该绝缘膜以及导电部件相接触,且与第一焊料的粘合性和第一扩散阻挡金属膜的粘合性相比,其与该绝缘膜的粘合性更强。
在该半导体器件中,第一扩散阻挡金属膜配置在粘合金属膜和第一焊料之间,并且第二扩散阻挡金属膜配置在粘合金属膜以及第二焊料之间。由于这些扩散阻挡金属膜的作用,可以防止该焊料到达绝缘膜和粘合金属膜之间的界面。因此,可以实现不易于导致绝缘膜以及粘合金属膜之间的分离的半导体器件。
根据本发明,还提供一种制造半导体器件的方法,其包括:在绝缘膜中形成导电部件,该导电部件的至少一部分由第二扩散阻挡金属膜构成;在绝缘膜以及导电部件上形成粘合金属膜,从而使得该粘合金属膜与绝缘膜以及导电部件相接触;在该粘合金属膜上形成第一扩散阻挡金属膜;在第一扩散阻挡金属膜上通过第一焊料设置第一电子电路组件,从而使得第一电子电路组件电连接到该导电部件;以及在绝缘膜的与第一电子电路组件相对的一侧上通过第二焊料设置第二电子电路组件,从而使得第二电子电路组件电连接到该导电部件,其中与第一焊料的粘合性以及第一扩散阻挡金属膜的粘合性相比,所述粘合金属膜具有的与所述绝缘膜的粘合性更强,并且该第一和第二扩散阻挡金属膜分别防止了第一和第二焊料的扩散。
该方法包括如下步骤:通过使用第二扩散阻挡金属膜形成配置在其至少一部分中的导电部件的步骤,以及在所述粘合金属膜上形成第一扩散阻挡金属膜的步骤。因此,所制造的半导体器件具有配置在粘合金属膜和第一焊料之间的第一扩散阻挡金属膜,并且还具有配置在粘合金属膜和第二焊料之间的第二扩散阻挡金属膜。由于这些扩散阻挡金属膜的作用,可以防止焊料到达绝缘膜和粘合金属膜之间的界面。因此,可以实现不易于导致绝缘膜以及粘合金属膜之间的分离的半导体器件。
根据本发明,可以实现不易于导致绝缘膜以及粘合金属膜之间的分离的半导体器件及上述半导体器件的制造方法。
附图说明
参考附图,根据以下说明,本发明的上述及其他目的、特征以及优点将变得更加明显,其中:
图1示出了根据本发明的半导体器件的实施例的剖面图;
图2示出了图1所示的部分半导体器件的剖面图;
图3示出了图1所示的部分半导体器件的平面图;
图4A到4C示出了本发明的半导体器件的制造方法的实施例的工艺步骤图;
图5A到5C示出了本发明的半导体器件的制造方法的实施例的工艺步骤图;
图6A到6C示出了本发明的半导体器件的制造方法的实施例的工艺步骤图;
图7A到7C示出了本发明的半导体器件的制造方法的实施例的工艺步骤图;
图8A以及8B示出了本发明的半导体器件的制造方法的实施例的工艺步骤图;
图9A以及9B示出了本发明的半导体器件的制造方法的实施例的工艺步骤图;
图10示出了实施例的变型例的剖面图;
图11示出了实施例的另一变型例的剖面图;
图12示出了实施例的另一变型例的剖面图;
图13示出了实施例的另一变型例的剖面图;
图14示出了实施例的另一变型例的剖面图;
图15示出了实施例的另一变型例的剖面图;以及
图16示出了实施例的另一变型例的剖面图。
具体实施方式
现在将参考说明性的实施例在此描述本发明。本领域技术人员将认识到使用本发明的教导可以完成多种可选实施例,而且本发明不局限于为了说明的目的而示出的实施例。
参考附图,以下段落将详述根据本发明的半导体器件的实施例及其制造方法。应当注意,在附图的说明中,任何相似的部件都给予了相似的参考标号,从而避免了重复说明。
图1示出了根据本发明的半导体器件的实施例的剖面图,图2示出了部分半导体器件的剖面图。该图示出了由图1所示的圆C1围绕的部分以及周边。图3示出了图1所示的部分半导体器件的平面图。半导体器件1具有半导体芯片10(第一电子电路组件),以及半导体芯片20(第二电子电路组件)。半导体芯片10以及半导体芯片20是例如LSI芯片。半导体芯片10被模制树脂82所覆盖。半导体芯片10以及半导体芯片20的连接部分30通过互连70电连接到半导体器件1的外部电极端90。该外部电极端90例如是BGA(球栅阵列)。
以下,将参考图2说明连接部分30的结构。在树脂膜50(绝缘膜)中,形成了导电部件40。树脂膜50的厚度例如是5到10μm。该厚度优选地是20μm或以下。树脂膜50可以举例为:环氧树脂膜、BT树脂膜、聚酰亚胺树脂膜等等。
每个导电部件40由Cu膜42以及Ni膜44(第二扩散阻挡金属膜)构成。Ni膜44防止了后面描述的焊料24的扩散。从图中很明显地看出,本实施例中的Ni膜44暴露到树脂膜50的表面S1(第一表面),以及Cu膜42暴露到树脂膜50的表面S2(第二表面)。换言之,表面S1侧上的导电部件40的表面层由Ni膜44构成,以及表面S2侧上的导电部件40的表面层由Cu膜42构成。Cu膜42的厚度例如是2到5μm。Ni膜44的厚度例如是3到5μm。
半导体芯片10以及半导体芯片20分别配置在树脂膜50的表面S1侧以及表面S2侧上。半导体芯片10以及半导体芯片20分别通过焊料14(第一焊料)以及焊料24(第二焊料)电连接到导电部件40。
在导电部件40以及焊料14之间,配置了Ni膜66(第一扩散阻挡金属膜)。该Ni膜防止了焊料14的扩散。在树脂膜50的表面S1上以及在导电部件40上,形成了Ti膜62(粘合金属膜),使其与树脂膜50以及导电部件40相接触。与焊料14以及Ni膜66的任何一个相比,Ti膜62具有与树脂膜50的更强的粘合性。作为该类的粘合金属膜,使用了如下的金属膜,其所具有的与树脂膜50的粘合性强于Cu膜的粘合性。此处的粘合性程度可以通过诸如带剥落(Tape peeling)的剥离试验来测量。由于Ni膜44配置在表面S1侧上的导电部件40的表面层中,因此Ni膜44与Ti膜62彼此相接触。在本实施例中,Cu膜64配置在Ti膜62以及Ni膜66之间。
上述的每一焊料14具有连接到半导体芯片10的电极12的一端,以及连接到Ni膜66的另一端。每一焊料24具有连接到半导体芯片20的电极22的一端,以及连接到导电部件40的Cu膜42的另一端。很明显如图2所示,在树脂膜50的表面S2上,每一焊料24与导电部件40相接触。换言之,在半导体器件1中,导电部件40以及焊料24彼此连接,而在其中间没有设置焊垫等。
在树脂膜50的表面S1上形成了互连70。互连70包括了构成粘合金属膜(在本实施例中,Ti)的材料。更具体地说,互连70由Ti膜72、Cu膜74以及Ni膜76构成。这些Ti膜72、Cu膜74以及Ni膜76以该顺序堆叠在表面S1上。换言之,互连70具有与如下所述的堆叠结构相同的堆叠结构,所述的堆叠结构由Ti膜62、Cu膜64以及Ni膜66构成。利用底部填充树脂84填充半导体芯片10和树脂膜50之间的间隙。类似地,利用底部填充树脂86填充半导体芯片20和树脂膜50之间的间隙。
如上所述,在半导体器件1中,半导体芯片10和半导体芯片20通过其相应的电极12、22连接,且同时电路形成表面彼此相对。在这些半导体芯片10、20之间,存在容纳互连70的树脂膜50,其中该树脂膜50具有形成在其中的、用于连接的孔。在所述孔中,形成了导电部件40。在连接电极12以及电极22的虚拟的线上,从电极12侧观察,配置有焊料14、Ni膜66、Cu膜64、Ti膜62、导电部件40以及焊料24。
在本实施例中,与焊料14接触的Au膜(第一Au膜)可以配置在Ni膜66上。还允许在导电部件40的Cu膜42上配置与焊料24接触的Au膜(第二Au膜)。
参考图4A到9B,将描述半导体器件1的制造的示例性方法,作为制造本发明的半导体器件的方法实施例。该方法包括以下步骤(a)到(g):
(a)在形成导电部件40之前,在支撑衬底上形成树脂膜50(图4A到图4C)
(b)在树脂膜50中(图5A),形成导电部件40;
(c)在树脂膜50上以及在导电部件40上形成Ti膜62,使其与树脂膜50以及导电部件40相接触(图5B到图5C);
(d)在Ti膜62上形成Ni膜66(图6A到图6C);
(e)在Ni膜66通过焊料14设置半导体芯片10,从而使得半导体芯片10电连接到导电部件40(图7A到图7C);
(f)在设置半导体芯片10之后以及在设置半导体芯片20之前,去除支撑衬底(图8A到图8B);以及
(g)在树脂膜50的与半导体芯片10相对的一侧上通过焊料24设置半导体芯片20,从而使得半导体芯片20电连接到导电部件40(图9A到图9B)。
更详细地,首先制备诸如硅衬底等支撑衬底92(图4A)。在支撑衬底92上,通过溅射形成具有大约0.2μm厚度的Cu膜作为电镀籽晶层94(图4B)。在电镀籽晶层94上涂敷光敏性聚酰亚胺,烘干、在边缘上漂净,经受曝光和显影,从而形成预定图案。由此形成了具有孔50a的树脂膜50(图4C)。
接下来,通过进行化学镀在孔50a中形成具有大约3μm厚度的Cu膜42以及具有大约3μm厚度的Ni膜44。在通过Ar等离子蚀刻去除Ni膜44表面上的氧化膜之后,Ti膜62以及Cu膜64被形成为溅射籽晶膜(图5B)。光致抗蚀剂R1被涂敷在Cu膜64上,烘干并经受曝光以及显影,从而形成预定的开口(图5C)。
接下来,在光致抗蚀剂R1的开口中通过化学镀顺序地形成具有大约3μm厚度的Cu膜、具有大约6μm厚度的Ni膜、以及具有大约1μm厚度的Au膜(图6A)。以下,该Cu膜、Ni膜以及Au膜被共同地称为互连膜60。接下来,通过溶剂清洗去除光致抗蚀剂R1(图6B)。随后,通过在其上没有形成互连膜60的部分中进行选择性地湿蚀刻从而去除Ti膜62以及Cu膜64(图6C)。
接下来,半导体芯片10的每个电极(未示出)通过焊料14连接到互连膜60(图7A)。利用底部填充树脂84填充半导体芯片10和树脂膜50之间的间隙(图7B)。形成模制树脂82从而覆盖半导体芯片10(图7C)。
接着,去除支撑衬底92(图8A)。可以通过例如使用研磨、化学机械抛光、蚀刻等等来去除支撑衬底92。接着,通过湿蚀刻去除电镀籽晶层94(图8B)。在作为去除支撑衬底92以及电镀籽晶层94的结果而暴露的Cu膜42上,通过无电的置换Au镀形成Au膜43(图9A)。半导体芯片20的每个电极(未示出)通过焊料24连接到Au膜43。利用底部填充树脂86填充半导体芯片20和树脂膜50之间的间隙(图9B)。以这种方法获得了图1所示的半导体器件1。
将说明该实施例的效果。在本实施例中,Ni膜66配置在Ti膜62以及焊料14之间,以及Ni膜44配置在Ti膜62以及焊料24之间。由于Ni膜66的作用,可以防止构成焊料14的材料到达树脂膜50和Ti膜62之间的界面。类似地,由于Ni膜44的作用,可以防止构成焊料24的材料到达上述界面。因此,可以实现不易于导致树脂膜50和Ti膜62之间的分离的半导体器件及上述半导体器件的制造方法。
相反,专利文献1中描述的半导体器件不具有作为扩散阻挡金属膜的Ni膜等,因此焊料很可能通过Cu膜扩散,并且到达Cu膜以及绝缘基底材料之间的界面。一旦焊料到达界面,则绝缘基底材料和Cu膜之间的粘合性退化,以及由此绝缘基底材料和Cu膜之间的应力差将导致在绝缘基底材料和Cu膜之间的界面处发生分离。糟糕的是,上述分离将会进一步诱发绝缘基底材料中的金属膜和Cu膜之间的界面处的分离。这是由于该绝缘基底材料和Cu膜之间的分离会导致上述金属膜和Cu膜之间的界面处的应力集中。
专利文献2中描述的半导体器件具有配置在其中扩散阻挡金属膜,其由Ti/Ni/Pd构成,位于导电浆(paste)以及焊料之间。然而,不存在被配置作为与树脂膜紧密接触的粘合金属膜。专利文献3中描述的半导体器件具有贴装在柔性衬底的两个表面上的半导体芯片。然而,不存在用于防止配置到其上的焊料发生扩散的扩散阻挡金属膜。
与专利文件1-3不同,通过在如上所述的粘合金属膜的两侧上配置扩散阻挡金属膜,本实施例成功地实现了粘合金属膜以及树脂膜之间的高水平的粘合性。在专利文献1中描述的半导体器件中,一种改善Cu膜与绝缘基底材料的粘合性的可行方法可以是使Cu膜的表面粗糙化。然而,在这种情况下,可能会出现形成精细图案变得困难的缺点。
进一步在本实施例中,Ni膜44与Ti膜62接触。由于该结构,即使当焊料材料扩散到树脂膜50中的Cu膜42中时,也成功地防止了构成焊料24的焊料材料到达Ni膜44和Ti膜62之间的界面。
焊料24与表面S2上的导电部件40相接触。与焊垫形成在表面S2上以及焊料24和导电部件40通过焊垫相连的情况相比,该结构可以减少工艺步骤的数目。与通过焊垫完成连接的情况相比,该结构还可以减少焊料24以及导电部件40之间的接触面积。
如该实施例所示,在Ni膜66上提供Au膜可以成功地提高对焊料14的可湿性(wettability)。类似地,对于在Cu膜42上配置Au膜的情况,也可以改善对焊料24的可湿性。
互连70包括构成Ti膜62的材料。该结构允许与Ti膜62同时形成部分或全部互连70,由此可以抑制工艺步骤数目的增加。具体来说,在本实施例中,互连70具有与如下堆叠结构相同的堆叠结构,所述堆叠结构由Ti膜62、Cu膜64以及Ni膜66构成。通过该结构,可以更有效地抑制工艺步骤数目的增加。
与厚度超过20μm的情况相比,当其厚度为20μm或者更小时,可以更容易地形成树脂膜50。然而,当树脂膜50变得越来越薄时,除非通过Ni膜44防止焊料扩散,否则构成焊料24的焊料材料就会变得更易于到达树脂膜50以及Ti膜62之间的界面。当树脂膜50的厚度为20μm或者更小时,该问题变得更加显著。因此在这种情况下,配置Ni膜44的效果变得特别大。
在本实施例中,直到设置半导体芯片10的工艺步骤都在支撑衬底92上进行。与没有使用支撑衬底92的情况相比,该结构更加容易处理。
根据本发明的半导体器件及其制造方法不局限于上述实施例,并且允许各种修改。例如,可以通过至少在其一部分中的第二扩散阻挡金属膜来配置导电部件40,其中如图10所示,可以通过Cu膜42配置表面S1侧上的表面层,以及可以通过Ni膜44配置表面S2侧上的表面层。仍然同时允许,如图11所示,可以通过Cu膜42来配置两侧上的导电部件40的表面层,以及Ni膜44配置在Cu膜42之间。可以通过Ni膜来配置导电部件40的整个部分。
上述实施例示出了另一膜(Cu膜64,图2)给出在粘合金属膜以及第一扩散阻挡金属膜之间的情况。然而,可以直接在粘合金属膜上配置第一扩散阻挡金属膜。换言之,粘合金属膜以及第一扩散阻挡金属膜可以彼此紧密接触。
上述实施例示出了第一和第二电子电路组件是半导体芯片的情况。然而,第一以及第二电子电路组件可以是互连衬底。仍然还可以允许第一以及第二电子电路组件其中任何一个是半导体芯片,而另一个可以是互连衬底。
上述实施例示出了Ti膜作为粘合金属膜。然而,粘合金属膜可以是TiN膜、W膜、TiW膜、Cr膜、Ta膜或者TaN膜。考虑到实际价值,Ti膜是特别优选的。
上述实施例示出了Ni膜作为第一以及第二扩散阻挡金属膜。然而,第一以及第二扩散阻挡金属膜可以是NiV膜等等。考虑到实际价值,Ni膜是特别优选的。并不总是第一以及第二扩散阻挡金属膜必须相同,而是其可以是不同的膜。
上述实施例示例了树脂膜作为绝缘膜。然而,绝缘膜可以是除了树脂膜之外的任何绝缘膜。
上述实施例举例说明了使用支撑衬底的制造方法。然而,支撑衬底的使用不是必需的。换言之,工艺步骤(a)和(f)可以从上述工艺步骤(a)到(g)中省略。
此外,互连70的结构不局限于图2所示的,而是允许各种修改。图12示出了互连70的示例性结构,在所述结构中,半导体芯片10的电极12的位置与半导体芯片20的电极22的位置彼此不同。图13示出了互连70的示例性结构,在所述结构中,半导体芯片10的电极12通过互连70连接到外部电极端90(参见图1)。互连70的右手端连接到外部电极端90。图14示出了互连70的示例性结构,在所述结构中,半导体芯片20的电极22通过互连70连接到外部电极端90。互连70的右手端连接到外部电极端90。图15示出了互连70的示例性结构,在所述结构中,互连70连接到连接部分30。应当注意,底部填充树脂84、86(参见图2)在图12到图15中没有示出。
还允许与连接部分30同时形成互连70。在这种情况下,在对光致抗蚀剂R1进行曝光和显影的步骤中(参见图5C),不仅在用于形成连接部分30的部分中而且在用于形成互连70的部分中去除光致抗蚀剂R1,如图16所示。随后,还在该部分P70中形成互连膜60,以及通过用作掩模的互连膜60蚀刻Cu膜64和Ti膜62。通过该工艺,与连接部分30同时地形成了互连70。其他工艺步骤与参考图4A到图9B说明的工艺步骤相同。
很明显本发明不限于上述实施例,并且可以在不背离本发明的保护范围和精神的情况下进行变化和改变。

Claims (11)

1.一种半导体器件,包括:
绝缘膜;
配置在所述绝缘膜中的导电部件;
第一电子电路组件,其配置在所述绝缘膜的第一表面侧上,并且通过第一焊料电连接到所述导电部件;
第二电子电路组件,其配置在所述绝缘膜的与所述第一表面侧相对的第二表面侧上,并且通过第二焊料电连接到所述导电部件;
第一扩散阻挡金属膜,其配置在所述导电部件和所述第一焊料之间,且防止所述第一焊料的扩散;
第二扩散阻挡金属膜,其构成至少部分所述导电部件,且防止所述第二焊料的扩散;以及
粘合金属膜,其配置在所述绝缘膜的所述第一表面上以及所述导电部件上,与所述绝缘膜以及所述导电部件相接触,与所述第一焊料与所述绝缘膜的粘合性以及所述第一扩散阻挡金属膜与所述绝缘膜的粘合性相比,所述粘合金属膜具有与所述绝缘膜的更强的粘合性。
2.如权利要求1的半导体器件,
其中所述第二扩散阻挡金属膜与所述粘合金属膜相接触。
3.如权利要求1的半导体器件,
其中所述第二焊料与所述绝缘膜的所述第二表面上的所述导电部件相接触。
4.如权利要求1的半导体器件,
其中所述粘合金属膜是Ti膜、TiN膜、W膜、TiW膜、Cr膜、Ta膜或者TaN膜。
5.如权利要求1的半导体器件,
其中所述第一和第二扩散阻挡金属膜中的每一个是Ni膜或者NiV膜。
6.如权利要求1的半导体器件,进一步包括配置在所述第一扩散阻挡金属膜上的第一Au膜,其与所述第一焊料相接触。
7.如权利要求1的半导体器件,进一步包括配置在所述导电部件上的第二Au膜,其与所述第二焊料相接触。
8.如权利要求1的半导体器件,进一步包括配置在所述绝缘膜的所述第一表面上的互连,其包括构成所述粘合金属膜的材料。
9.如权利要求1的半导体器件,
其中所述绝缘膜具有20μm或者更小的厚度。
10.一种制造半导体器件的方法,包括:
在绝缘膜中形成导电部件,所述导电部件的至少一部分由第二扩散阻挡金属膜构成;
在所述绝缘膜上以及在所述导电部件上形成粘合金属膜,从而使得所述粘合金属膜与所述绝缘膜和所述导电部件相接触;
在所述粘合金属膜上形成第一扩散阻挡金属膜;
在所述第一扩散阻挡金属膜上,通过第一焊料设置第一电子电路组件,从而使得所述第一电子电路组件电连接到所述导电部件;以及
在所述绝缘膜的与所述第一电子电路组件相对的一侧上,通过第二焊料设置第二电子电路组件,从而使得所述第二电子电路组件电连接到所述导电部件,
其中与所述第一焊料与所述绝缘膜的粘合性以及所述第一扩散阻挡金属膜与所述绝缘膜的粘合性相比,所述粘合金属膜具有与所述绝缘膜的更强的粘合性,并且
所述第一和第二扩散阻挡金属膜分别防止所述第一和第二焊料的扩散。
11.如权利要求10的制造半导体器件的方法,进一步包括:
在所述形成所述导电部件之前,在支撑衬底上形成所述绝缘膜;以及
在所述设置所述第一电子电路组件之后,以及在所述设置所述第二电子电路组件之前,去除所述支撑衬底。
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JP3169254B2 (ja) * 1992-03-18 2001-05-21 株式会社日立製作所 多層配線基板
JP2680232B2 (ja) 1992-10-22 1997-11-19 ローム株式会社 半田ワイヤによるワイヤーボンディング方法
US6730541B2 (en) * 1997-11-20 2004-05-04 Texas Instruments Incorporated Wafer-scale assembly of chip-size packages
JP3397689B2 (ja) * 1998-06-01 2003-04-21 株式会社東芝 マルチチップ半導体装置およびその製造方法
JP2001217388A (ja) 2000-02-01 2001-08-10 Sony Corp 電子装置およびその製造方法
US20020074637A1 (en) * 2000-12-19 2002-06-20 Intel Corporation Stacked flip chip assemblies
JP4092890B2 (ja) * 2001-05-31 2008-05-28 株式会社日立製作所 マルチチップモジュール
JP2003264260A (ja) * 2002-03-08 2003-09-19 Toshiba Corp 半導体チップ搭載基板、半導体装置、半導体モジュール及び半導体装置実装基板
US7045887B2 (en) * 2002-10-08 2006-05-16 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
US20040140571A1 (en) * 2003-01-17 2004-07-22 Matsushita Electric Industrial Co., Ltd. Mounting structure of electronic device
JP2006012890A (ja) * 2004-06-22 2006-01-12 Canon Inc 半導体装置およびその製造方法
JP3905100B2 (ja) * 2004-08-13 2007-04-18 株式会社東芝 半導体装置とその製造方法
JP2006216758A (ja) * 2005-02-03 2006-08-17 Three M Innovative Properties Co プリント回路基板の接続方法
JP4344707B2 (ja) * 2005-02-24 2009-10-14 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US7868457B2 (en) * 2007-09-14 2011-01-11 International Business Machines Corporation Thermo-compression bonded electrical interconnect structure and method

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