CN101101900A - 管芯配置及制造方法 - Google Patents
管芯配置及制造方法 Download PDFInfo
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- CN101101900A CN101101900A CNA2007101290444A CN200710129044A CN101101900A CN 101101900 A CN101101900 A CN 101101900A CN A2007101290444 A CNA2007101290444 A CN A2007101290444A CN 200710129044 A CN200710129044 A CN 200710129044A CN 101101900 A CN101101900 A CN 101101900A
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- tube core
- connector
- salient point
- configuration
- welding disc
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Abstract
一种管芯配置包括:管芯,具有活性侧以及与活性侧相对的非活性侧。非活性侧连接到热沉。连接件可以提供在活性侧上。
Description
技术领域
本发明涉及管芯配置以及制造管芯配置的方法。
背景技术
当前的半导体封装技术要求使用芯片载体或间插物(例如衬底)作为从芯片到印刷电路板的互连。这取消了大多数普通芯片所经历的冗长组装过程。
此外,在常规半导体封装中,热沉附到封装上。这导致相当不良的冷却性能。
所以需要有一种具有改进冷却性能的芯片配置,以下也称为管芯配置。
发明内容
本发明的实施例提供了具有改进冷却性能的管芯配置以及制造管芯配置的方法。
按照本发明的示范实施例,提供一种管芯配置,它包括管芯,管芯具有活性侧以及与活性侧相对的非活性侧,非活性侧连接到热沉。
按照本发明的另一示范实施例,提供一种管芯配置,它包括管芯,管芯的第一侧连接到热沉,管芯的第二侧与管芯的第一侧相对,并连接到管芯配置焊盘区。
鉴于以下附图和详细说明将更好理解本发明的这些和其它特征。
附图说明
为了更全面理解本发明及其优点,现参考结合附图所作的以下说明,附图包括:
图1示出按照本发明示范实施例的管芯配置的截面图;
图2示出按照本发明另一示范实施例的管芯配置的截面图;
图3A到3S示出按照本发明示范实施例的管芯配置在其制造的不同时间瞬间的截面图;
图4示出按照本发明示范实施例的管芯配置顶视图,显示管芯附到金属板上;
图5示出按照本发明示范实施例的图4中管芯配置的金属板的部分A的截面图;
图6示出按照本发明示范实施例的图4中管芯配置的部分B的截面图;
图7示出按照本发明示范实施例的管芯配置的凸点的顶视图;及
图8示出按照本发明示范实施例的管芯配置的凸点的截面图。
为清晰起见,以前标识的特征在随后的附图中保留其参考标记。
具体实施方式
以下对实施和使用目前优选的实施例作详细讨论。但应理解,本发明提供了许多可应用的发明概念,它们可在多种具体环境中实施。本文所讨论的具体实施例仅说明实施和使用本发明的具体途径,而不是限制本发明的范围。
按照本发明的示范实施例,管芯配置还包括在管芯的非活性侧和热沉之间的热界面材料。
热沉可包括金属板或可由金属板形成,以下也称为引线框。
显然,在本发明的实施例中,管芯封装(也称为芯片封装)中的热沉直接附到管芯上。“直接”在此情况下应理解为热沉附连(连接)到管芯,可选地经由热界面材料,但在热沉和管芯之间没有任何封装材料诸如成型料(例如环氧树脂)。换句话说,在本发明一个示范实施例中,在热沉和管芯之间没有或仅有导热材料。
在本发明的示范实施例中,管芯配置的热扩散性能以及因此其冷却性能得到改进,且不需要外部热扩散器,从而也增加了模块可靠性。这导致产品成本节约以及快的周转时间。
管芯配置可包括任何种类的芯片,例如存储器芯片、逻辑芯片或微处理器芯片。换句话说,管芯配置的管芯可具有一个或多个电子元件,例如电阻器、电容器、电感器、晶体管、任何类型的存储器单元(随机存取存储器或只读存储器)等等。
为了接触管芯中的电子元件,管芯配置可具有一个或多个管芯配置焊盘区。管芯配置焊盘区可连接到管芯的管芯焊盘区,管芯焊盘区又连接到管芯中的电子元件。
在本发明的实施例中,可以提供管芯配置连接件,它们可连接到管芯配置焊盘区。管芯配置连接件可以是焊料件,诸如球栅阵列(BGA)焊料凸点。
按照本发明的实施例,焊料件是无铅焊料件。
按照本发明的另一实施例,可将成型材料提供在管芯周围,其中管芯的非活性侧保持至少部分暴露。因此,管芯的至少部分暴露的非活性侧可用来将管芯连接到外部装置,诸如印刷电路板(PCB)。
另外,管芯配置还可包括管芯活性侧上的管芯焊盘区,以及将管芯配置焊盘区连接到管芯焊盘区的管芯连接件。管芯焊盘区可连接到管芯的电子元件。
在本发明的一个实施例中,管芯连接件中的至少一个管芯连接件包括凸点或由凸点形成,例如柱状凸点,例如金属凸点。金属凸点可由任何适合的金属例如铜制成。
按照本发明的一个实施例,凸点包括第一部分凸点和第二部分凸点,第二部分凸点具有不同于(例如大于)第一部分凸点的宽度。
在本发明另一实施例中,管芯配置连接件可位于第二部分凸点上。在此情况下,管芯配置连接件例如焊料凸点附到第二部分凸点,换句话说,附到具有扩大截面的部分凸点上,这简化了安装过程,并节省了将外部装置诸如印刷电路板连接到管芯焊盘所用的金属。
按照本发明另一示范实施例,提供一种管芯配置,它包括:管芯,具有活性侧以及与活性侧相对的非活性侧;管芯非活性侧上的热界面材料层,该热界面材料层连接到金属板。在此实施例中,金属板一方面在制造过程期间用作管芯的载体,另一方面用作热沉,它直接连接到管芯,从而增强了管芯配置的热性能。
管芯配置连接件可以连接管芯配置焊盘区。
此外,管芯配置连接件可以是焊料件。
在上述实施例的一种配置中,成型材料可提供在管芯周围,至少部分暴露出热沉。而且,可将管芯焊盘区提供在管芯的活性侧上,且可提供管芯连接件,通过成型材料将管芯配置焊盘区连接到管芯焊盘区。
按照本发明的另一示范实施例,提供一种管芯配置,它包括管芯,管芯的第一侧连接到热沉,管芯的第二侧与管芯的第一侧相对,并连接到管芯配置焊盘区。
按照本发明的另一示范实施例,提供一种管芯配置,它包括:管芯,管芯的第一侧连接到热沉,管芯的第二侧与管芯的第一侧相对,并连接到管芯配置焊盘区;以及电路板,连接到管芯配置焊盘区。
电路板可以是印刷电路板。
按照本发明的另一示范实施例,提供一种管芯配置,它包括:管芯;管芯的第一侧,连接到金属板;管芯周围的成型材料,至少部分暴露出金属板;管芯的第二侧,与管芯的第一侧相对并包括在管芯活性侧上的管芯焊盘区;管芯配置焊盘区;管芯连接件,通过成型材料将管芯配置焊盘区连接到管芯焊盘区;以及印刷电路板,连接到管芯配置焊盘区。
按照本发明的另一示范实施例,提供一种管芯配置,它包括:管芯;管芯的第一侧,连接到金属板;管芯周围的成型材料,至少部分暴露出金属板;管芯的第二侧,与管芯的第一侧相对并包括在管芯活性侧上的管芯焊盘区;管芯配置焊盘区;管芯连接件,通过成型材料将管芯配置焊盘区连接到管芯焊盘区;以及印刷电路板,连接到管芯配置焊盘区。管芯连接件中的每个管芯连接件可由金属柱状凸点形成,柱状凸点包括第一部分凸点和第二部分凸点,第二部分凸点具有大于第一部分凸点的宽度。管芯配置连接件可位于第二部分凸点上。
按照本发明的另一示范实施例,提供一种管芯配置,它包括管芯、管芯周围的成型材料、包括管芯焊盘区的管芯的一侧、管芯配置焊盘区、通过成型材料将管芯配置焊盘区连接到管芯焊盘区的管芯连接件。管芯连接件中的每个管芯连接件可由凸点形成,凸点包括第一部分凸点和第二部分凸点,第二部分凸点具有大于第一部分凸点的宽度。而且,管芯配置连接件可以提供并位于第二部分凸点上。按照本发明的另一示范实施例,提供一种制造管芯配置的方法,包括将管芯的非活性侧连接到热沉,管芯的非活性侧与管芯的活性侧相对。
将管芯的非活性侧连接到热沉还可包括在管芯的非活性侧上淀积热界面材料,并将热沉连接到热界面材料。
在本发明的示范实施例中,该方法还包括在位于管芯活性侧上的管芯焊盘区上形成管芯连接件。
在本发明的示范实施例中,将管芯的非活性侧连接到热沉包括将管芯的非活性侧连接到金属板。
在本发明的示范实施例中,在管芯焊盘区上形成管芯连接件是使用至少一个光刻工艺来完成的。光刻工艺可用来定义要制造的凸点的截面宽度。
在本发明的示范实施例中,在管芯焊盘区上形成管芯连接件还包括形成第一部分连接件以及在第一部分连接件上形成第二部分连接件。
而且,在该方法的一种配置中,在管芯焊盘区上形成管芯连接件还包括形成第一部分连接件以及在第一部分连接件上形成第二部分连接件,第二部分连接件具有大于第一部分连接件的宽度。
按照本发明的另一实施例,在管芯焊盘区上形成管芯连接件还包括使用第一光刻工艺形成第一部分连接件,以及使用第二光刻工艺形成第二部分连接件。
而且,在管芯焊盘区上形成管芯连接件可使用至少一个金属电镀工艺来完成。
按照本发明的另一实施例,在管芯焊盘区上形成管芯连接件还包括电镀使用第一光刻工艺在管芯的管芯焊盘区上形成的第一部分连接件,以及电镀使用第二光刻工艺在第一部分连接件上形成的第二部分连接件。
而且,管芯可从其它管芯切割下来(换句话说,与其分离)。
此外,可将管芯或多个管芯附到热沉上,例如附到金属板上,在此情况下它也用作管芯的载体。
该方法还可包括成型被附到热沉上的管芯,至少部分暴露出管芯连接件。
管芯的成型可使用带式成型工艺完成。
按照本发明另一示范实施例,该方法还包括将管芯配置连接件,诸如焊料凸点,安装在管芯连接件上。
按照本发明另一示范实施例,该方法还包括将管芯配置连接件耦合到印刷电路板上。
按照本发明的另一示范实施例,提供一种制造管芯配置的方法,包括通过在管芯的活性侧上形成第一部分连接件以及在已形成的第一部分连接件上形成第二部分连接件,来在位于管芯活性侧上的管芯焊盘区上形成管芯连接件,第二部分连接件具有大于第一部分连接件的宽度。
按照本发明的另一示范实施例,在管芯焊盘区上形成管芯连接件还包括电镀使用第一光刻工艺在管芯的管芯焊盘区上形成的第一部分连接件,以及电镀使用第二光刻工艺在第一部分连接件上形成的第二部分连接件。
图1示出按照本发明示范实施例的管芯配置100的截面图。
管芯配置100具有管芯102,也称为芯片102。管芯102具有多个电子元件(未示出),例如电阻器、电容器、电感器、晶体管、任何类型的存储器单元(随机存取存储器或只读存储器)等等,都单片集成在其中。管芯102可以是逻辑芯片、存储器芯片或微处理器芯片。在本发明另一实施例中,管芯102可以是混合芯片,包括逻辑元件以及存储器元件(例如可包括嵌入式存储器)。
在管芯102的活性侧104上,设置有管芯焊盘106,它们与管芯102中的电子元件耦合。管芯焊盘106用作管芯外部电连接。
而且,用导电材料例如由诸如铜或铝等金属或任何其它适用材料制成的柱状凸点108被布置在管芯焊盘106的暴露表面上。如以下详述的,柱状凸点108可具有任何形状,例如多边形截面形状,在备选实施例中,可以是圆形截面形状。
在本发明的一个实施例中,提供一个柱状凸点108用于并连接到一个相应的管芯焊盘106。
在本发明的一个实施例中,每个柱状凸点108具有两部分柱状凸点:第一部分柱状凸点110和第二部分柱状凸点112。第一部分柱状凸点110分别连接到暴露的管芯焊盘106。如以下详述的,第一部分柱状凸点110其截面具有第一形状,且第二部分柱状凸点112其截面具有第二形状。第一形状和第二形状可具有同一形状,但第一形状和第二形状也可具有不同形状。在本发明的此示范实施例中,第一形状是多边形,例如六边形,而第二形状是圆形。
在管芯102的非活性侧114上,它与管芯102的活性侧104相对,提供有可选的热界面材料层116。在本发明的示范实施例中,这层覆盖了管芯102的非活性侧114的整个表面。在一个实施例中,热界面材料可以是热焊盘(例如相变材料)、热粘合剂或热滑脂。举例来说,加固的或基于泡沫的导热固化硅酮胶可用作热界面材料116。
与管芯102相对的热界面材料层116的表面附到金属板118。
成型材料120提供在管芯102的三个侧面上,从而包封了管芯102,但金属板118和第二部分柱状凸点112的上表面除外,它们保持暴露,供与印刷电路板或另一所需外部装置连接。
由无铅焊料材料(例如由Sn或Sn合金)制成的球栅阵列焊料凸点122形成在第二部分柱状凸点112的暴露表面上,用于焊料连接印刷电路板124或另一所需外部装置。
图2示出按照本发明另一示范实施例的管芯配置200的截面图。
管芯配置200类似于图1中所示的管芯配置100,其区别在于,在图2的管芯配置200中省略了热界面材料层116。因此,按照管芯配置200,金属板118直接连接到管芯102的非活性侧114。
图3A-3S示出按照本发明示范实施例的管芯配置在其制造的不同时间瞬间的截面视图。
现参阅图3A,经前端工序处理的来料圆片300包括圆片衬底302、多个电子元件(未示出)、在圆片衬底302活性侧上的钝化层304以及管芯焊盘306,用作所描述的封装后端工序处理的起始点。圆片衬底302由半导体材料制成,虽然在本发明另一实施例中,也可使用其它适合的材料,如聚合物。在本发明的示范实施例中,圆片衬底302由硅制成(掺杂或未掺杂的)。在本发明的备选实施例中,圆片衬底302是绝缘体上外延硅(SOI)圆片。作为备选方案,任何其它适合的半导体材料都可用作圆片衬底302,例如半导体化合物材料,诸如砷化钾(GaAs)、硅锗(SiGe)、磷化铟(InP),但也可使用任何适合的三元半导体化合物材料或四元半导体化合物材料,诸如铟镓砷(InGaAs)。
如图3A所示,第一管芯区308(图3A的左手侧)和第二管芯区310(图3A的右手侧)示为分别用于制造第一管芯和第二管芯。
随后,利用UBM溅射,将凸点下金属化(UBM)材料314施加在钝化层304的整个暴露表面上以及暴露的管芯焊盘306上(见图3B中的结构312)。
如图3C中的结构316所示,利用旋涂或任何其它适合的工艺,将第一光刻胶层318施加到UBM材料314上。
用光刻工艺,使用第一光刻掩模(未示出)将第一光刻胶层318曝光。对曝光区或未曝光区进行蚀刻(视使用的是正性第一光刻胶材料还是负性第一光刻胶材料而定),从而形成作有图案的第一光刻胶层322(见图3D中的结构320)。
利用电镀或利用无电镀,用金属例如用铜填充因形成图案而在第一光刻胶层318中形成的孔324,从而形成第一部分柱状凸点328(见图3E中的结构326)。换句话说,进行第一电镀工艺以便制造第一部分柱状凸点328。
在下一步骤,剥离作有图案的第一光刻胶层322,从而暴露出第一部分柱状凸点328,它们现在是UBM材料上的明显独立式结构,且布置在相应管芯焊盘306之上(见图3F中的结构330)。
如图3G所示,利用湿蚀刻或干蚀刻对UBM材料314进行蚀刻(各向异性或各向同性),以使第一部分柱状凸点328彼此电隔离。但有些UBM材料314保留在第一部分柱状凸点328之下,以便分别使每个第一部分柱状凸点328与相应分配的管芯焊盘306电连接(见图3G中的结构332)。
如图3H中的结构334所示,利用旋涂或任何其它适合工艺,将第二光刻胶层336施加到暴露的钝化层304和整个第一部分柱状凸点328上。
用光刻工艺,使用第二光刻掩模(未示出)使第二光刻胶层336曝光。对曝光区或未曝光区进行蚀刻(视使用的是正性第二光刻胶材料还是负性第二光刻胶材料而定),从而形成作有图案的第二光刻胶层340(见图3I中的结构338)。
利用电镀或利用无电镀,用金属例如用铜填充因形成图案并曝光第一部分柱状凸点328的上表面而在第二光刻胶层336中形成的孔342,从而形成第二部分柱状凸点346(见图3J中的结构344)。换句话说,进行第二电镀工艺以便制造第二部分柱状凸点346。第二部分柱状凸点346具有大于第一部分柱状凸点328的截面(或直径)。因此,由第一部分柱状凸点328和第二部分柱状凸点346形成的柱状凸点具有T形。
在下一步骤,剥离形成图案的第二光刻胶层340,从而暴露出第一部分柱状凸点328和第二部分柱状凸点346,它们现在是UBM材料上的明显独立式结构(例如独立式的T结构),且布置在相应管芯焊盘306之上(见图3K中的结构348)。
如图3L中的结构350所示,例如利用背面研磨使圆片衬底302变薄,从而产生变薄的圆片结构350。
接下来,进行圆片切割工艺,从而将变薄的圆片结构350分成多个管芯354和356(见图3M中的管芯布置352)。圆片切割工艺可以是任何适合的工艺,包括锯、蚀刻或断开变薄的圆片结构350。
将热界面材料层360施加到现已分离的管芯354和356的非活性侧362上,并使分离的管芯354和356附到金属板364上(见图3N中的管芯布置358)。
在下一步骤,进行管芯附连固化工艺,从而固化用于管芯附连的材料(见图3O中的管芯布置366)。
如图4和5所示,图5是图4中部分A的放大截面视图,金属板364提供一个格栅,其中在金属板364中的格栅图案中提供有多条蚀刻划线402。
图6示出图4中部分B的放大截面视图,并示出图3O中管芯布置366的一个管芯。
如图7所示,由相应第一部分柱状凸点328和相应第二部分柱状凸点346形成的每个柱状凸点700都具有T形。第一部分柱状凸点328为具有正六边形截面的圆柱形状,其中正六边形的直径大于约50μm,例如大于约80μm。第二部分柱状凸点346为具有圆形截面的圆柱形状,其中圆形基底的直径大于第一部分柱状凸点328的截面直径。举例来说,圆形基底的直径大于约200μm,例如大于约250μm。而且,第一部分柱状凸点328具有的厚度大约至少为20μm,例如大约至少为50μm。第二部分柱状凸点346具有的厚度大约至少为10μm,例如大约至少为20μm(见图8中的截面图800)。
现参阅图3P中的管芯布置368,使用带式成型工艺对附连的管芯354和356成型。换句话说,将附连的管芯354和356放在成型单元370中,并用带子372覆盖第二部分柱状凸点346的上表面。然后,将成型材料374诸如环氧树脂注入成型单元370中,从而使成型单元370的整个中空空间填充有成型材料374。
应指出,在图3P、图3Q和图3R中,管芯354和356以简化形式示出,即,没有钝化层304和UBM材料314。
在注入成型工艺已经完成之后,从成型单元370中取出成型的附连管芯354和356,并对这样形成的封装进一步处理,如图3Q所示。
在下一步骤中,将球栅阵列焊球378安装在铜焊盘380上,即,第二部分柱状凸点346暴露的上表面上,它们是由于在注入成型工艺期间使用带子而暴露出的(见图3Q中的管芯布置376)。
在已经将球栅阵列焊球378安装在铜焊盘380上之后,利用封装切割工艺(例如利用锯或蚀刻或断开封装)将封装分离,从而形成封装的管芯384和386(见图3R中的管芯布置382)。
封装的管芯384和386具有和图1所示管芯配置100相同的结构。
接下来,利用BGA焊球378将封装的管芯384和386安装在印刷电路板388上(见图3S中的管芯布置390)。
图2中所示的制造管芯配置200的过程类似于参阅图3A到3S所述的过程,但形成热界面材料的步骤被省略了。
在本发明示范实施例中,封装的管芯是圆片级封装(WLP)管芯。
在本发明的示范实施例中,铜柱状凸点形成法用作芯片(管芯)和印刷电路板的互连方法。按照本发明示范实施例所使用的铜柱状凸点分两步电镀。第一步用来生长主要的互连立柱(例如其直径大于约50μm),且第二步用来扩大立柱的末端,以允许正常的焊球附连(例如焊盘直径大于约250μm)。然后通过预组装诸如背面研磨和切割,对有凸点的圆片进行处理。使用可选的热界面材料使切割的芯片然后附到蚀刻的金属板上,随后进行固化。金属板将通过组装过程暂时用作芯片载体,并最终将用作封装的热沉。利用带式成型对带有附连芯片的金属板进行处理,以允许焊盘区域被暴露出来用于随后的BGA焊料附连。进一步的处理步骤类似于正常的BGA封装工艺。
上述说明是为了图示和说明的目的而提供的。并不旨在是详尽无遗的,或是将本发明限制在所公开的准确形式,而且根据所公开的示教显然可以有许多修改和变化。所述实施例的选择是为了最好地解释本发明的原理及其实际应用,从而使所属领域的技术人员能在各种实施例中最好地利用本发明,并具有适合于设想的特定用途的各种修改。旨在本发明的范围由所附权利要求书定义。
Claims (36)
1.一种管芯配置,包括:
管芯;
所述管芯周围的成型材料;
所述管芯的一侧,包括管芯焊盘区;
管芯配置焊盘区;
管芯连接件,通过所述成型材料将所述管芯配置焊盘区连接到所述管芯焊盘区,所述管芯连接件中的每个管芯连接件由凸点形成,所述凸点包括第一部分凸点和第二部分凸点,第二部分凸点具有不同于第一部分凸点的宽度;以及
管芯配置连接件,位于第二部分凸点上。
2.如权利要求1所述的管芯配置,其中所述管芯具有活性侧以及与所述活性侧相对的非活性侧,所述管芯配置还包括耦合到所述非活性侧的热沉。
3.如权利要求2所述的管芯配置,其中所述热沉包括金属板。
4.如权利要求1所述的管芯配置,其中所述管芯配置连接件包括焊料件。
5.如权利要求4所述的管芯配置,其中所述焊料件包括球栅阵列焊料凸点。
6.如权利要求4所述的管芯配置,其中所述焊料件包括无铅焊料件。
7.如权利要求1所述的管芯配置,其中所述管芯焊盘区电耦合到所述管芯的电子元件。
8.如权利要求1所述的管芯配置,其中所述凸点包括柱状凸点。
9.如权利要求1所述的管芯配置,其中所述凸点包括金属凸点。
10.如权利要求1所述的管芯配置,其中所述凸点包括铜凸点。
11.如权利要求1所述的管芯配置,其中第二部分凸点具有大于第一部分凸点的宽度。
12.一种制造管芯配置的方法,所述方法包括:
提供具有活性侧和非活性侧的管芯;
在所述管芯的所述活性侧上的管芯焊盘区上形成管芯连接件,所述管芯连接件通过在所述管芯的所述活性侧上形成第一部分连接件并在所形成的第一部分连接件上形成第二部分连接件而形成,第二部分连接件具有大于第一部分连接件的宽度。
13.如权利要求12所述的方法,其中在管芯焊盘区上形成管芯连接件使用至少一个金属电镀工艺完成。
14.如权利要求13所述的方法,其中在管芯焊盘区上形成所述管芯连接件还包括:
电镀使用第一光刻工艺在所述管芯的所述管芯焊盘区上形成的第一部分连接件;以及
电镀使用第二光刻工艺在第一部分连接件上形成的第二部分连接件。
15.如权利要求12所述的方法,还包括从其它管芯切割所述管芯。
16.如权利要求15所述的方法,还包括将所述管芯附到热沉上。
17.如权利要求16所述的方法,还包括成型附到所述热沉的所述管芯,从而至少部分暴露出所述管芯连接件。
18.如权利要求17所述的方法,其中成型所述管芯使用带式成型工艺完成。
19.如权利要求17所述的方法,还包括将管芯配置连接件安装在所述管芯连接件上。
20.如权利要求19所述的方法,其中将管芯配置连接件安装在所述管芯连接件上包括将焊料件安装在所述管芯连接件上。
21.如权利要求19所述的方法,还包括将所述管芯配置连接件耦合到印刷电路板。
22.如权利要求12所述的方法,还包括将热沉连接到所述管芯的所述非活性侧,所述管芯的所述非活性侧与所述管芯的活性侧相对。
23.一种管芯配置,包括:
管芯,具有活性侧以及与所述活性侧相对的非活性侧;
热界面材料层,在所述管芯的所述非活性侧上;以及
金属板,邻近所述管芯的所述非活性侧,所述热界面材料层在所述金属板和所述管芯之间。
24.如权利要求23所述的管芯配置,还包括耦合到所述管芯配置焊盘区的管芯配置连接件。
25.如权利要求24所述的管芯配置,其中所述管芯配置连接件包括焊料件。
26.如权利要求23所述的管芯配置,还包括:
所述管芯周围的成型材料,至少部分暴露出所述金属板;
所述管芯的所述活性侧上的管芯焊盘区;以及
管芯连接件,通过所述成型材料将所述管芯配置焊盘区连接到所述管芯焊盘区。
27.如权利要求23所述的管芯配置,还包括连接到所述管芯配置焊盘区的电路板。
28.如权利要求27所述的管芯配置,其中所述电路板包括印刷电路板。
29.一种管芯配置,包括:
管芯;
所述管芯的第一侧,连接到金属板;
所述管芯周围的成型材料,至少部分暴露出所述金属板;
所述管芯的第二侧,与所述管芯的第一侧相对并包括管芯焊盘区;
管芯配置焊盘区;
管芯连接件,通过所述成型材料将所述管芯配置焊盘区连接到所述管芯焊盘区,其中所述管芯连接件中的每个管芯连接件包括金属柱状凸点,所述柱状凸点包括第一部分凸点和第二部分凸点,第二部分凸点具有大于第一部分凸点的宽度;
印刷电路板,连接到所述管芯配置焊盘区;以及
管芯配置连接件,位于第二部分凸点上。
30.一种制造管芯配置的方法,所述方法包括:
将热界面材料淀积在管芯的非活性侧上,所述管芯的所述非活性侧与所述管芯的活性侧相对;以及
将金属板连接到所述热界面材料。
31.如权利要求30所述的方法,还包括在位于所述管芯的所述活性侧上的管芯焊盘区上形成管芯连接件。
32.如权利要求31所述的方法,其中在管芯焊盘区上形成所述管芯连接件包括执行至少一个光刻工艺。
33.如权利要求31所述的方法,其中在管芯焊盘区上形成所述管芯连接件还包括:
形成第一部分连接件;以及
在第一部分连接件上形成第二部分连接件。
34.如权利要求31所述的方法,其中:
在管芯焊盘区上形成所述管芯连接件还包括:
形成第一部分连接件;以及
在第一部分连接件上形成第二部分连接件,第二部分连接件具有大于第一部分连接件的宽度。
35.如权利要求34所述的方法,其中在管芯焊盘区上形成管芯连接件包括:
使用第一光刻工艺形成第一部分连接件;以及
使用第二光刻工艺形成第二部分连接件。
36.一种管芯配置,包括:
管芯,具有活性侧以及与所述活性侧相对的非活性侧;
热沉,内部耦合到所述管芯的所述非活性侧;以及
热界面材料,在所述管芯的所述非活性侧与所述热沉之间。
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7772691B2 (en) | 2007-10-12 | 2010-08-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermally enhanced wafer level package |
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Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100818101B1 (ko) * | 2006-11-08 | 2008-03-31 | 주식회사 하이닉스반도체 | 웨이퍼 레벨 칩 사이즈 패키지 |
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US8487435B2 (en) * | 2008-09-09 | 2013-07-16 | Triquint Semiconductor, Inc. | Sheet-molded chip-scale package |
US9355962B2 (en) * | 2009-06-12 | 2016-05-31 | Stats Chippac Ltd. | Integrated circuit package stacking system with redistribution and method of manufacture thereof |
US8383457B2 (en) | 2010-09-03 | 2013-02-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
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US8604600B2 (en) | 2011-12-30 | 2013-12-10 | Deca Technologies Inc. | Fully molded fan-out |
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US8264089B2 (en) * | 2010-03-17 | 2012-09-11 | Maxim Integrated Products, Inc. | Enhanced WLP for superior temp cycling, drop test and high current applications |
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US8421245B2 (en) * | 2010-12-22 | 2013-04-16 | Intel Corporation | Substrate with embedded stacked through-silicon via die |
US8525309B2 (en) * | 2011-06-30 | 2013-09-03 | Tessera, Inc. | Flip-chip QFN structure using etched lead frame |
US9386725B2 (en) | 2011-09-01 | 2016-07-05 | Hewlett-Packard Development Company, L.P. | Heat sinking |
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US9831170B2 (en) | 2011-12-30 | 2017-11-28 | Deca Technologies, Inc. | Fully molded miniaturized semiconductor module |
WO2013102146A1 (en) | 2011-12-30 | 2013-07-04 | Deca Technologies, Inc. | Die up fully molded fan-out wafer level packaging |
US10050004B2 (en) | 2015-11-20 | 2018-08-14 | Deca Technologies Inc. | Fully molded peripheral package on package device |
JP5979495B2 (ja) * | 2013-03-19 | 2016-08-24 | Shマテリアル株式会社 | 半導体素子搭載用基板の製造方法 |
US9269622B2 (en) | 2013-05-09 | 2016-02-23 | Deca Technologies Inc. | Semiconductor device and method of land grid array packaging with bussing lines |
US10037975B2 (en) | 2016-08-31 | 2018-07-31 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and a method of manufacturing the same |
US11244918B2 (en) | 2017-08-17 | 2022-02-08 | Semiconductor Components Industries, Llc | Molded semiconductor package and related methods |
CN109950214A (zh) * | 2017-12-20 | 2019-06-28 | 安世有限公司 | 芯片级封装半导体器件及其制造方法 |
US10593630B2 (en) | 2018-05-11 | 2020-03-17 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method for manufacturing the same |
US11056453B2 (en) | 2019-06-18 | 2021-07-06 | Deca Technologies Usa, Inc. | Stackable fully molded semiconductor structure with vertical interconnects |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5528462A (en) * | 1994-06-29 | 1996-06-18 | Pendse; Rajendra D. | Direct chip connection using demountable flip chip package |
US6326700B1 (en) | 2000-08-15 | 2001-12-04 | United Test Center, Inc. | Low profile semiconductor package and process for making the same |
US20030160319A1 (en) * | 2002-02-27 | 2003-08-28 | Wen-Chun Zheng | Solid assembly of flip-chip package attached to heat removal device and method of manufacturing same |
FR2853962B1 (fr) * | 2003-04-16 | 2006-06-16 | Snpe Materiaux Energetiques | Dispositif d'initiation electrique d'une micro-charge pyrotechnique et microsysteme utilisant un tel dispositif |
US7199466B2 (en) * | 2004-05-03 | 2007-04-03 | Intel Corporation | Package design using thermal linkage from die to printed circuit board |
US7290596B2 (en) * | 2004-10-20 | 2007-11-06 | University Of Maryland | Thermal management of systems having localized regions of elevated heat flux |
US7975377B2 (en) * | 2005-04-28 | 2011-07-12 | Stats Chippac Ltd. | Wafer scale heat slug system |
-
2006
- 2006-06-27 US US11/475,720 patent/US7476980B2/en active Active
-
2007
- 2007-06-27 CN CNA2007101290444A patent/CN101101900A/zh active Pending
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