CN101093800B - 制作多晶硅薄膜的方法 - Google Patents

制作多晶硅薄膜的方法 Download PDF

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CN101093800B
CN101093800B CN2007101106836A CN200710110683A CN101093800B CN 101093800 B CN101093800 B CN 101093800B CN 2007101106836 A CN2007101106836 A CN 2007101106836A CN 200710110683 A CN200710110683 A CN 200710110683A CN 101093800 B CN101093800 B CN 101093800B
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卡卡德·拉梅许
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TPO Displays Corp
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Abstract

一种制作多晶硅薄膜的方法。首先形成晶种层(seed layer)于基底的表面，然后形成硅层于该晶种层的表面。接着进行激光退火工艺，使该硅层转换为多晶硅层，且该激光退火工艺的能量大于或等于可完全融化该硅层的能量。

Description

制作多晶硅薄膜的方法
技术领域
本发明关于一种制作多晶硅薄膜的方法。
背景技术
由于液晶显示器其有外型轻薄、耗电量少以及无辐射污染等特性，故已被广泛地应用在笔记型电脑、个人数字助理(PDA)等携带式资讯产品上。然而随着使用者对于显示器视觉感受要求的提升，加上新技术应用领域不断的扩展，于是更高画质、高分辨率且具低价位的平面显示器变成未来显示技术发展的趋势，也造就了新的显示技术发的原动力，而低温多晶硅薄膜晶体管(low temperature polysilicon thin film transistor，LTPS TFT)除了具有符合有源驱动(actively drive)潮流的特性外，其技术是达成上述目标的一项重要技术突破。
请参照图1，图1为习知制作一低温多晶硅薄膜的示意图。如图1所示，首先提供一基底10，例如一由玻璃所构成的基底。然后形成一由氧化硅或氮化硅所构成的阻隔层12于基底10上，且阻隔层12具有一非晶体结构。接着形成一非晶硅(amorphous silicon)层14于阻隔层12上，并利用准分子激光对非晶硅层14进行一激光退火工艺16，使非晶硅层14产生一结晶化现象(crystallization)。
一般而言，在结晶化的过程中，非晶硅层14会经历融化与再生(regrowth)的步骤而形成一多晶硅层，且多晶硅层的晶粒尺寸会取决于激光退火工艺中的能量。举例来说，多晶硅层中的晶粒尺寸会随着激光能量的提升而增加，直到一足以完全融化该硅层的能量单位，且该能量单位通称为一完全融化临界点(full-melt threshold)。当激光能量到达或超过完全融化临界点时，多晶硅层中的晶粒便会再次缩小，进而形成微小结晶体(microcrystalline)的型态。此现象是由于当非晶硅层14在非晶体阻隔层12上成长时，在完全融化临界点下，晶核(nucleus)无法存活，且在后续进行冷却步骤时，许多微小的晶核会形成，进而形成许多微小的晶粒。因此，为了有效增加晶粒的尺寸与均匀性，习知于结晶化过程中必须将激光能量控制于完全融化临界点之下，而此范围下的激光能量，亦即所需的工艺范畴通常约为10mJ/cm2。然而，在这么小的工艺范畴下，习知制作多晶硅薄膜时，由于空间变异以及每次所进行的激光能量有变异，会造成硅晶体的品质不均且再现性不佳，且此现象将会使硅层中的晶粒无法达到所需的质量或产生分布不均的现象。
由于另一决定完全融化临界点的重要因素为硅层的厚度，因此，随着激光工艺间的变异量影响硅层的厚度，导致晶体品质不均匀。此外，习知制作多晶硅薄膜的另一缺点是需利用多道的激光脉冲对非晶硅层的各区域进行处理，以达到均匀的晶格分布。在一般状况下，使用者必须对非晶硅层进行至少20至40道的激光脉冲处理，以获得均匀的晶粒大小。然而，随着激光脉冲次数的增加，激光退火工艺的整体效率将无可避免的降低。
发明内容
因此本发明的主要目的是提供一种制作多晶硅薄膜的方法，以有效提升多晶硅薄膜的均匀性。
本发明揭露一种制作多晶硅薄膜的方法。首先形成晶种层(seed layer)于基底的表面，然后形成硅层于该晶种层的表面。接着进行激光退火工艺，使该硅层转换为多晶硅层，且该激光退火工艺的能量大于或等于可完全融化该硅层的能量。
本发明将一晶种层设置于非晶硅层与阻隔层之间，且该晶种层的晶格结构对应该非晶硅层的晶格结构。值得注意的是，本发明可藉由此晶种层来大幅提升激光能量的范围，亦即增加硅层进行结晶化过程中的工艺范畴，以有效降低形成均匀硅层所需注射的激光脉冲数量、提升产能、降低成本、以及改善后续多晶硅层的晶格特性与薄膜晶体管的性能。
附图说明
图1为习知制作一低温多晶硅薄膜的示意图；
图2为本发明优选实施例制作一多晶硅薄膜的示意图；
图3至图5为本发明制作一低温多晶硅薄膜晶体管的示意图；
图6为本发明一实施例的一液晶显示面板的示意图；
图7为本发明将液晶显示面板应用于一电子装置的方块示意图。
主要元件符号说明
10    基底                    12    阻隔层
14    非晶硅层                16    激光退火工艺
20    透明基底                22    阻隔层
24    晶种层                  26    非晶硅层
28    激光退火工艺            42    基底
43    有源区域                44    多晶硅层
46    栅极绝缘层              48    栅极
50    源极                    52    漏极
60    液晶显示面板            62    彩色滤光片
64    公共电极                66    上基板
68    多晶硅薄膜晶体管        70    像素电极
72    下基板                  76    液晶层
80    输入单元                90    电子装置
具体实施方式
请参照图2，图2为本发明优选实施例制作一多晶硅薄膜的示意图。如图2所示，首先提供一透明基底20，例如一由玻璃所构成的基底。然后形成一由氧化硅或氮化硅所构成的非晶体阻隔层22于透明基底20上。接着进行一溅镀(sputtering)工艺、原子层沉积(atomic layer deposition)工艺、蒸镀(evaporation)工艺或一化学气相沉积(CVD)工艺，以形成一具有结晶结构的晶种层24于阻隔层22上。随后再进行一化学气相沉积工艺或一溅镀工艺，以形成一非晶硅层26于晶种层24表面。
根据本发明的优选实施例，晶种层24的厚度介于500埃至5000埃，且晶种层24可具有结晶特性(crystallinity)以及一结晶结构。因此，藉由调整晶种层24的结晶特性与晶格排列方向(orientation)，使用者可有效控制后续多晶硅薄膜的结晶特性与晶格排列方向。其次，晶种层24的晶粒尺寸介于500埃至5000埃，且晶种层24的晶格结构可对应后续退火工艺中由非晶硅层26而形成的一多晶硅层的晶格结构。此外，晶种层24可由氧化铈(cerium oxide)、氟化钙(calcium fluoride)或氧化锆(zirconium oxide)所构成。
接着于沉积非晶硅层26后进行一激光退火工艺28，例如一准分子激光退火(excimer laser annealing)工艺或固态激光退火(solid-state laser annealing)工艺，使非晶硅层26产生一结晶化现象。一般而言，激光退火工艺的能量可大于或等于一可完全融化硅层的能量，如先前所述的完全融化临界点，且完全融化临界点的能量取决于硅层的厚度、激光的波长以及激光脉冲的范围等条件。根据本发明的一实施例，激光退火工艺的能量可介于250mJ/cm2至500mJ/cm2之间，且激光退火工艺可进行多次激光脉冲，例如二至十次的激光脉冲。举例来说，如本发明利用氯化氙(XeCl)脉冲激光对一厚度约500埃的硅层进行处理，则激光退火的能量一般会介于280mJ/cm2至350mJ/cm2之间。
理想情形下，在结晶化的过程中，晶格对应的晶种层24可作为一晶种材料，以促进非晶硅层26的生长。因此，随着激光退火工艺的能量超越完全融化临界点并到达可完全融化非晶硅层26的程度时，非晶硅层26便会随着晶格对应晶种层24的晶格结构而成长，进而转变为一多晶硅薄膜。
由于多晶硅薄膜的结晶特性由晶种层24所控制，因此激光能量密度以及薄膜厚度的变异性将不会对多晶硅薄膜的结晶特性有显著的影响。换句话说，本发明藉由晶种层24来控制晶粒的尺寸，以有效改善习知制作多晶硅薄膜易于激光能量大于完全融化临界点时产生微小结晶体的现象。
此外，根据本发明的实施例，由于多晶硅薄膜的晶粒尺寸取决于晶种层24的结晶特性，因此本发明方法可于减少激光次数的条件下形成大小均匀的晶粒。同时，根据本发明的一些实施例，本发明可增加产量，对于既定产量下，可减少激光器材的使用量，进而降低器材、设施与维修的成本。
其次，使用者又可藉由调整晶种层24的晶格特性与晶粒的晶格排列方向来控制所形成的多晶硅薄膜的晶格特性与晶粒的晶格排列方向，举例来说，使用者可沉积一具有高优势排列(highly preferred oriented)(111)的氧化铈(cerium oxide)层，而使后续形成一同样具有优势排列的硅层。
根据本发明的另一实施例，本发明又可将先前形成的多晶硅薄膜进行加工，以形成多个多晶硅薄膜晶体管。请参照图3至图5，图3至图5为本发明制作一低温多晶硅薄膜晶体管的示意图。如图3所示，首先提供一基底42，且基底42具有一多晶硅层44覆盖其上。其中，多晶硅层44由先前所述的方法所制作完成。然后进行一蚀刻工艺，以于多晶硅层44上形成多个有源区域43。如图4所示，接着沉积一由氧化硅或氮化硅所构成的栅极绝缘层46于多晶硅层44表面，并形成一由钨或铬所组成的金属层(图未示)于栅极绝缘层46上。随后形成一图案化光阻层(图未示)于该金属层上，并进行一蚀刻工艺，例如一干蚀刻工艺，将图案化光阻层作为一掩模，以蚀刻部分该金属层并于多晶硅层44上形成一栅极48。然后如图5所示，移除该图案化光阻层，将栅极48作为一掩模并进行一离子注入工艺，以于多晶硅层44的有源区域43中形成一源极50与漏极52，进而完成一低温多晶硅薄膜晶体管68的制作。
根据本发明的另一实施例，本发明又可将先前所制作的低温多晶硅薄膜晶体管应用于一显示面板，例如一液晶显示面板或一有机发光二极体面板上。请参照图6，图6为本发明一实施例的一液晶显示面板60的示意图。如图6所示，本发明的液晶显示面板60包含有一彩色滤光片62以及一公共电极64设置于一上基板66的下表面、一薄膜晶体管68以及一像素电极70设置于一下基板72上以及一液晶层76设于上基板66与下基板72之间。值得注意的是，薄膜晶体管68是经由先前实施例的方法所制作完成。
根据本发明的又一实施例，本发明又可将液晶显示面板60应用于一电子装置中。请参照图7，图7为本发明将液晶显示面板60应用于一电子装置90的方块示意图。其中，电子装置90可为一个人数字助理(PDA)、数码相机、笔记型电脑、手持式电脑、行动电话、或DVD播放器等可携式电子产品。电子装置90包含有液晶显示面板60及一输入单元80。其中，输入单元80耦合液晶显示面板60并提供液晶显示面板60所需的输入信号(例如一图像信号)，进而使液晶显示面板显示画面。
综上所述，本发明将一额外的晶种层设置于非晶硅层与阻隔层之间，且该晶种层的晶格结构对应多晶硅层的晶格结构。本发明可藉由此晶种层来大幅提升激光能量的范围，亦即增加硅层进行结晶化过程中的工艺范畴，以有效降低形成均匀硅层所需注射的激光脉冲数量、提升产能、降低成本、以及改善后续多晶硅层的晶格特性与薄膜晶体管的性能。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (9)

1.一种制作多晶硅薄膜的方法，包含有：
形成晶种层于基底的表面；
形成硅层于该晶种层的表面；以及
进行激光退火工艺，使该硅层转换为多晶硅层，且该激光退火工艺的能量大于或等于可完全融化该硅层的能量，
其中该晶种层包含有氧化铈、氟化钙或氧化锆。
2.如权利要求1所述的方法，其中该硅层包含非晶硅。
3.如权利要求1所述的方法，其中该晶种层的厚度介于500埃至5000埃。
4.如权利要求1所述的方法，其中该晶种层包含有结晶结构。
5.如权利要求4所述的方法，其中该晶种层的晶格结构对应该多晶硅层的晶格结构。
6.如权利要求4所述的方法，其中该晶种层的晶粒尺寸介于500埃至5000埃。
7.如权利要求1所述的方法，其中该激光退火工艺的能量介于250mJ/cm2至500mJ/cm2之间。
8.如权利要求1所述的方法，其中进行该激光退火工艺的步骤包含有进行多次激光脉冲。
9.如权利要求8所述的方法，其中该激光退火工艺包含有进行二至十次激光脉冲。
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Publication number Priority date Publication date Assignee Title
US7914619B2 (en) * 2008-11-03 2011-03-29 International Business Machines Corporation Thick epitaxial silicon by grain reorientation annealing and applications thereof
JP2012004542A (ja) * 2010-05-20 2012-01-05 Tokyo Electron Ltd シリコン膜の形成方法およびその形成装置
JP5864360B2 (ja) * 2011-06-30 2016-02-17 東京エレクトロン株式会社 シリコン膜の形成方法およびその形成装置
DE102012102305A1 (de) * 2012-03-19 2013-09-19 Osram Opto Semiconductors Gmbh Laserdiodenvorrichtung
CN102856173B (zh) * 2012-09-29 2015-03-18 京东方科技集团股份有限公司 一种多晶硅薄膜及其制备方法、阵列基板、显示装置
CN109801973B (zh) * 2018-09-25 2021-01-26 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、阵列基板及显示装置
CN111987182A (zh) * 2020-08-27 2020-11-24 上海理想万里晖薄膜设备有限公司 TOPCon太阳能电池及其制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11354444A (ja) 1998-06-04 1999-12-24 Toshiba Corp 多結晶半導体膜の製造方法
TWI269922B (en) 2002-03-07 2007-01-01 Tpo Displays Corp Manufacturing method of LCD screen
TW540172B (en) 2002-07-25 2003-07-01 Toppoly Optoelectronics Corp Method of fabricating polysilicon film by excimer laser annealing process
TW564489B (en) 2002-07-25 2003-12-01 Toppoly Optoelectronics Corp Method for improving contact hole patterning
TWI234030B (en) 2002-09-03 2005-06-11 Toppoly Optoelectronics Corp Liquid crystal display device integrated with driving circuit and method for fabrication the same
TW554444B (en) 2002-09-03 2003-09-21 Toppoly Optoelectronics Corp Manufacturing method for liquid crystal display
TW565944B (en) 2002-10-09 2003-12-11 Toppoly Optoelectronics Corp Method of forming a low temperature polysilicon thin film transistor
TW586144B (en) 2002-11-15 2004-05-01 Toppoly Optoelectronics Corp Method of forming a liquid crystal display
TWI305681B (en) 2002-11-22 2009-01-21 Toppoly Optoelectronics Corp Method for fabricating thin film transistor array and driving circuits
US20060121742A1 (en) * 2004-12-07 2006-06-08 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
TWI260747B (en) * 2005-08-24 2006-08-21 Quanta Display Inc A method for forming a thin film transistor, and a method for transforming an amorphous layer into a poly crystal layer of a single crystal layer
TWI262550B (en) * 2005-10-14 2006-09-21 Ind Tech Res Inst Element with a low temperature poly-Si film, method of direct poly-Si deposition at low temperature and inductively-coupled plasma chemical vapor deposition

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开平11-354444A 1999.12.24

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