CN101057326A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN101057326A
CN101057326A CNA2004800443945A CN200480044394A CN101057326A CN 101057326 A CN101057326 A CN 101057326A CN A2004800443945 A CNA2004800443945 A CN A2004800443945A CN 200480044394 A CN200480044394 A CN 200480044394A CN 101057326 A CN101057326 A CN 101057326A
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semiconductor element
integrated capacitor
terminal
thermal component
current potential
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十和人
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Fujitsu Semiconductor Ltd
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Fujitsu Ltd
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Abstract

半导体器件包括：衬底；半导体元件，其装载在衬底上；散热部件，其覆盖半导体元件而安装在衬底上；封装树脂，其覆盖半导体元件。集成电容器与半导体元件相对置而安装在散热部件上，而且与半导体元件电连接。集成电容器的端子与半导体元件的端子以最短距离连接。并且，散热部件包括通过绝缘层被分离的第一金属板和第二金属板，集成电容器的一部分端子通过第一金属板连接至衬底的对应端子，集成电容器的另一部分端子通过第二金属板连接至衬底的对应端子。由此，能够抑制因追加电容器所导致的电感的增加。

Description

半导体器件
技术领域
本发明涉及一种具有用于稳定电源的电容器以及散热部件的半导体器件。
背景技术
在衬底上装载半导体元件并进行树脂封装的半导体器件，例如被称为BGA或PBGA。并且，提出有如下的提案：设置有覆盖半导体元件的散热部件(散热板)，半导体元件产生的热量经由散热部件而排出到半导体器件的外部(例如，参照JP特开2000-77575号公报、实用新型注册第3074779号公报)。
并且，在半导体器件中，为了稳定电源电位而设置有多个电容器。到目前为止，多个电容器分别独立地设置在衬底的上表面或下表面，因此存在如下的问题：半导体元件与电容器之间的距离变长而导致电感变大。最近，随着半导体器件动作的高速化，半导体器件的电源线以及地线上的电感已成为问题。
发明内容
本发明的目的在于，提供一种半导体器件，该半导体器件为了稳定电源而追加了电容器，进而能够抑制因追加电容器而导致的电感的增加。
本发明提供一种半导体器件，其特征在于，具有：衬底；半导体元件，其装载在该衬底上；散热部件，其覆盖该半导体元件而安装在该衬底上；集成电容器，其与该半导体元件相对置而安装在该散热部件上，而且与该半导体元件电连接；封装树脂，其覆盖该半导体元件。
若采用该结构，则将多个电容器集中设置在一张衬底上而作为集成电容器，并且将集成电容器与半导体元件相对置而装载在散热部件上。集成电容器与半导体元件电连接。因此，集成电容器与半导体元件通过最短距离实现电连接，并且集合电容器将散热部件作为导通路径而与安装衬底电连接，因此能够降低由于安装集成电容器而导致的电感的影响。另外，由多个电容器构成集成电容器，因此稳定电源的效果也很好。另外，在制造过程中，只要将一个集成电容器安装在散热部件上即可，所以也能够降低成本。
附图说明
图1是表示本发明的第一实施例的半导体器件的剖视图。
图2是表示图1的集成电容器的俯视图。
图3是表示形成图1的散热部件的第一导体层的第一金属板的俯视图。
图4是表示沿着图3的IV-IV线剖切的第一金属板的剖视图。
图5是表示形成图1的散热部件的第二导体层的第二金属板的俯视图。
图6是表示沿着图5的VI-VI线剖切的第二金属板的剖视图。
图7是表示形成粘贴有绝缘胶带的图3的第一导体层的金属板的仰视图。
图8是表示沿着图7的VIII-VIII线剖切的第一金属板的剖视图。
图9是表示通过绝缘胶带被粘合的第一以及第二金属板的仰视图。
图10是表示沿着图9的X-X线剖切的第一以及第二金属板的剖视图。
图11是表示装载有集成电容器的第一以及第二金属板的仰视图。
图12是表示沿着图11的XII-XII线剖切的第一以及第二金属板的剖视图。
图13是表示沿着图11的XIII-XIII线剖切的第一以及第二金属板的剖视图。
图14是表示在图1的半导体器件的制造过程中装载有半导体元件的衬底的剖视图。
图15是表示在图1的半导体器件的制造过程中装载有集成电容器的散热部件的剖视图。
图16是表示本发明的其他实施例的半导体器件的剖视图。
最佳实施方式
下面，参照附图，针对本发明的实施例进行说明。
图1是表示本发明的半导体器件的剖视图。半导体器件10由以下部分构成：衬底12；半导体元件(半导体芯片)14，其装载在衬底12上；散热部件16，其覆盖半导体元件14而安装在衬底上；集成电容器18，其与半导体元件14相对置而安装在散热部件16上，而且与半导体元件14电连接；封装树脂20，其覆盖半导体元件14。封装树脂20局部地覆盖散热部件16。位于半导体元件14上方的散热部件16的中央部分，从封装树脂20露出到外部，而散热部件16的周边部分位于封装树脂20的内部。
衬底12由多层电路衬底构成，具有由未图示的导体所形成的电路图案。衬底12在其上表面侧具有信号端子22、接地端子24、处于规定的电位电平(电源电位)的电位端子26，在其下表面侧具有锡球等外部端子28。
半导体元件14通过芯片焊接材料30被固定在衬底12上。半导体元件14具有设置在半导体元件14的周边部的多个信号端子32、和设置在半导体元件14的中央部的一组接地端子34以及电位端子36。半导体元件14的信号端子32通过导线(接合线)38而连接至衬底12的信号端子22。半导体元件14也可以在半导体元件14的周边部具有接地端子以及电位端子，使它们与信号端子32混在一起，而且，这种半导体元件14的接地端子以及电位端子通过导线连接至衬底12的未图示接地端子以及电位端子。
图2是表示图1的集成电容器18的俯视图。对于集成电容器18以及相关的导线等来说，图1是图2的沿着I-I线剖开的剖视图(也相当于图13的剖视图)。集成电容器18是将多个电容器集成在硅衬底上而成的。电容器例如发挥旁路电容器的作用。集成电容器18的表面设置有分别与多个电容器连接的多个接地端子以及多个电位端子。在图2中涂黑表示的端子为接地端子，以空白表示的端子为电位端子。
在集成电容器18的中央部具有多个第一接地端子40以及多个第一电位端子42，在集成电容器18的周边部具有多个第二接地端子44以及多个第二电位端子46。集成电容器18例如包括10～20个电容器。在图示的例子中，集成电容器18包括8个电容器。各电容器具有两个电极，各电容器的一个电极，与一个第一接地端子40以及一个第二接地端子44连接，而且，各电容器的另一个电极，与第一电位端子42以及第二电位端子46连接。
第一接地端子40以及第一电位端子42通过导电性粘合部件48、50连接至半导体元件14的接地端子34以及电位端子36。导电性粘合部件48、50例如可以是凸点(Stud Bump)、导线以及导电膏等的单个或其组合。第二接地端子44以及第二电位端子46通过散热部件16连接至衬底12的接地端子24以及电位端子26。
散热部件16由形成第一导体层的铜等第一金属板52、形成第二导体层的第二金属板54构成。第一以及第二金属板52、54通过聚酰亚胺或环氧树脂等绝缘胶带(双面胶带)56相互粘合在一起，而且在电学上处于互相分离的状态。第一以及第二金属板52、54均都形成为覆盖集成电容器18的形状。第一金属板52位于比第二金属板54更远离半导体元件14的一侧(外侧)。
图3至图13表示散热部件16的第一金属板52以及第二金属板54。图3以及图4表示散热部件16的第一金属板52。第一金属板52具有：大致平坦的中央部分52A；大致平坦的环状部分52C，其通过台阶部52B连接至中央部分52A的外侧；伸出部分52E，其通过台阶部52D连接至环状部分52C的各边。第一金属板52在台阶部52B的四个角部具有狭槽58。
图5以及图6表示散热部件16的第二金属板54。第二金属板54具有：大致平坦的中央部分54A；大致平坦的环状部分54C，其通过台阶部54B连接至中央部分54A的外侧。第二金属板54在台阶部52B的四个角部具有狭槽60。并且，第二金属板54在中央部分54A具有矩形的开口部62。
图7以及图8表示粘贴有绝缘胶带56的第一金属板52。图7表示第一金属板52的内表面侧，一条矩形环状的绝缘胶带56粘贴在第一金属板52的环状部分52C上，而且一对带状的绝缘胶带56粘贴在第一金属板52的中央部分52A上。
图9以及图10表示通过绝缘胶带56粘合的第一以及第二金属板52、54。在图7以及图8所示的第一金属板52上配置第二金属板54，并施加压力，则能够通过绝缘胶带56将第一以及第二金属板52、54相互粘合在一起。图9是从第二金属板54的内表面侧观察被粘合的第一以及第二金属板52、54的图。当第一以及第二金属板52、54相互被粘合在一起时，使图7所示的一对带状的绝缘胶带56位于第二金属板54的开口部62的两侧。
第一金属板52的狭槽58与第二金属板54的狭槽60以相互连通的方式配置，因此，在进行树脂封装而形成封装树脂20时，能够使熔融树脂从散热部件16的外部通畅地流入散热部件16的内部，从而提高填充树脂的性能。
图11至图13表示装载有集成电容器18的第一以及第二金属板52、54。图11是从第二金属板54的内表面侧观察被粘合的第一以及第二金属板52、54的图。同时一起参照图1，集成电容器18通过第二金属板54的开口部62，并通过导电膏等导电性粘合材料被固定在第一金属板52的中央部分52A。
如图2所示，集成电容器18具有位于中央部的多个第一接地端子40以及多个第一电位端子42、还有位于周边部的多个第二接地端子44以及多个第二电位端子46。在图11至图13中，省略图示了位于中央部的接地端子以及电位端子。位于周边部的多个第二接地端子44以及多个第二电位端子46以与图2同样的方式被配置。
如图11以及图12所示，集成电容器18的第二接地端子44通过导线(接合线)64连接至散热部件16的第一金属板52。如图11以及图13所示，集成电容器18的第二电位端子46通过导线(接合线)66连接至散热部件16的第二金属板54。在图1中，只表示了连接电位端子46与第二金属板54的导线66。
在图1中，散热部件16的第一金属板52通过导电性粘合部件68连接至衬底12的接地端子24，散热部件16的第二金属板54通过导电性粘合部件70连接至衬底12的电位端子26。因此，集成电容器18的第二接地端子44以及第二电位端子46通过导线64、66以及第一及第二金属板52、54连接至衬底12的接地端子24以及电位端子26。由于导线64、66相对短，所以电感小，而且第一以及第二金属板52、54的面积大，从而在第一以及第二金属板52、54的电压下降小。
若采用以上的结构，则将多个电容器集中设置在一张硅衬底上而作为集成电容器18，集成电容器18与半导体元件14相对置而装载在散热部件16上。集成电容器18与半导体元件14以最短距离实现电连接，从而能够使各电容器的电感下降。另外，由于集成多个电容器而构成集成电容器18，所以只要在散热部件16上安装一个集成电容器18即可，从而有利于制造成本的降低。
图14是表示在图1的半导体器件10的制造过程中装载有半导体元件14的衬底12的剖视图。图15是表示在图1的半导体器件10的制造过程中装载有集成电容器18的散热部件16的剖视图。例如通过图14以及图15所示的制造方法来制造图1所示的半导体器件10。
如图14所示，准备装载有半导体元件14的衬底12。在衬底12上形成有信号端子22、接地端子24、电位端子26、外部端子28。半导体元件14通过芯片焊接材料30被固定在衬底12上。在半导体元件14上形成有信号端子32、接地端子34、电位端子36。半导体元件14的信号端子32通过导线38连接至衬底12的信号端子22。在接地端子24以及电位端子26上涂敷或形成有导电膏等导电性粘合部件68、70。
如图15所示，准备装载有集成电容器18的散热部件16。散热部件16由作为第一导体层的第一金属板52、以及作为第二导体层的第二金属板54构成，而且上述第一金属板52和第二金属板54通过作为绝缘层的绝缘胶带56被分离。装载有集成电容器18的散热部件16是例如通过参照图3至图13所说明的方式制造的。第二金属板54在中央部具有开口部62，集成电容器18通过该开口部62而利用导电膏等导电性粘合材料被固定在第一金属板52上。
集成电容器18的第二接地端子44通过导线64连接至散热部件16的第一金属板52，第二电位端子46通过导线66连接至散热部件16的第二金属板54。在第一接地端子40以及第一电位端子42上涂敷或形成有导电性粘合部件48、50。
因此，在使图15所示的散热部件16倒立的状态下，向图14的衬底12按压散热部件16。集成电容器18的第一接地端子40以及第一电位端子42对应于半导体元件14的接地端子34以及电位端子36而被按压，从而通过导电性粘合部件48、50被固定。第一以及第二金属板52、54对应于衬底12的接地端子24以及电位端子26而被按压，从而通过导电性粘合部件68、70被固定。然后，用封装树脂20进行树脂成型，从而得到图1所示的半导体器件10。此外，也可以在进行树脂成型之后将外部端子28设置在衬底12上。
此外，在实施例中，虽然将导电性粘合部件48、50设置在集成电容器18上，但也可以将导电性粘合部件48、50设置在半导体元件14上。同样，虽然将导电性粘合部件68、70设置在衬底12上，但也可以将导电性粘合部件68、70设置在散热部件16的第一以及第二金属板52、54上。并且，虽然导电性粘合部件48、50、68、70可以采用导电膏，但也可以取代导电膏而采用通过金丝等球焊线制成的凸点。或者，这些导电性粘合部件可以采用导电膏等粘合材料和凸点的组合。
图16是表示本发明的其他实施例的半导体器件的剖视图。与图1的实施例同样，半导体器件10由以下部分构成：衬底12；半导体元件(半导体芯片)14，其装载在衬底12上；散热部件16，其覆盖半导体元件14而安装在衬底上；集成电容器18，其与半导体元件14相对置而安装在散热部件16上，而且与半导体元件14电连接；封装树脂20，其覆盖半导体元件14。封装树脂20局部地覆盖散热部件16。
衬底12由多层电路衬底构成，具有信号端子22、接地端子24、处于规定的电位电平(电源电位)的电位端子26、以及外部端子28。半导体元件14通过芯片焊接材料30被固定在衬底12上。半导体元件14具有设置在半导体元件14的周边部的信号端子32、和设置在半导体元件14的中央部的一组接地端子34以及电位端子36。半导体元件14的信号端子32通过导线38而与衬底12的信号端子22连接。如图2所示，集成电容器18具有多个第一接地端子40以及多个第一电位端子42、还有多个第二接地端子44以及多个第二电位端子46。
在该实施例中，导电性粘合部件由设置在半导体元件14上的锡凸点72、设置在集成电容器18上的环形导线74构成，其中，该导电性粘合部件将半导体元件14的接地端子34以及电位端子36连接至集成电容器18的第一接地端子40以及第一电位端子42。
图16的其他结构与图1所示的结构相同。即，第二接地端子44以及第二电位端子46通过散热部件16而与衬底12的接地端子24以及电位端子26连接。散热部件16由第一金属板52和第二金属板54构成，该第一以及第二金属板52、54通过绝缘胶带(双面胶带)56相互被粘合，而且在电学上处于互相分离的状态。装载有集成电容器18的散热部件16与图3至图13所示的部件相同。第一金属板52具有狭槽58，第二金属板54具有狭槽60以及开口部62。集成电容器18通过第二金属板54的开口部62，并利用导电膏等导电粘合材料被固定在第一金属板52上。第一以及第二金属板52、54的狭槽58、60为了实现如下目的而被设置：在形成封装树脂20时，使熔融树脂通畅地流入散热部件16的内部，从而提高填充树脂的性能。
工业上的可利用性
如上述说明，若采用本发明，则能够提供一种因追加用于稳定电源电位的电容器而导致的对电感的影响小的半导体器件。另外，由于多个电容器构成集成电容器，而且将散热部件作为导通路径而电连接至安装衬底上，因此对稳定电源电位的效果很好。另外，在制造过程中，也只要将一个集成电容器安装在散热部件上即可，所以有利于成本的降低。

Claims (10)

1.一种半导体器件，其特征在于，具有：
衬底；
半导体元件，其装载在该衬底上；
散热部件，其覆盖该半导体元件而安装在该衬底上；
集成电容器，其与该半导体元件相对置而安装在该散热部件上，而且与该半导体元件电连接；
封装树脂，其覆盖该半导体元件。
2.如权利要求1所述的半导体器件，其特征在于，
该集成电容器具有多个第一接地端子以及多个第一电位端子，
该集成电容器的第一接地端子连接至该半导体元件的接地端子，
该集成电容器的第一电位端子连接至该半导体元件的电位端子。
3.如权利要求2所述的半导体器件，其特征在于，
该集成电容器还具有多个第二接地端子以及多个第二电位端子，
该集成电容器的第二接地端子以及第二电位端子通过该散热部件连接至该衬底的接地端子以及电位端子。
4.如权利要求3所述的半导体器件，其特征在于，
该散热部件具有第一导体层以及第二导体层，而且上述第一导体层以及第二导体层被绝缘层分离，
该集成电容器的第二接地端子通过该散热部件的第一导体层连接至该衬底的接地端子，
该集成电容器的第二电位端子通过该散热部件的第二导体层连接至该衬底的电位端子。
5.如权利要求4所述的半导体器件，其特征在于，
该集成电容器通过导电性粘合部件安装在该散热部件的第一导体层上。
6.如权利要求5所述的半导体器件，其特征在于，
该集成电容器的第二接地端子通过第一导线连接至该散热部件的第一导体层，
该集成电容器的第二电位端子通过第二导线连接至该散热部件的第二导体层。
7.如权利要求6所述的半导体器件，其特征在于，
将该半导体元件的电位端子连接至该集成电容器的第一电位端子的导电性粘合部件、以及将该半导体元件的接地端子连接至该集成电容器的第一接地端子的导电性粘合部件，由设置在集成电容器的端子上的导线和设置在半导体元件的端子上的凸点构成。
8.如权利要求4所述的半导体器件，其特征在于，
该散热部件的第一及第二导体层分别由金属板构成，
该绝缘层由用于粘合两张金属板的绝缘胶带构成。
9.如权利要求4所述的半导体器件，其特征在于，
该散热部件的第一及第二导体层、以及该绝缘层，具有在进行树脂封装时用于填充树脂的狭槽。
10.如权利要求4所述的半导体器件，其特征在于，
该散热部件的第一导体层位于比该第二导体层更远离该半导体元件一侧，
该第二导体层具有安放该集成电容器的开口部，
该集成电容器通过第二导体层的开口部而被固定在第一导体层上。
CNA2004800443945A 2004-11-17 2004-11-17 半导体器件 Pending CN101057326A (zh)

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KR101187903B1 (ko) * 2007-07-09 2012-10-05 삼성테크윈 주식회사 리드 프레임 및 이를 구비한 반도체 패키지
JP5328145B2 (ja) * 2007-12-24 2013-10-30 ラピスセミコンダクタ株式会社 不揮発性メモリデバイス及びその製造方法
US8372502B2 (en) 2010-04-01 2013-02-12 Apple Inc. Structures for containing liquid materials and maintaining part alignment during assembly operations
US9266310B2 (en) 2011-12-16 2016-02-23 Apple Inc. Methods of joining device structures with adhesive
KR101546575B1 (ko) * 2013-08-12 2015-08-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US11588009B2 (en) * 2018-12-12 2023-02-21 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device having a lid configured as an enclosure and a capacitive structure and method of manufacturing a semiconductor device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002170920A (ja) * 2000-12-04 2002-06-14 Nec Eng Ltd フリップチップ装置
JP4422323B2 (ja) * 2000-12-15 2010-02-24 株式会社ルネサステクノロジ 半導体装置
JP2002329834A (ja) * 2001-05-07 2002-11-15 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置
JP2003332515A (ja) * 2002-05-09 2003-11-21 Sharp Corp 半導体集積回路装置およびその製造方法
JP3679786B2 (ja) * 2002-06-25 2005-08-03 松下電器産業株式会社 半導体装置の製造方法
US20040212080A1 (en) * 2003-04-22 2004-10-28 Kai-Chi Chen [chip package structure and process for fabricating the same]

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106328611A (zh) * 2016-10-21 2017-01-11 苏州日月新半导体有限公司 半导体封装构造及其制造方法
CN106328611B (zh) * 2016-10-21 2019-03-12 苏州日月新半导体有限公司 半导体封装构造及其制造方法

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