CN116487356A - 包括芯片-基板复合半导体装置的半导体封装 - Google Patents

包括芯片-基板复合半导体装置的半导体封装 Download PDF

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Publication number
CN116487356A
CN116487356A CN202310079223.0A CN202310079223A CN116487356A CN 116487356 A CN116487356 A CN 116487356A CN 202310079223 A CN202310079223 A CN 202310079223A CN 116487356 A CN116487356 A CN 116487356A
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China
Prior art keywords
high voltage
inorganic substrate
dielectric inorganic
semiconductor package
metal
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CN202310079223.0A
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English (en)
Inventor
C·法赫曼
B·A·格兰泽
A·里格勒尔
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Publication of CN116487356A publication Critical patent/CN116487356A/zh
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Abstract

本文公开了包括芯片‑基板复合半导体装置的半导体封装。一种高电压半导体封装包括半导体装置。半导体装置包括高电压半导体晶体管芯片，其包括前侧和背侧。低电压负载电极和控制电极设置在半导体晶体管芯片的前侧。高电压负载电极设置在半导体晶体管芯片的背侧。半导体封装还包括电介质无机基板。电介质无机基板包括贯穿电介质无机基板的第一金属结构的图案，其中，第一金属结构的图案连接到低电压负载电极以及贯穿电介质无机基板的至少一个第二金属结构，其中，第二金属结构连接到控制电极。半导体晶体管芯片的前侧通过晶圆接合连接被附接到电介质无机基板，并且电介质无机基板具有至少50μm的厚度。

Description

包括芯片-基板复合半导体装置的半导体封装
技术领域
本公开一般涉及半导体装置的领域，并且特别地，涉及封装半导体芯片的领域。
背景技术
半导体装置制造商正在不断努力提高其产品的性能，同时降低其制造成本。在半导体装置的制造中的对成本和装置性能敏感的领域是对半导体芯片进行封装。封装尤其涉及形成从芯片电极(管芯焊盘)到封装端子的电互连。互连技术应当提供对于半导体装置的高的电性能和热性能以及可靠性。
高电压(HV)半导体芯片的封装涉及多个特定问题。例如，芯片的高电压边缘是非常敏感的，并且在高电压边缘附近的任何改变可能对芯片的边缘终止产生不利影响。例如，在半导体芯片边缘与低电压端子元件(例如，源极端子元件或栅极端子元件)之间必须有相对大的距离，其跨越芯片边缘从而允许场线在芯片边缘与低电压端子元件之间的横向离开。
其他方面的目的在于成本有效的制造工艺和考虑到产品通用性和封装可安装性的消费者利益。
发明内容
根据本公开的方面，一种高电压半导体封装包括半导体装置。半导体装置包括高电压半导体晶体管芯片，其包括前侧和背侧。低电压负载电极和控制电极设置在半导体晶体管芯片的前侧。高电压负载电极设置在半导体晶体管芯片的背侧。半导体封装还包括电介质无机基板。电介质无机基板包括贯穿电介质无机基板的第一金属结构的图案，其中，第一金属结构的图案连接到低电压负载电极，以及贯穿电介质无机基板的至少一个第二金属结构，其中，第二金属结构连接到控制电极。半导体晶体管芯片的前侧通过晶圆接合连接被附接到电介质无机基板，并且电介质无机基板具有至少50μm的厚度。
附图说明
附图的元件不一定相对于彼此成比例。类似的附图标记指代对应的相似部分。除非各个图示的实施例的特征彼此排斥，否则它们可以组合，和/或如果没有被描述成必要的，则可以被选择性省略。在附图中描绘了实施例，并且在以下描述中示例性地详细描述了实施例。
图1是根据本公开的包括半导体芯片和电介质无机基板的示例性半导体装置的示意性横截面图。
图2A是沿图1中的线X-X的电介质无机基板的横截面图。
图2B是图1和图2A中的细节D的局部视图。
图3是根据本公开的包括半导体芯片和电介质无机基板的示例性引线框架封装的示意性横截面图。
图4是图3中的示例性引线框架的俯视图。
图5是示出了当图2A中的电介质无机基板位于引线框架之上时的横截面图的俯视图。
图6是根据本公开的半导体芯片和电介质无机基板的示例性的板上组件的示意性横截面图。
图7是根据本公开的包括半导体芯片和电介质无机基板的层合嵌入式芯片封装的示例的示意性横截面图。
图8是根据本公开的包括半导体芯片和电介质无机基板的层合嵌入式芯片封装的示例的示意性横截面图。
图9是包括多个堆叠的电介质无机基板层的电介质无机基板150的示意性横截面图。
图10A-图10L是示出了根据本公开的制造示例性半导体装置的示例性阶段的示意性横截面图。
具体实施方式
如本说明书中所使用的，术语“电连接”或“连接”或类似术语不意在表示元件直接接触在一起；可以在“电连接”或“连接”的元件之间分别提供中间元件。然而，根据本公开，以上提及的和类似的术语可以可选地也具有元件直接接触在一起的特定含义，即，在“电连接”或“连接”的元件之间分别不提供中间元件。
此外，关于形成或位于表面“之上”或“之下”的部件、元件或材料层的词语“之上”或“之下”在本文中可以用于表示部件、元件或材料层直接位于(例如，放置、形成、布置、沉积等)所暗示的表面“上”或直接位于所暗示的表面“下”，例如，与所暗示的表面直接接触。然而，关于形成或位于表面“之上”或“之下”的部件、元件或材料层所使用的词语“之上”或“之下”在本文中可以用于表示部件、元件或材料层间接位于(例如，放置、形成、布置、沉积等)所暗示的表面“上”或间接位于所暗示的表面“下”，其中一个或多个额外的部件、元件或层布置在所暗示的表面与部件、元件或材料层之间。
图1示出了示例性半导体装置100的示意性横截面图。半导体装置100包括半导体晶体管芯片110。半导体晶体管芯片110是在等于或高于例如100V、200V、300V、400V、500V、600V、700V、800V、900V或1000V的电源电压(例如漏极电压)下操作的高电压半导体晶体管芯片。特别地，半导体晶体管芯片110可以在处于300V与800V之间的范围中的电源电压下操作。
半导体晶体管芯片110可以是垂直晶体管装置。半导体晶体管芯片110具有前侧110A和背侧110B。低电压负载电极120和控制电极130设置在半导体晶体管芯片110的前侧110A，并且高电压负载电极140设置在半导体晶体管芯片110的背侧110B。
半导体晶体管芯片110可以例如是由任何半导体材料(例如Si、SiC、SiGe、GaAs、GaN、AlGaN、InGaAs、InAlAs等)制成的。特别地，本文中考虑高电压Si或SiC晶体管芯片110。
电介质无机基板150附接到半导体晶体管芯片110的前侧110A。更具体地，半导体晶体管芯片110的前侧110A通过晶圆接合连接180附接到电介质无机基板150的顶表面150A。半导体晶体管芯片110的前侧110A可以被电介质无机基板150完全覆盖。特别地，电介质无机基板150可以是玻璃基板，并且晶圆接合连接180可以例如是玻璃熔料连接。
电介质无机基板150包括第一金属结构160的图案。第一金属结构160可以容纳在电介质无机基板150的凹陷中。第一金属结构160贯穿电介质无机基板150，其中，第一金属结构160的图案连接到低电压负载电极120。
电介质无机基板150还包括贯穿电介质无机基板150的至少一个第二金属结构170。第二金属结构170连接到控制电极130。
第一金属结构160和第二金属结构170可以是由镀覆的金属柱形成的。为此，在晶圆接合之前，在电介质无机基板150中形成凹陷或通孔，并且可以通过金属镀覆在电介质无机基板150的凹陷或通孔中形成第一金属结构160和第二金属结构170。
电介质无机基板150可以是玻璃基板或半导体基板。如果金属结构160需要彼此电绝缘，则可以使用玻璃或本征半导体基板材料或具有带有绝缘侧壁的凹陷的半导体基板。具有绝缘侧壁的凹陷可以例如是通过将绝缘层(例如氧化硅层或氮化硅层)施加到凹陷的侧壁来形成的，第一金属结构160和第二金属结构170容纳在凹陷中。
半导体装置100可以被称为复合芯片或基板-半导体异质结构。这样的复合芯片可以是从复合晶圆切分出来的，复合晶圆可以包括通过晶圆接合连接接合在一起的半导体晶圆和电介质无机基板晶圆。
这样的复合芯片提供了多个优点，尤其是对于高电压晶体管芯片的封装。
首先，通过将永久电介质无机基板150与半导体晶体管芯片110一起集成在封装中，电介质无机基板150可以用作“适配器”，其可以被适当地结构化和金属化从而使复合芯片直接可焊接到引线框架或应用板或给定几何形状的另一端子结构。例如，第一金属结构160可以结束于基板金属化部120M中，基板金属化部120M代表半导体装置(复合芯片)100的低电压负载电极120并且在电介质无机基板150的底表面150B上延伸。因此，一个或多个第二金属结构170可以结束于基板金属化部130M中，基板金属化部130M代表半导体装置(复合芯片)100的控制电极130。由于基板金属化部120M和130M(通过电介质无机基板150)与半导体晶体管芯片110间隔开，在其几何形状方面的约束是基本上宽松的。为此以及出于其他原因，(低电压)基板金属化部120M、130M的几何形状可以分别相对于低电压负载电极120和控制电极130的几何形状而改变。
换言之，电介质无机基板150作为半导体晶体管芯片110与在包括半导体装置100的高电压半导体封装的内部(例如，由引线框架)或外部(例如，由应用板)提供的端子几何形状之间的“芯片电极布局适配器”可能是有用的。这允许“适配的”芯片前侧电极(即基板金属化部120M、130M)到端子结构(例如，引线框架)的直接接合，而在修改端子结构几何形状(例如，引线框架设计)时无需芯片加工的改变。此外，如果已经可用的芯片类型将被封装在使用给定端子结构(例如，引线框架)几何形状的封装中，则这样的“芯片电极布局适配器”可能是有用的。
作为第二方面，当被电介质无机基板晶圆支撑时，电介质无机基板150的实施方式允许对非常薄的半导体晶圆进行加工。因此，可以使用具有先进的电性能和热性能的高电压半导体晶体管芯片110。
第三，应当注意，在高电压半导体晶体管芯片110的情况下，在半导体晶体管芯片110的前侧110A与低电压连接元件(例如，低电压负载电极连接元件或控制电极连接元件)之间需要横向延伸跨越半导体晶体管芯片110的边缘的相对大的间距。需要该间距是因为芯片边缘与半导体晶体管芯片110的背侧110B处于快速改变的高电压电位下。例如，虽然在半导体晶体管芯片110的前侧110A处的电压波动在低电压负载电极处位于例如0.1-3V之间，并且在控制电极处位于例如0-20V之间，但是在半导体晶体管芯片110的背侧110B和边缘处的电压波动位于0V与(例如)300V至800V或甚至1000V之间，频率为数百kHz。位于半导体晶体管芯片110的前侧110A与低电压连接元件或端子(例如，引线框架或应用板或层合体的导体迹线)之间的延伸跨越半导体晶体管芯片110的边缘的相对大的间距允许场线在低电压连接元件与芯片边缘之间横向逃逸。
该距离是通过提供具有足够厚度TS的电介质无机基板150产生的。因此，电介质无机基板150充当“延伸”以允许场线在低电压端子元件与芯片边缘之间横向离开。例如，电介质无机基板150可以具有可以等于或大于或小于50μm或100μm或200μm或300μm或400μm的厚度TS。虽然对于SiC或其他高能带间隙半导体材料，50μm的厚度TS可以(例如)是足够的，但是Si半导体晶体管芯片110有利地可以使用等于或大于100μm的厚度TS的电介质无机基板150。
电介质无机基板150的底表面150B可以是(高度地)平面的。电介质无机基板150的底表面150B可以与半导体晶体管芯片110的背侧110B平行。
从图2A和图2B显而易见的是，第一金属结构160可以以密集充填的阵列布置在电介质无机基板150中。换句话说，电介质无机基板150可以形成用于第一金属结构160的图案或阵列的矩阵。第一金属结构160的图案或阵列内的金属在电介质无机基板150中的体积百分比可能较高，例如等于或大于(例如)40％或50％或60％或70％或80％。
第一金属结构160的图案可以(例如)是规则的阵列。第一金属结构160的图案的间距可以例如等于或大于或小于15μm或17.5μm或20μm或22.5μm或25μm或27.5μm或30μm。相邻的第一金属结构160之间的距离可以例如等于或大于或小于50μm或30μm或10μm或5μm或4μm或3μm或2μm。每个第一金属结构160的横向尺寸可以例如等于或大于或小于12.5μm或15μm或17.5μm或20μm或22.5μm或25μm或27.5μm。相邻的第一金属结构160之间的距离与第一金属结构160的横向尺寸(例如，直径)的比率可以等于或者小于5或3或2或1。
参考图2A，电介质无机基板150可以例如具有多边形形状，特别是矩形形状。
借助电介质无机基板150，半导体装置100可以具有先进的散热性能。半导体装置100中的散热尤其依赖于半导体晶体管芯片110与半导体芯片110安装在其上的端子结构(例如，引线框架或应用板或层合体的导体迹线等)之间的电互连。这里，该电互连包括电介质无机基板150中的第一金属结构160的图案，或者由电介质无机基板150中的第一金属结构160的图案构成。可以在导热性和/或热容量方面对第一金属结构160的图案进行优化。第一金属结构160在电介质无机基板150中充填得越密集，电介质无机基板150的导热性和热容量越好。此外，增加电介质无机基板150的厚度TS增加了其热容量，因为更多的金属保持在电介质无机基板150中以可用于瞬时热吸收。
第二金属结构170可以与上文针对第一金属结构160所描述的相同方式来实施，并且为了简洁起见避免重复。然而，当(多个)第二金属结构170连接到低电流控制电极时，还可能的是，仅单一的第二金属结构(即，连接在控制电极130与控制电极的基板金属化部130M之间的单一的金属柱)是足够的。
返回图2B，第一金属结构160可以例如具有多边形(正方形、六边形等)或圆形横截面。正方形横截面形状示例性地示出在图2B中，而图2A示出了(例如)圆形横截面形状。六边形横截面形状可能是有益的，因为其在电介质无机基板150中提供了高的金属的面积充填密度。
每个第一金属结构160可以是线性的和/或具有轴对称的横截面形状。此外，每个第一金属结构160沿着其穿过电介质无机基板150的延伸可以(例如)具有基本恒定的横截面形状。沿纵向延伸的可变横截面形状(例如，锥形形状或凸出物或增厚物)也是可能的。
此外，图案不需要被设计成规则的阵列。相反，图案可以由多个不同的图案或(例如，规则的)阵列构成。这样的不同的图案(例如，子图案)或阵列(例如，子阵列)可以在第一金属结构160的间距和/或横截面形状方面彼此区别。
图3示出了引线框架封装300的示例。引线框架封装300包括具有第一引线框架焊盘310_1和第二引线框架焊盘310_2的引线框架310。如上所述，半导体装置100接合到引线框架310。更具体地，第一金属结构160的图案接合到第一引线框架焊盘310_1，并且至少一个第二金属结构170接合到第二引线框架焊盘310_2。
如图3所示，引线框架封装300依赖于低电压电极向下的方法。在下文中，在不失一般性的情况下，通过半导体晶体管芯片110的源极电极例示出了低电压负载电极120，并且通过半导体晶体管芯片110的栅极电极例示出了控制电极130。因此，低电压电极向下的方法在下文中被称为源极向下的方法。
引线框架封装300的源极向下的方法解决了高电压应用的另一问题。常规地，散热器总是耦合到漏极(这里，背侧高电压负载电极140)。在该情况下，散热器必须不断地充电或放电，或者，如果散热器电容地耦合到漏极140，由于电容性耦合，因此发生损耗。对于高电压引线框架封装，关于散热器的这两种类型的损耗(充电/放电损耗或电容性损耗)以及其他高频率电磁干扰(EMI)特性(其由于漏极140电极的大面积而不可避免地发生)是主要缺点。
采用图3中的源极向下的方法，解决了这些问题。这是因为半导体晶体管芯片110使其源极经由电介质无机基板延伸150连接到引线框架310，并且因此也连接到散热器。如前文提及的，源极总是处于低电位下，即并非不断地在零与高电压之间波动。
引线框架封装300可以包括由模制包封材料(未示出)形成的封装体。此外，引线框架封装300可以包括接合到高电压负载电极(例如，漏极电极)140的导电元件340。导电元件340可以例如是连接到高电压引线框架封装300的高电压端子(未示出)的夹或带或多个接合导线。
如上所述，引线框架310可以具有多种不同的几何形状(例如，具体示例参见图4)，由于由电介质无机基板150提供的几何适应性，其可以被容易地修改。
图5以俯视图图示示出了电介质无机基板150位于引线框架310之上的示例性位置。低电压负载电极120(例如，源极电极)的轮廓由虚线520指示，并且控制电极130的轮廓由虚线530指示。显而易见的是，电介质无机基板150允许使用引线框架几何结构，如果引线框架310将直接焊接到半导体晶体管芯片110，则可以不使用引线框架几何结构。此外，由于第一引线框架焊盘310_1代表引线框架310的热焊盘，因此图3至图5中的源极向下的方法允许低电压负载电极120经由具有高导热性的第一金属结构160与散热器(即第一引线框架焊盘310_1)接触，而无充电/放电损耗或电容性损耗，并且改进了EMI特性。
参考图6，半导体装置100可以直接地安装(例如，焊接)到应用板610。更具体地，低电压负载电极基板金属化部120M和控制电极基板金属化部130M可以通过接合材料620(例如，焊料、导电粘合剂、烧结材料……)电和机械固定到提供在应用板610上的导体迹线(未示出)。
与上文所描述相类似，可以通过使用例如导电元件340(在图6中未示出)和/或模制包封体来对半导体装置100进行封装。参考以上描述以避免重复。
图7示出了层合嵌入式芯片封装700的示例。层合嵌入式芯片封装700包括用于半导体装置嵌入的层合结构710。半导体装置100嵌入层合结构710中。
层合结构710可以例如是印刷电路板(PCB)。PCB可以包括由层合层750间隔开的导电层720、730。层合层750提供对导电层720、730的电绝缘和机械支撑。导电层720、730可以是结构化的(参见导电层730)或非结构化的。含有(例如环氧树脂或聚酯的)基质和增强结构(例如玻璃纤维或其他填料材料(例如，陶瓷))的电介质复合材料可以用作层合结构710。层合结构710可以例如是FR-4PCB。
层合嵌入式芯片封装700可以由多种层合和芯片嵌入式工艺形成。例如，层合结构710可以由凹陷的PCB形成，并且然后将半导体装置100放置到凹陷中。
另一可能性是首先将半导体装置100(复合芯片)放置于在图7中由导电层720代表的基底载体上。该基底载体可以是金属板或引线框架。半导体装置100可以通过公知的技术(例如使用可印刷导电膏或者焊接)接合到该基底载体。在将半导体装置100接合到基底载体(例如，导电层720)的工艺之后，层合层750可以真空层合在基底载体上。换言之，接合到引线框架(例如，例如等于或大于150μm的厚度的结构化或非结构化的金属板)的半导体装置100经受层合工艺以进行封装。在层合之后，可以形成到基底载体720和到基板金属化部120M、130M的过孔接触部(未示出)以将半导体装置100电连接到外部端子。
图8示出了另一层合嵌入式芯片封装800的示例。在该示例中，层合结构710是嵌入式芯片封装800的核心层合结构。层合嵌入式芯片封装800还包括在核心层合结构710和半导体装置100下方延伸的底部层合结构810_1。替代地或另外地，层合嵌入式芯片封装800可以设置有在核心层合结构710和半导体装置100上方延伸的顶部层合结构810_2。此外，导电层820和/或830可以提供在底部层合结构810_1和/或顶部层合结构810_2上。这些导电层820、830可以是结构化的或非结构化的，并且可以通过延伸穿过底部层合结构810_1和/或顶部层合结构810_2的过孔(未示出)分别电连接到导电层720或730，以便将半导体装置100电连接到外部电路系统。这里，(例如)结构化的导电层730形成到半导体装置100的电接触部，这些电接触部彼此断开连接并且嵌入电介质材料(层合层750和顶部层合结构810_2)中。此外，如上文针对层合嵌入式芯片封装700所描述的，同样在层合嵌入式芯片封装800中，半导体装置100可以预先接合到(结构化或非结构化的)引线框架(而不是导电层720)，并且然后通过组合的半导体装置100和引线框架层合容纳在层合嵌入式芯片封装800中。(结构化或非结构化的)引线框架或导电层720和/或导电层730可以具有(例如)等于或大于150μm的厚度。
层合嵌入式芯片封装700、800还利用了电介质无机基板150的间隔体功能性。电介质无机基板150保证了位于芯片边缘与导电层730之间的延伸跨越芯片边缘的足够的间距。没有电介质无机基板150时，将需要通过其他方式提供该间距，例如通过施加的相对厚的层合间隔层，而不是电介质无机基板150。然而，这样的厚的层合间隔层在嵌入工艺中引起困难。考虑到工艺和装置稳定性，使用具有预安装的电介质无机基板间隔体作为将层合的对象的半导体晶体管芯片110要方便得多。因此，应用到层合芯片封装中的芯片嵌入的“复合芯片”方法使得这样的HV封装的制造工艺更加容易且更加可靠。
参考图9，电介质无机基板150可以包括多个堆叠的电介质无机基板层150_1、150_2、150_3，或者由多个堆叠的电介质无机基板层150_1、150_2、150_3构成。每个电介质无机基板层150_1、150_2、150_3可以以与针对电介质无机基板150所描述的相同的方式来构造。如图9所示，通过多层结构实施电介质无机基板150可以促进制造厚电介质无机基板150的工艺，因为采用较薄的结构(即，层150_1、150_2和150_3)可以更加方便地执行凹陷形成和金属镀覆。例如，如果期望300μm的厚度TS，则仅需要对(例如)50μm或100μm的厚度的电介质无机基板层150_1、150_2、150_3执行这些工艺中的每种工艺。
可以预先制作包括第一金属结构160和第二金属结构170的电介质无机基板层150_1、150_2、150_3，并且然后对准并接合在一起以形成电介质无机基板150。如前所述，可以(例如)在相邻的电介质无机基板层150_1、150_2和150_3之间通过使用玻璃熔料连接在晶圆水平上完成层接合。
此外，该堆叠多个电介质无机基板层150_1、150_2、150_3的技术允许形成第三金属结构960，其不延伸穿过电介质无机基板150，但是结束于电介质无机基板150中的与设置有第三金属结构960的电介质无机基板层150_2、150_3相邻的电介质无机基板层150_1、150_2处。这样的第三金属结构960可以用作场板(例如，源极场板)，其允许在半导体晶体管芯片110上方适当地产生电场。由于电介质无机基板150的逐层布置，不需要制作盲孔来实现终止于电介质无机基板150中的这样的第三金属结构960。
图10A-图10L示出了根据本公开的制造半导体装置100的工艺的示例性阶段。
参考图10A，提供了电介质无机基板晶圆1050。电介质无机基板晶圆1050可以例如具有300至1100μm(特别地，400至700μm)的厚度。电介质无机基板晶圆1050可以例如是玻璃晶圆或半导体晶圆。图10A-图10L仅示出了电介质无机基板晶圆1050的包括例如一个半导体芯片110的一部分，参见图10L。
图10B示出了在电介质无机基板晶圆1050的顶表面1050A中的凹陷1020的形成。凹陷1020可以是通过蚀刻形成的。凹陷1020的尺寸(横向尺寸，深度)可以与上文针对第一金属结构160所描述的尺寸相对应。
根据图10B，电介质无机基板晶圆1050可以包括(每芯片)凹陷1020的第一图案PAT1和凹陷1020的第二图案PAT2。如图10B的右手侧所示，其示出了电介质无机基板晶圆1050的芯片部分的俯视图，PAT1的面积可以(例如)基本上大于PAT2的面积。此外，如前文提及的，PAT1和PAT2中的凹陷1020的参数(间距、距离、形状……)可以彼此不同或者可以是相同的。
在一个实施例中，仅形成第一图案PAT1作为凹陷的图案，而第二图案PAT2由另一类型的贯穿连接(例如，充当用于例如半导体晶体管芯片110的控制电极130的贯穿连接的单一的孔)替代。
形成在电介质无机基板晶圆1050中的凹陷1020中的一些凹陷可以具有比电介质无机基板晶圆1050的目标厚度(即图1中的TS)小的深度，而其他凹陷1020具有比电介质无机基板晶圆1050的目标厚度大的深度。
参考图10C，衬层1012可以可选地沉积在电介质无机基板晶圆1050的顶表面1050A之上。衬层1012可以例如是导电晶种层。
参考图10D，可以在电介质无机基板晶圆1050的顶表面之上以及例如衬层1012之上施加保护层1014。可以使用自对准工艺来施加保护层1014。就是说，可以仅在电介质无机基板晶圆1050的顶表面1050A的非凹陷的部分之上施加保护层1014。可以(例如)通过轧制和/或印刷工艺施加保护层1014，并且保护层1014可以(例如)完全覆盖位于电介质无机基板晶圆1050的顶表面1050A的非凹陷部分处的衬层1012。
应当注意的是，图10C和图10D所示的衬层1012沉积和/或保护层1014沉积的工艺是可选的工艺，因为也可以在不采用衬层1012和/或保护层1014沉积的情况下执行如下文所描述的金属镀覆。
参考图10F，对金属进行镀覆以填充凹陷1020。因此，形成第一金属结构160。第一金属结构160可以完全填充凹陷1020。此外，可以形成第二金属结构170。
第一金属结构160可以在电介质无机基板晶圆1050的顶表面1050A之上伸出较小的距离。可以通过电化学沉积(ECD)执行金属镀覆。例如，铜或铜合金可以用作镀覆金属，但是也可以使用本领域中公知的适合于封装互连的其他金属。对于(多个)第二金属结构170，这同样成立。
参考图10G，通过(例如)蚀刻来移除保护层1014(如果存在)和衬层1012(如果存在)。
参考图10H，可以在电介质无机基板晶圆1050上施加接合材料1080。可以在电介质无机基板晶圆1050的与半导体晶圆1010的非有源区域相对应的区域上施加接合材料1080(参见图10I)。
接合材料1080可以(例如)包括或者是玻璃胶(例如玻璃熔料)或树脂或适合将电介质无机基板晶圆1050永久地接合到半导体晶圆1010的任何其他材料(参见图10I)。
参考图10I，半导体晶圆1010的前侧与电介质无机基板晶圆1050组合以形成复合晶圆1000。在该工艺期间，第一金属结构160的多个图案与多个低电压负载电极120相对地放置在半导体晶圆1010上。另外，应当注意，图10I仅示出了电介质无机基板晶圆1050和半导体晶圆1010的局部视图，其基本上与半导体晶圆1010中的一个半导体晶体管芯片110相对应。因此，第一金属结构160的第一图案PAT1和第二金属结构170的第二图案PAT2可以形成与半导体晶圆1010的单一的半导体晶体管芯片110的两个电极120、130相对应的子图案。
可以通过使用贯穿电介质无机基板晶圆1050的光学对准(例如，所谓的贯穿玻璃对准或贯穿半导体对准)，来执行如图10I中所示的将半导体晶圆1010与电介质无机基板晶圆1050进行组合的工艺。就是说，可以通过贯穿电介质无机基板晶圆1050来观察以识别半导体晶圆1010相对于电介质无机基板晶圆1050的位置的位置，从而以适当的对准将半导体晶圆1010与电介质无机基板晶圆1050进行组合。
接合材料1080可能也已经被施加到半导体晶圆1010，而不是被施加到电介质无机基板晶圆1050。
图10J示出了将半导体晶圆1010接合到电介质无机基板晶圆1050的工艺，其中半导体晶圆1010的前侧1010A面向电介质无机基板晶圆1050。该工艺可以同时将电介质无机基板晶圆1050上的第一金属结构160的多个图案连接到半导体晶圆1010上的多个低电压负载电极120。可以通过向复合晶圆1000施加热和压力来执行该工艺。
借助该工艺，接合材料1080将半导体晶圆1010固定地紧固到电介质无机基板晶圆1050。此外，通过该工艺或另一工艺，第一金属结构160可以固定地电和机械连接到低电压负载电极120。连接可以是无焊料的，即没有焊料材料可以用于建立低电压负载电极120与第一金属结构160之间的电、机械和热连接。通过示例，连接可以是通过低电压负载电极120的金属与第一金属结构160的金属之间的共晶相的形成来创建的。对于第二金属结构170到控制电极130的连接，这同样成立。
参考图10K和图10L，可以从与顶表面1050A相对的底表面1050B(参见图10J)对电介质无机基板晶圆1050进行减薄，以暴露凹陷1020中的金属结构160的至少一部分或所有的金属。
更具体地，减薄可以(例如)在多阶段工艺中执行。例如，如图10K所示，减薄可以包括对电介质无机基板晶圆1050向下研磨至仅稍微大于凹陷1020的深度的厚度。例如，研磨可以在凹陷1020的底部之上等于或者小于的20μm或15μm或10μm的距离处停止。
然后可以通过将电介质无机基板晶圆1050向下蚀刻至厚度TS(参见图1)来暴露第一金属结构160或它们中的至少一部分。可以通过湿法或干法化学蚀刻来执行蚀刻。蚀刻可以继续直到第一金属结构160(或它们中的至少一些)，并且例如，第二金属结构170也在减薄的电介质无机基板晶圆1050的底表面之上伸出较小的距离，例如，几个μm。如图1所示，减薄的电介质无机基板晶圆1050的底表面可以与电介质无机基板150的底表面150B相对应。
在下文中，可以对图10L中所示的复合晶圆1000执行芯片封装的后段制程(BEOL)工艺。在该背景下，沿切分线L将复合晶圆1000分离成与半导体装置100相对应的复合芯片。可以通过任何适当的切分方法(例如机械切割、激光切分和/或蚀刻)将复合晶圆1000分离成复合芯片。因此，高电压半导体晶体管芯片110和电介质无机基板150可以具有对准的切割边缘。
以下示例涉及本公开的其他方面：
示例1是一种高电压半导体封装，包括：半导体装置，其包括高电压半导体晶体管芯片，高电压半导体晶体管芯片包括前侧和背侧，其中，低电压负载电极和控制电极设置在半导体晶体管芯片的前侧，并且高电压负载电极设置在半导体晶体管芯片的背侧；电介质无机基板，其包括贯穿电介质无机基板的第一金属结构的图案，其中，第一金属结构的图案连接到低电压负载电极；以及贯穿电介质无机基板的至少一个第二金属结构，其中，第二金属结构连接到控制电极，其中，半导体晶体管芯片的前侧通过晶圆接合连接被附接到电介质无机基板，并且电介质无机基板具有至少50μm的厚度。
在示例2中，示例1的主题可以可选地包括：其中，引线框架包括第一引线框架焊盘和第二引线框架焊盘；以及半导体装置，其中，电介质无机基板接合到引线框架，其中，第一金属结构的图案接合到第一引线框架焊盘，并且至少一个第二金属结构接合到第二引线框架焊盘。
在示例3中，示例2的主题可以可选地包括：其中，第一引线框架焊盘形成高电压半导体封装的低电压端子，特别是源极端子，并且第二引线框架焊盘形成高电压半导体封装的控制端子，特别是栅极端子。
在示例4中，示例2或3的主题可以可选地包括：导电元件，其接合到半导体晶体管芯片的高电压负载电极，并且连接到高电压半导体封装的高电压端子。
在示例5中，示例1的主题可以可选地包括：其中，用于半导体装置嵌入的层合结构，其中，半导体装置嵌入在层合结构中。
在示例6中，示例5的主题可以可选地包括：其中，层合结构是印刷电路板。
在示例7中，示例5或6的主题可以可选地包括：其中，层合结构是核心层合结构，高电压半导体封装还包括：在核心层合结构和半导体装置下方延伸的底部层合结构；和/或在核心层合结构和半导体装置上方延伸的顶部层合结构。
在示例8中，前述示例中的任何一项的主题可以可选地包括：其中，电介质无机基板是玻璃基板。
在示例9中，示例8的主题可以可选地包括：其中，晶圆接合连接是玻璃熔料连接。
在示例10中，前述示例中的任何一项的主题可以可选地包括：其中，第一金属结构通过金属到金属的晶圆接合连接来连接到低电压负载电极，和/或第二金属结构通过金属到金属的晶圆接合连接来连接到控制电极。
在示例11中，前述示例中的任何一项的主题可以可选地包括：其中，电介质无机基板包括多个堆叠的电介质无机基板层。
在示例12中，前述示例中的任何一项的主题可以可选地包括：其中，第一金属结构是镀覆的金属柱。
在示例13中，前述示例中的任何一项的主题可以可选地包括：其中，图案是规则的阵列。
在示例14中，前述示例中的任何一项的主题可以可选地包括：其中，相邻的第一金属结构之间的距离与第一金属结构的横向尺寸(例如直径)的比率等于或者小于5或3或2或1。
在示例15中，前述示例中的任何一项的主题可以可选地包括：其中，半导体晶体管芯片的前侧被电介质无机基板完全覆盖。
尽管这里已经示出和描述了特定实施例，但是本领域普通技术人员将理解，各种替代和/或等效实施方式可以替代所示出和描述的特定实施例，而不脱离本发明的范围。本申请旨在覆盖本文所讨论的特定实施例的任何改造或变化。因此，旨在使本发明仅由权利要求及其等同物限制。

Claims (15)

1.一种高电压半导体封装，包括：
半导体装置，所述半导体装置包括：
高电压半导体晶体管芯片，其包括前侧和背侧，其中，低电压负载电极和控制电极设置在所述半导体晶体管芯片的所述前侧，并且高电压负载电极设置在所述半导体晶体管芯片的所述背侧；
电介质无机基板，所述电介质无机基板包括：
贯穿所述电介质无机基板的第一金属结构的图案，其中，所述第一金属结构的所述图案连接到所述低电压负载电极；以及
贯穿所述电介质无机基板的至少一个第二金属结构，其中，所述第二金属结构连接到所述控制电极，其中，
所述半导体晶体管芯片的所述前侧通过晶圆接合连接被附接到所述电介质无机基板，并且
所述电介质无机基板具有至少50μm的厚度。
2.根据权利要求1所述的高电压半导体封装，还包括：
引线框架，所述引线框架包括第一引线框架焊盘和第二引线框架焊盘；以及
所述半导体装置，其中，所述电介质无机基板接合到所述引线框架，其中，所述第一金属结构的所述图案接合到所述第一引线框架焊盘，并且所述至少一个第二金属结构接合到所述第二引线框架焊盘。
3.根据权利要求2所述的高电压半导体封装，其中，所述第一引线框架焊盘形成所述高电压半导体封装的低电压端子，特别是源极端子，并且所述第二引线框架焊盘形成所述高电压半导体封装的控制端子，特别是栅极端子。
4.根据权利要求2或3所述的高电压半导体封装，还包括：
导电元件，所述导电元件接合到所述半导体晶体管芯片的所述高电压负载电极，并且连接到所述高电压半导体封装的高电压端子。
5.根据权利要求1所述的高电压半导体封装，还包括：
用于半导体装置嵌入的层合结构，其中，所述半导体装置嵌入在所述层合结构中。
6.根据权利要求5所述的高电压半导体封装，其中，所述层合结构是印刷电路板。
7.根据权利要求5或6所述的高电压半导体封装，其中，所述层合结构是核心层合结构，所述高电压半导体封装还包括：
在所述核心层合结构和所述半导体装置下方延伸的底部层合结构；和/或
在所述核心层合结构和所述半导体装置上方延伸的顶部层合结构。
8.根据前述权利要求中的任何一项所述的高电压半导体封装，其中，所述电介质无机基板是玻璃基板。
9.根据权利要求8所述的高电压半导体封装，其中，所述晶圆接合连接是玻璃熔料连接。
10.根据前述权利要求中的任何一项所述的高电压半导体封装，其中，所述第一金属结构通过金属到金属的晶圆接合连接来连接到所述低电压负载电极，和/或所述第二金属结构通过金属到金属的晶圆接合连接来连接到所述控制电极。
11.根据前述权利要求中的任何一项所述的高电压半导体封装，其中，所述电介质无机基板包括多个堆叠的电介质无机基板层。
12.根据前述权利要求中的任何一项所述的高电压半导体封装，其中，所述第一金属结构是镀覆的金属柱。
13.根据前述权利要求中的任何一项所述的高电压半导体封装，其中，所述图案是规则的阵列。
14.根据前述权利要求中的任何一项所述的高电压半导体封装，其中，相邻的第一金属结构之间的距离与第一金属结构的横向尺寸的比率等于或者小于5或3或2或1。
15.根据前述权利要求中的任何一项所述的高电压半导体封装，其中，所述半导体晶体管芯片的所述前侧被所述电介质无机基板完全覆盖。
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