CN100589204C - 与控制器通信的存储单元、存储系统和集成电路及配置就绪/忙信号的方法 - Google Patents

与控制器通信的存储单元、存储系统和集成电路及配置就绪/忙信号的方法 Download PDF

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Publication number
CN100589204C
CN100589204C CN200580022673A CN200580022673A CN100589204C CN 100589204 C CN100589204 C CN 100589204C CN 200580022673 A CN200580022673 A CN 200580022673A CN 200580022673 A CN200580022673 A CN 200580022673A CN 100589204 C CN100589204 C CN 100589204C
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controller
memory
busy
ready
integrated circuit
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CN1981345A (zh
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彼得·约翰·史密斯
瑟吉·阿纳托利耶维奇·戈罗别茨
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Shengdi Technology Co ltd
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SanDisk Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
CN200580022673A 2004-05-27 2005-05-20 与控制器通信的存储单元、存储系统和集成电路及配置就绪/忙信号的方法 Expired - Lifetime CN100589204C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/857,532 US8429313B2 (en) 2004-05-27 2004-05-27 Configurable ready/busy control
US10/857,532 2004-05-27

Publications (2)

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CN1981345A CN1981345A (zh) 2007-06-13
CN100589204C true CN100589204C (zh) 2010-02-10

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CN200580022673A Expired - Lifetime CN100589204C (zh) 2004-05-27 2005-05-20 与控制器通信的存储单元、存储系统和集成电路及配置就绪/忙信号的方法

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Country Link
US (1) US8429313B2 (https=)
EP (1) EP1751772B1 (https=)
JP (1) JP2008500678A (https=)
KR (1) KR101182597B1 (https=)
CN (1) CN100589204C (https=)
AT (1) ATE437440T1 (https=)
DE (1) DE602005015578D1 (https=)
TW (1) TWI280580B (https=)
WO (1) WO2005119693A2 (https=)

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CN103247613B (zh) * 2013-04-09 2016-03-30 北京兆易创新科技股份有限公司 增强型Flash的多芯片的封装芯片、通信方法和封装方法
CN103247611B (zh) * 2013-04-09 2015-09-09 北京兆易创新科技股份有限公司 一种增强型flash芯片和一种芯片封装方法
CN103246553B (zh) * 2013-04-09 2016-12-28 北京兆易创新科技股份有限公司 一种增强型Flash芯片和一种芯片封装方法
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JP2015176309A (ja) 2014-03-14 2015-10-05 株式会社東芝 半導体記憶装置
CN105511807B (zh) * 2015-11-30 2018-05-22 杭州华澜微电子股份有限公司 一种基于存储设备的数据存储管理方法及系统
KR102554416B1 (ko) 2016-08-16 2023-07-11 삼성전자주식회사 메모리 장치의 내부 상태 출력 장치 및 이를 적용하는 메모리 시스템
JP2018041154A (ja) * 2016-09-05 2018-03-15 東芝メモリ株式会社 ストレージシステムおよび処理方法
KR102632452B1 (ko) * 2016-10-17 2024-02-05 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법
JP2019046254A (ja) * 2017-09-04 2019-03-22 東芝メモリ株式会社 半導体メモリ装置、方法及びプログラム
KR20190032809A (ko) * 2017-09-20 2019-03-28 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작 방법
KR102408482B1 (ko) * 2017-10-20 2022-06-14 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법
CN111210855B (zh) * 2019-12-30 2020-09-15 深圳市芯天下技术有限公司 一种多晶元叠封存储器及其输出同步方法
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CN113448962B (zh) * 2021-06-02 2022-10-28 中科驭数（北京）科技有限公司 数据库数据管理方法和装置
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Also Published As

Publication number Publication date
CN1981345A (zh) 2007-06-13
US20050268025A1 (en) 2005-12-01
EP1751772A2 (en) 2007-02-14
KR101182597B1 (ko) 2012-09-18
ATE437440T1 (de) 2009-08-15
WO2005119693A3 (en) 2006-04-13
WO2005119693A2 (en) 2005-12-15
DE602005015578D1 (https=) 2009-09-03
KR20070024545A (ko) 2007-03-02
TWI280580B (en) 2007-05-01
EP1751772B1 (en) 2009-07-22
JP2008500678A (ja) 2008-01-10
TW200620290A (en) 2006-06-16
US8429313B2 (en) 2013-04-23

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