CN100568485C - 抛光设备和抛光集成电路金属层的两步方法 - Google Patents

抛光设备和抛光集成电路金属层的两步方法 Download PDF

Info

Publication number
CN100568485C
CN100568485C CNB2004800039241A CN200480003924A CN100568485C CN 100568485 C CN100568485 C CN 100568485C CN B2004800039241 A CNB2004800039241 A CN B2004800039241A CN 200480003924 A CN200480003924 A CN 200480003924A CN 100568485 C CN100568485 C CN 100568485C
Authority
CN
China
Prior art keywords
polishing
etchant
metal
period
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2004800039241A
Other languages
English (en)
Chinese (zh)
Other versions
CN1748302A (zh
Inventor
V·恩古延霍安格
R·达亚门
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
NXP BV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV, Koninklijke Philips Electronics NV filed Critical NXP BV
Publication of CN1748302A publication Critical patent/CN1748302A/zh
Application granted granted Critical
Publication of CN100568485C publication Critical patent/CN100568485C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
CNB2004800039241A 2003-02-11 2004-01-23 抛光设备和抛光集成电路金属层的两步方法 Expired - Fee Related CN100568485C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03100284.3 2003-02-11
EP03100284 2003-02-11

Publications (2)

Publication Number Publication Date
CN1748302A CN1748302A (zh) 2006-03-15
CN100568485C true CN100568485C (zh) 2009-12-09

Family

ID=32865028

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004800039241A Expired - Fee Related CN100568485C (zh) 2003-02-11 2004-01-23 抛光设备和抛光集成电路金属层的两步方法

Country Status (7)

Country Link
US (1) US7709387B2 (enExample)
EP (1) EP1595286A1 (enExample)
JP (1) JP2006517737A (enExample)
KR (1) KR20050094481A (enExample)
CN (1) CN100568485C (enExample)
TW (1) TWI324798B (enExample)
WO (1) WO2004073060A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006040585B4 (de) * 2006-08-30 2013-02-07 Infineon Technologies Ag Verfahren zum Auffüllen eines Grabens in einem Halbleiterprodukt
CN103985668B (zh) * 2014-05-13 2018-02-23 上海集成电路研发中心有限公司 铜互连的制备方法
US11898081B2 (en) 2019-11-21 2024-02-13 Tokyo Ohka Kogyo Co., Ltd. Ruthenium-etching solution, method for manufacturing ruthenium-etching solution, method for processing object to be processed, and method for manufacturing ruthenium-containing wiring
JP6895577B2 (ja) * 2019-11-21 2021-06-30 東京応化工業株式会社 エッチング液、エッチング液の製造方法、被処理体の処理方法、及びルテニウム含有配線の製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1185034A (zh) * 1996-12-13 1998-06-17 西门子公司 铝连接的制作方法
EP1085067A1 (en) * 1999-09-20 2001-03-21 Fujimi Incorporated Polishing composition and polishing process
US6326299B1 (en) * 1998-11-09 2001-12-04 Hitachi, Ltd. Method for manufacturing a semiconductor device
US6465354B1 (en) * 1998-11-10 2002-10-15 Nec Corporation Method of improving the planarization of wiring by CMP
US6482743B1 (en) * 1999-09-13 2002-11-19 Sony Corporation Method of forming a semiconductor device using CMP to polish a metal film

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5934980A (en) * 1997-06-09 1999-08-10 Micron Technology, Inc. Method of chemical mechanical polishing
US6436829B1 (en) * 2000-08-04 2002-08-20 Agere Systems Guardian Corp. Two phase chemical/mechanical polishing process for tungsten layers
US20020098673A1 (en) * 2001-01-19 2002-07-25 Ming-Shi Yeh Method for fabricating metal interconnects
US6660627B2 (en) * 2002-03-25 2003-12-09 United Microelectronics Corp. Method for planarization of wafers with high selectivities

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1185034A (zh) * 1996-12-13 1998-06-17 西门子公司 铝连接的制作方法
US6326299B1 (en) * 1998-11-09 2001-12-04 Hitachi, Ltd. Method for manufacturing a semiconductor device
US6465354B1 (en) * 1998-11-10 2002-10-15 Nec Corporation Method of improving the planarization of wiring by CMP
US6482743B1 (en) * 1999-09-13 2002-11-19 Sony Corporation Method of forming a semiconductor device using CMP to polish a metal film
EP1085067A1 (en) * 1999-09-20 2001-03-21 Fujimi Incorporated Polishing composition and polishing process

Also Published As

Publication number Publication date
TWI324798B (en) 2010-05-11
KR20050094481A (ko) 2005-09-27
CN1748302A (zh) 2006-03-15
EP1595286A1 (en) 2005-11-16
TW200507093A (en) 2005-02-16
US20060134915A1 (en) 2006-06-22
US7709387B2 (en) 2010-05-04
JP2006517737A (ja) 2006-07-27
WO2004073060A1 (en) 2004-08-26

Similar Documents

Publication Publication Date Title
US12051621B2 (en) Microelectronic assembly from processed substrate
US6635565B2 (en) Method of cleaning a dual damascene structure
KR101031682B1 (ko) 초저 ｋ 유전체를 갖는 금속을 집적시키는 방법
US6806193B2 (en) CMP in-situ conditioning with pad and retaining ring clean
KR20040060112A (ko) 반도체 소자 제조시 듀얼 다마신 공정을 이용한 콘텍형성방법
JP2001308097A (ja) 半導体装置およびその製造方法
KR100729972B1 (ko) 화학적 기계적 연마 후 반도체 웨이퍼를 세정 및 처리하기 위한 방법
US7056821B2 (en) Method for manufacturing dual damascene structure with a trench formed first
CN100568485C (zh) 抛光设备和抛光集成电路金属层的两步方法
US6936534B2 (en) Method for the post-etch cleaning of multi-level damascene structures having underlying copper metallization
JP2003243400A (ja) 金属製相互接続部を製造する方法
US20020102834A1 (en) Method of forming dual damascene structure
US20050239289A1 (en) Method for reducing integrated circuit defects
CN100353521C (zh) 使用化学机械研磨法制造半导体元件的内连线结构的方法
JP2003092300A (ja) 半導体装置の製造方法及び半導体製造装置
JP2009272560A (ja) 半導体装置の製造方法
KR100310172B1 (ko) 반도체 소자의 금속 배선층 형성 방법
JP2006147655A (ja) 半導体装置の製造方法
Wang et al. Integrated tungsten chemical mechanical polishing process characterization for via plug interconnection in ultralarge scale integrated circuits
US20030216019A1 (en) Method for forming wiring structure
JP2004095813A (ja) 配線構造の形成方法
JP2001044200A (ja) 半導体集積回路装置の製造方法および半導体集積回路装置
KR20090069502A (ko) 반도체 소자의 구리배선 형성방법
KR20100037219A (ko) 구리 금속 배선 형성 방법
JP2004063735A (ja) 半導体装置の製造方法および製造装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: NXP CO., LTD.

Free format text: FORMER OWNER: KONINKLIJKE PHILIPS ELECTRONICS N.V.

Effective date: 20071109

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20071109

Address after: Holland Ian Deho Finn

Applicant after: Koninkl Philips Electronics NV

Address before: Holland Ian Deho Finn

Applicant before: Koninklijke Philips Electronics N.V.

C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20091209

Termination date: 20130123