CN100541659C - 具有2t存储器单元的存储器阵列 - Google Patents
具有2t存储器单元的存储器阵列 Download PDFInfo
- Publication number
- CN100541659C CN100541659C CNB038120100A CN03812010A CN100541659C CN 100541659 C CN100541659 C CN 100541659C CN B038120100 A CNB038120100 A CN B038120100A CN 03812010 A CN03812010 A CN 03812010A CN 100541659 C CN100541659 C CN 100541659C
- Authority
- CN
- China
- Prior art keywords
- voltage
- memory
- word line
- transistor
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
- Medicines Containing Antibodies Or Antigens For Use As Internal Diagnostic Agents (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP02077100 | 2002-05-28 | ||
| EP02077100.2 | 2002-05-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1656565A CN1656565A (zh) | 2005-08-17 |
| CN100541659C true CN100541659C (zh) | 2009-09-16 |
Family
ID=29558383
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB038120100A Expired - Fee Related CN100541659C (zh) | 2002-05-28 | 2003-05-09 | 具有2t存储器单元的存储器阵列 |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US7038943B2 (https=) |
| EP (1) | EP1512150B1 (https=) |
| JP (1) | JP2005527931A (https=) |
| CN (1) | CN100541659C (https=) |
| AT (1) | ATE479990T1 (https=) |
| AU (1) | AU2003230096A1 (https=) |
| DE (1) | DE60333998D1 (https=) |
| TW (1) | TWI289305B (https=) |
| WO (1) | WO2003100788A2 (https=) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7880238B2 (en) * | 2008-04-10 | 2011-02-01 | International Business Machines Corporation | 2-T SRAM cell structure and method |
| US8164964B2 (en) * | 2009-09-16 | 2012-04-24 | Arm Limited | Boosting voltage levels applied to an access control line when accessing storage cells in a memory |
| US8355276B2 (en) * | 2009-11-20 | 2013-01-15 | Arm Limited | Controlling voltage levels applied to access devices when accessing storage cells in a memory |
| US8634230B2 (en) * | 2011-01-28 | 2014-01-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for driving the same |
| KR101944535B1 (ko) * | 2012-03-28 | 2019-01-31 | 삼성전자주식회사 | 반도체 기억 소자 |
| KR20140092537A (ko) | 2013-01-16 | 2014-07-24 | 삼성전자주식회사 | 메모리 셀 및 이를 포함하는 메모리 장치 |
| US9659944B2 (en) * | 2015-06-30 | 2017-05-23 | Avago Technologies General Ip (Singapore) Pte. Ltd. | One time programmable memory with a twin gate structure |
| KR20180130581A (ko) * | 2016-08-31 | 2018-12-07 | 마이크론 테크놀로지, 인크 | 메모리 셀 및 메모리 어레이 |
| WO2018132250A1 (en) | 2017-01-12 | 2018-07-19 | Micron Technology, Inc. | Memory cells, arrays of two transistor-one capacitor memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry |
| CN107678920B (zh) * | 2017-09-27 | 2021-11-23 | 惠州Tcl移动通信有限公司 | 防止动态存储烧坏存储器的方法、存储介质及智能终端 |
| US10395752B2 (en) * | 2017-10-11 | 2019-08-27 | Globalfoundries Inc. | Margin test for multiple-time programmable memory (MTPM) with split wordlines |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5943270A (en) * | 1997-11-26 | 1999-08-24 | Intel Corporation | Two-transistor DRAM cell for logic process technology |
| US5995410A (en) * | 1997-06-20 | 1999-11-30 | Micron Technology, Inc. | Multiplication of storage capacitance in memory cells by using the Miller effect |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5066607A (en) * | 1987-11-30 | 1991-11-19 | Texas Instruments Incorporated | Method of making a trench DRAM cell with dynamic gain |
| US6246083B1 (en) * | 1998-02-24 | 2001-06-12 | Micron Technology, Inc. | Vertical gain cell and array for a dynamic random access memory |
| JP2001290124A (ja) * | 2000-04-07 | 2001-10-19 | Canon Inc | 液晶表示装置 |
| US6804142B2 (en) * | 2002-11-12 | 2004-10-12 | Micron Technology, Inc. | 6F2 3-transistor DRAM gain cell |
-
2003
- 2003-05-09 DE DE60333998T patent/DE60333998D1/de not_active Expired - Lifetime
- 2003-05-09 JP JP2004508351A patent/JP2005527931A/ja active Pending
- 2003-05-09 WO PCT/IB2003/001931 patent/WO2003100788A2/en not_active Ceased
- 2003-05-09 AT AT03722939T patent/ATE479990T1/de not_active IP Right Cessation
- 2003-05-09 US US10/515,941 patent/US7038943B2/en not_active Expired - Fee Related
- 2003-05-09 CN CNB038120100A patent/CN100541659C/zh not_active Expired - Fee Related
- 2003-05-09 EP EP03722939A patent/EP1512150B1/en not_active Expired - Lifetime
- 2003-05-09 AU AU2003230096A patent/AU2003230096A1/en not_active Abandoned
- 2003-05-23 TW TW092114054A patent/TWI289305B/zh not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5995410A (en) * | 1997-06-20 | 1999-11-30 | Micron Technology, Inc. | Multiplication of storage capacitance in memory cells by using the Miller effect |
| US5943270A (en) * | 1997-11-26 | 1999-08-24 | Intel Corporation | Two-transistor DRAM cell for logic process technology |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI289305B (en) | 2007-11-01 |
| WO2003100788A3 (en) | 2004-02-26 |
| JP2005527931A (ja) | 2005-09-15 |
| DE60333998D1 (https=) | 2010-10-14 |
| ATE479990T1 (de) | 2010-09-15 |
| WO2003100788A2 (en) | 2003-12-04 |
| EP1512150B1 (en) | 2010-09-01 |
| AU2003230096A8 (en) | 2003-12-12 |
| US7038943B2 (en) | 2006-05-02 |
| AU2003230096A1 (en) | 2003-12-12 |
| EP1512150A2 (en) | 2005-03-09 |
| TW200403674A (en) | 2004-03-01 |
| US20050157533A1 (en) | 2005-07-21 |
| CN1656565A (zh) | 2005-08-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: NXP CO., LTD. Free format text: FORMER OWNER: KONINKLIJKE PHILIPS ELECTRONICS N.V. Effective date: 20070810 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20070810 Address after: Holland Ian Deho Finn Applicant after: Koninkl Philips Electronics NV Address before: Holland Ian Deho Finn Applicant before: Koninklijke Philips Electronics N.V. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090916 Termination date: 20120509 |