CN100530640C - 集成电路组合件 - Google Patents

集成电路组合件 Download PDF

Info

Publication number
CN100530640C
CN100530640C CNB2003801092161A CN200380109216A CN100530640C CN 100530640 C CN100530640 C CN 100530640C CN B2003801092161 A CNB2003801092161 A CN B2003801092161A CN 200380109216 A CN200380109216 A CN 200380109216A CN 100530640 C CN100530640 C CN 100530640C
Authority
CN
China
Prior art keywords
trace
circuit die
substrate
circuit
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2003801092161A
Other languages
English (en)
Chinese (zh)
Other versions
CN1742372A (zh
Inventor
伊戈尔·K·汉德罗斯
本杰明·N·埃尔德里奇
查尔斯·A·米勒
A·尼古拉斯·斯珀克
加里·W·格鲁比
加埃唐·L·马蒂厄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FormFactor Inc
Original Assignee
FormFactor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by FormFactor Inc filed Critical FormFactor Inc
Publication of CN1742372A publication Critical patent/CN1742372A/zh
Application granted granted Critical
Publication of CN100530640C publication Critical patent/CN100530640C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H10W70/415—Leadframe inner leads serving as die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/701—Tape-automated bond [TAB] connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/077—Connecting of TAB connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structure Of Printed Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)
CNB2003801092161A 2002-12-12 2003-12-12 集成电路组合件 Expired - Fee Related CN100530640C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/317,661 2002-12-12
US10/317,661 US7550842B2 (en) 2002-12-12 2002-12-12 Integrated circuit assembly

Publications (2)

Publication Number Publication Date
CN1742372A CN1742372A (zh) 2006-03-01
CN100530640C true CN100530640C (zh) 2009-08-19

Family

ID=32506187

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2003801092161A Expired - Fee Related CN100530640C (zh) 2002-12-12 2003-12-12 集成电路组合件

Country Status (8)

Country Link
US (1) US7550842B2 (https=)
EP (1) EP1573815A1 (https=)
JP (1) JP4452627B2 (https=)
KR (1) KR101062260B1 (https=)
CN (1) CN100530640C (https=)
AU (1) AU2003299608A1 (https=)
TW (1) TWI339435B (https=)
WO (1) WO2004055895A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107818799A (zh) * 2016-09-13 2018-03-20 希捷科技有限公司 具有背侧阻抗控制结构的柔性动态回路

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7750446B2 (en) 2002-04-29 2010-07-06 Interconnect Portfolio Llc IC package structures having separate circuit interconnection structures and assemblies constructed thereof
JP2005524239A (ja) * 2002-04-29 2005-08-11 シリコン・パイプ・インコーポレーテッド ダイレクト・コネクト形信号システム
US8324725B2 (en) * 2004-09-27 2012-12-04 Formfactor, Inc. Stacked die module
US7663216B2 (en) 2005-11-02 2010-02-16 Sandisk Corporation High density three dimensional semiconductor die package
US20070241441A1 (en) * 2006-04-17 2007-10-18 Stats Chippac Ltd. Multichip package system
US7569421B2 (en) * 2007-05-04 2009-08-04 Stats Chippac, Ltd. Through-hole via on saw streets
US7723157B2 (en) * 2007-12-28 2010-05-25 Walton Advanced Engineering, Inc. Method for cutting and molding in small windows to fabricate semiconductor packages
TWI370714B (en) * 2008-01-09 2012-08-11 Ind Tech Res Inst Circuit structure and menufacturing method thereof
US7643305B2 (en) * 2008-03-07 2010-01-05 Qualcomm Mems Technologies, Inc. System and method of preventing damage to metal traces of flexible printed circuits
JP2010287733A (ja) * 2009-06-11 2010-12-24 Elpida Memory Inc 半導体装置
KR20110082643A (ko) * 2010-01-12 2011-07-20 삼성전자주식회사 반도체 칩의 실장 기판 및 이를 갖는 반도체 패키지
JP2011155203A (ja) * 2010-01-28 2011-08-11 Elpida Memory Inc 半導体装置
US9136197B2 (en) 2010-09-16 2015-09-15 Tessera, Inc. Impedence controlled packages with metal sheet or 2-layer RDL
US8786083B2 (en) * 2010-09-16 2014-07-22 Tessera, Inc. Impedance controlled packages with metal sheet or 2-layer RDL
US9153530B2 (en) * 2011-06-16 2015-10-06 Broadcom Corporation Thermal enhanced high density flip chip package
US8513817B2 (en) 2011-07-12 2013-08-20 Invensas Corporation Memory module in a package
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
US8502390B2 (en) 2011-07-12 2013-08-06 Tessera, Inc. De-skewed multi-die packages
WO2013052080A1 (en) 2011-10-03 2013-04-11 Invensas Corporation Stub minimization for multi-die wirebond assemblies with orthogonal windows
US8659142B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization for wirebond assemblies without windows
US8659141B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
US8917532B2 (en) 2011-10-03 2014-12-23 Invensas Corporation Stub minimization with terminal grids offset from center of package
US8441111B2 (en) * 2011-10-03 2013-05-14 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
EP2764543A2 (en) 2011-10-03 2014-08-13 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8659140B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
US8525327B2 (en) 2011-10-03 2013-09-03 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
US8436457B2 (en) * 2011-10-03 2013-05-07 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
TWI528500B (zh) 2012-03-20 2016-04-01 鈺創科技股份有限公司 包裹式記憶體和用於製造具有一外部輸入輸出匯流排的包裹式記憶體 的製造方法
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
US8787034B2 (en) 2012-08-27 2014-07-22 Invensas Corporation Co-support system and microelectronic assembly
US8848392B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support module and microelectronic assembly
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US9019710B2 (en) 2012-10-11 2015-04-28 Apple Inc. Devices having flexible printed circuits with bent stiffeners
US9601557B2 (en) 2012-11-16 2017-03-21 Apple Inc. Flexible display
US20140191403A1 (en) * 2013-01-07 2014-07-10 Lsi Corporation Multi-die semiconductor package and method of manufacturing thereof
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
KR101416159B1 (ko) * 2013-09-06 2014-07-14 주식회사 기가레인 접촉 패드를 구비하는 인쇄회로기판
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US10153238B2 (en) * 2014-08-20 2018-12-11 Samsung Display Co., Ltd. Electrical channel including pattern voids
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
US9600112B2 (en) * 2014-10-10 2017-03-21 Apple Inc. Signal trace patterns for flexible substrates
US10154583B1 (en) 2015-03-27 2018-12-11 Flex Ltd Mechanical strain reduction on flexible and rigid-flexible circuits
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
US9992880B2 (en) 2015-11-12 2018-06-05 Multek Technologies Limited Rigid-bend printed circuit board fabrication
US9679613B1 (en) 2016-05-06 2017-06-13 Invensas Corporation TFD I/O partition for high-speed, high-density applications
KR102708773B1 (ko) 2016-12-26 2024-09-23 엘지디스플레이 주식회사 플렉서블 표시장치
TWI652983B (zh) * 2018-04-16 2019-03-01 緯創資通股份有限公司 電子裝置及電磁遮蔽裝置
KR102620865B1 (ko) * 2018-12-03 2024-01-04 에스케이하이닉스 주식회사 반도체 패키지
KR102538705B1 (ko) * 2018-12-04 2023-06-01 에스케이하이닉스 주식회사 반도체 패키지
JP6961784B1 (ja) * 2020-12-28 2021-11-05 日立Astemo株式会社 パワー半導体装置
US20230108475A1 (en) * 2021-10-04 2023-04-06 Formfactor, Inc. Thermal management techniques for high power integrated circuits operating in dry cryogenic environments
US12489061B2 (en) * 2022-06-27 2025-12-02 Texas Instruments Incorporated Semiconductor device with multiple dies

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5373188A (en) * 1992-11-04 1994-12-13 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor device including multiple semiconductor chips and cross-over lead
US5998860A (en) * 1997-12-19 1999-12-07 Texas Instruments Incorporated Double sided single inline memory module
US6214641B1 (en) * 1996-06-25 2001-04-10 Micron Technology, Inc. Method of fabricating a multi-chip module
US6249052B1 (en) * 1998-06-01 2001-06-19 Paul T. Lin Substrate on chip (SOC) multiple-chip module (MCM) with chip-size-package (CSP) ready configuration
US20010026008A1 (en) * 2000-03-24 2001-10-04 Kensuke Tsuneda Semiconductor device, a semiconductor module loaded with said semiconductor device and a method of manufacturing said semiconductor device
US20020059911A1 (en) * 2000-11-22 2002-05-23 Masayuki Takahashi Internal combustion engine
US20020081755A1 (en) * 2000-12-22 2002-06-27 Yinon Degani Method of testing and constructing monolithic multi-chip modules

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5423497A (en) * 1965-12-03 1995-06-13 Shorts Missile Systems Limited Control systems for moving bodies
DE3911711A1 (de) 1989-04-10 1990-10-11 Ibm Modul-aufbau mit integriertem halbleiterchip und chiptraeger
GB8918482D0 (en) 1989-08-14 1989-09-20 Inmos Ltd Packaging semiconductor chips
US5227338A (en) * 1990-04-30 1993-07-13 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US6219908B1 (en) 1991-06-04 2001-04-24 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US5243497A (en) 1992-09-29 1993-09-07 Texas Instruments Chip on board assembly
US5602421A (en) * 1995-01-31 1997-02-11 Hughes Aircraft Company Microwave monolithic integrated circuit package with improved RF ports
KR0177395B1 (ko) * 1995-04-27 1999-05-15 문정환 반도체소자를 칩 상태로 장착시켜서 된 전자회로 보드 및 그 제조방법
KR0144164B1 (ko) * 1995-05-12 1998-07-01 문정환 엘오씨 반도체 패키지 및 반도체 장치를 패키징하는 방법
US5818698A (en) * 1995-10-12 1998-10-06 Micron Technology, Inc. Method and apparatus for a chip-on-board semiconductor module
US6667560B2 (en) 1996-05-29 2003-12-23 Texas Instruments Incorporated Board on chip ball grid array
US5811879A (en) 1996-06-26 1998-09-22 Micron Technology, Inc. Stacked leads-over-chip multi-chip module
US6017776A (en) * 1997-04-29 2000-01-25 Micron Technology, Inc. Method of attaching a leadframe to singulated semiconductor dice
US5899705A (en) * 1997-11-20 1999-05-04 Akram; Salman Stacked leads-over chip multi-chip module
US6049129A (en) * 1997-12-19 2000-04-11 Texas Instruments Incorporated Chip size integrated circuit package
TW368707B (en) * 1998-10-27 1999-09-01 Tech Field Co Ltd Packaging method for semiconductor die and the product of the same
US6455354B1 (en) 1998-12-30 2002-09-24 Micron Technology, Inc. Method of fabricating tape attachment chip-on-board assemblies
US6351028B1 (en) * 1999-02-08 2002-02-26 Micron Technology, Inc. Multiple die stack apparatus employing T-shaped interposer elements
US6856013B1 (en) * 1999-02-19 2005-02-15 Micron Technology, Inc. Integrated circuit packages, ball-grid array integrated circuit packages and methods of packaging an integrated circuit
JP2000315776A (ja) 1999-05-06 2000-11-14 Hitachi Ltd 半導体装置
US6387732B1 (en) * 1999-06-18 2002-05-14 Micron Technology, Inc. Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip and packages formed thereby
US6825550B2 (en) * 1999-09-02 2004-11-30 Micron Technology, Inc. Board-on-chip packages with conductive foil on the chip surface
US6534861B1 (en) 1999-11-15 2003-03-18 Substrate Technologies Incorporated Ball grid substrate for lead-on-chip semiconductor package
KR20010064907A (ko) * 1999-12-20 2001-07-11 마이클 디. 오브라이언 와이어본딩 방법 및 이를 이용한 반도체패키지
US6404660B1 (en) 1999-12-23 2002-06-11 Rambus, Inc. Semiconductor package with a controlled impedance bus and method of forming same
JP2001223324A (ja) * 2000-02-10 2001-08-17 Mitsubishi Electric Corp 半導体装置
US6522018B1 (en) 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US6683377B1 (en) * 2000-05-30 2004-01-27 Amkor Technology, Inc. Multi-stacked memory package
KR100608608B1 (ko) * 2000-06-23 2006-08-09 삼성전자주식회사 혼합형 본딩패드 구조를 갖는 반도체 칩 패키지 및 그제조방법
JP2002074985A (ja) 2000-08-29 2002-03-15 Mitsubishi Electric Corp メモリモジュールおよびその製造方法ならびにそれに使用するテストコネクタ
US20020043709A1 (en) * 2000-10-13 2002-04-18 Yeh Nai Hua Stackable integrated circuit
US6680213B2 (en) * 2001-04-02 2004-01-20 Micron Technology, Inc. Method and system for fabricating contacts on semiconductor components
US6706624B1 (en) * 2001-10-31 2004-03-16 Lockheed Martin Corporation Method for making multichip module substrates by encapsulating electrical conductors
US6835592B2 (en) * 2002-05-24 2004-12-28 Micron Technology, Inc. Methods for molding a semiconductor die package with enhanced thermal conductivity
US6987031B2 (en) * 2002-08-27 2006-01-17 Micron Technology, Inc. Multiple chip semiconductor package and method of fabricating same
US7323772B2 (en) * 2002-08-28 2008-01-29 Micron Technology, Inc. Ball grid array structures and tape-based method of manufacturing same
US6879030B2 (en) * 2002-09-30 2005-04-12 Ultratera Corporation Strengthened window-type semiconductor package

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5373188A (en) * 1992-11-04 1994-12-13 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor device including multiple semiconductor chips and cross-over lead
US6214641B1 (en) * 1996-06-25 2001-04-10 Micron Technology, Inc. Method of fabricating a multi-chip module
US5998860A (en) * 1997-12-19 1999-12-07 Texas Instruments Incorporated Double sided single inline memory module
US6249052B1 (en) * 1998-06-01 2001-06-19 Paul T. Lin Substrate on chip (SOC) multiple-chip module (MCM) with chip-size-package (CSP) ready configuration
US20010026008A1 (en) * 2000-03-24 2001-10-04 Kensuke Tsuneda Semiconductor device, a semiconductor module loaded with said semiconductor device and a method of manufacturing said semiconductor device
US20020059911A1 (en) * 2000-11-22 2002-05-23 Masayuki Takahashi Internal combustion engine
US20020081755A1 (en) * 2000-12-22 2002-06-27 Yinon Degani Method of testing and constructing monolithic multi-chip modules

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107818799A (zh) * 2016-09-13 2018-03-20 希捷科技有限公司 具有背侧阻抗控制结构的柔性动态回路
CN107818799B (zh) * 2016-09-13 2021-03-12 希捷科技有限公司 具有背侧阻抗控制结构的柔性动态回路

Also Published As

Publication number Publication date
CN1742372A (zh) 2006-03-01
WO2004055895A1 (en) 2004-07-01
TW200425462A (en) 2004-11-16
KR101062260B1 (ko) 2011-09-06
TWI339435B (en) 2011-03-21
EP1573815A1 (en) 2005-09-14
JP2006510224A (ja) 2006-03-23
AU2003299608A1 (en) 2004-07-09
KR20050085561A (ko) 2005-08-29
JP4452627B2 (ja) 2010-04-21
US20040113250A1 (en) 2004-06-17
US7550842B2 (en) 2009-06-23

Similar Documents

Publication Publication Date Title
CN100530640C (zh) 集成电路组合件
JP2819285B2 (ja) 積層型ボトムリード半導体パッケージ
JP3105089B2 (ja) 半導体装置
KR101215283B1 (ko) 적어도 부분적인 패키징을 갖는 디바이스
US8869387B2 (en) Methods for making microelectronic die systems
US5828126A (en) Chip on board package with top and bottom terminals
US6268649B1 (en) Stackable ball grid array package
JP3499202B2 (ja) 半導体装置の製造方法
US6882034B2 (en) Routing element for use in multi-chip modules, multi-chip modules including the routing element, and methods
CN1113410C (zh) 一种集成电路封装组件和组装集成电路封装的方法
CN100477141C (zh) 半导体封装器件及其制造和测试方法
US6704609B1 (en) Multi-chip semiconductor module and manufacturing process thereof
US20040108581A1 (en) Assemblies having stacked semiconductor chips and methods of making same
US6407333B1 (en) Wafer level packaging
US20020027272A1 (en) Semiconductor device, semiconductor package for use therein, and manufacturing method thereof
JP2004063824A (ja) 半導体装置及びその製造方法
JPH047866A (ja) 混成集積回路装置
JP2002261231A (ja) 半導体装置および半導体装置の製造方法
JP2004063570A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090819

Termination date: 20111212