CN100530640C - 集成电路组合件 - Google Patents

集成电路组合件 Download PDF

Info

Publication number
CN100530640C
CN100530640C CNB2003801092161A CN200380109216A CN100530640C CN 100530640 C CN100530640 C CN 100530640C CN B2003801092161 A CNB2003801092161 A CN B2003801092161A CN 200380109216 A CN200380109216 A CN 200380109216A CN 100530640 C CN100530640 C CN 100530640C
Authority
CN
China
Prior art keywords
trace
circuit die
substrate
sub
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2003801092161A
Other languages
English (en)
Other versions
CN1742372A (zh
Inventor
伊戈尔·K·汉德罗斯
本杰明·N·埃尔德里奇
查尔斯·A·米勒
A·尼古拉斯·斯珀克
加里·W·格鲁比
加埃唐·L·马蒂厄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FormFactor Inc
Original Assignee
FormFactor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by FormFactor Inc filed Critical FormFactor Inc
Publication of CN1742372A publication Critical patent/CN1742372A/zh
Application granted granted Critical
Publication of CN100530640C publication Critical patent/CN100530640C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structure Of Printed Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

在一集成电路组合件中，在一衬底上装配已知优良电路小片(know-good-die，KGD)。互连元件将附着在所述衬底上的电路小片上的衬垫电连接至所述衬底上的迹线或其它电导体或连接至附着在所述衬底上的另一电路小片上的衬垫。所述衬底可具有一个或多个开口，以暴露所述电路小片的衬垫。所述组合件可包括一个或多个电路小片。

Description

集成电路组合件
技术领域
本发明涉及集成电路，且更具体而言，涉及在一衬底上使用已知优良电路管芯的集成电路。
背景技术
集成电路可包括一以机械方式附着并电连接至一芯片上引线(LOC)引线框的半导体电路管芯。所述电路管芯及引线框架通常被包封在一转模塑料封装、陶瓷封装或金属封装内。使用已知优良电路管芯(KGD)替代封装式电路管芯可提高制造效率且可降低成本。已知优良电路管芯(KGD)是已经受各种测试及/或老化且通常据认为与其它等效封装电路管芯具有相同质量及可靠性的未封装电路管芯。
人们所期望的是一种因使用已知优良电路管芯而提高了性能并使制造成本最小化的集成电路组合件及用于制造所述组合件的方法。
发明内容
一般而言，本发明提供一种在一衬底上使用已知优良电路管芯(KGD)的改进型集成电路组合件。互连元件将所述电路管芯上的衬垫电连接至迹线或其它电导体或连接至另一电路管芯上的衬垫。
附图说明
图1是一根据本发明一实施例的集成电路组合件10的平面图。
图2是一沿线2-2截取且从箭头方向观看的图1中集成电路组合件10的横截面侧视图。
图3是一图1中集成电路组合件10的一替代实施例的横截面侧视图。
图4是一根据本发明另一实施例的集成电路组合件40的平面视图。
图5是一沿线5-5截取且从箭头方向观看的图4中集成电路组合件40的横截面侧视图。
图6是一根据本发明另一实施例的集成电路组合件47的平面视图。
图7是一沿线7-7截取且从箭头方向观看的图6中集成电路组合件47的横截面侧视图。
图8是一图6中集成电路组合件47的仰视图。
图9是一根据本发明另一实施例的集成电路组合件76的横截面侧视图。
图10是一根据本发明另一实施例的集成电路组合件82的横截面侧视图。
图11是一根据本发明另一实施例的集成电路组合件95的平面视图。
图12是一根据本发明另一实施例的集成电路组合件105的平面视图。
图13是一沿线13-13截取且从箭头方向观看的图12中集成电路组合件105的横截面侧视图。
图14是一根据本发明另一实施例的集成电路组合件113的横截面侧视图。
图15-20是根据本发明其他实施例的数个集成电路组合件的横截面侧视图。
图21图解说明添加一与导电迹线及互连元件绝缘隔离的一导电平面以用于控制所述导电迹线及互连元件的阻抗。
图22图解说明一包括不同类型的互连集成电路的系统的组合件的俯视图。
图23图解说明图22中的所述组合件的一侧视图。
图24图解说明一其中互连从一集成电路直接连接至另一集成电路的组合件的俯视图。
图25图解说明图24中的所述组合件的一横截面侧视图。
图26图解说明一本发明实施例的俯视图，其中互连从一电路管芯上的端子接合至一衬底中的通孔。
图27图解说明图26中的所述组合件的一横截面侧视图。
具体实施方式
出于促进了解本发明原理的目的，现在，下文将参照附图中所图解说明的实施例并使用特定语言来阐述这些实施例。然而，应理解：本文并非意欲借此来限制本发明的范围，而是涵盖本发明所属领域的技术人员在正常情况下将会构想出的所说明装置的任何改变或修改及本文所示的本发明原理的任何其它应用。
参照图1及2，图中显示一根据本发明一实施例的集成电路组合件10。组合件10大体包括一衬底11、多个电路管芯(优选先前经过测试的已知优良电路管芯(KGD))12-15、及互连器(诸如多个接合导线18)。衬底19可以是适用于一电路管芯组合件的任何衬底，包括(但不限于)印刷电路板、陶瓷、塑料、挠性电路等。应注意，在将所有集成电路最终装配在所述衬底上之前或之后，可研磨或抛光衬底19以使所述衬底变薄。迹线21以各种组合形式形成一总线以便为与衬底19相连接的一个或多个KGS提供电力、接地及诸如数据、地址、控制等信号。衬底19限定多个在多个位置中断迹线21的间隔开口23-26。所述开口可具有不同的大小及形状，且可被所述衬底完全环绕或仅部分地环绕或围绕其周边界定。如图所示，某些迹线21由此在相邻组的开口23-26之间延伸，且被称作中心迹线27。多组迹线(即，在开口24与25之间延伸的含五个迹线的迹线组或从开口23敷设且由此向外延伸的含五个迹线的迹线组)最好并排敷设、基本上平行且长度大体上相同。可将一边缘加强件28连接至或施加至衬底19的一充足部分以给衬底提供强度。在图1的实施例中，如图所示，边缘加强件28包括一对环绕衬底19的周边的配对金属条(一个在上，一个在下)。某些迹线21在衬底19的一边缘处向衬底19的外侧延伸以形成用于向外连接至一更高级电路的连接器29。在衬底19的一边缘处向外延伸的迹线称为边缘迹线30。边缘迹线30延伸穿过加强件28。加强件28的大小及配置可使其充当散热器。其可为任何大小、形状或构成，包括杆、板、周边框架(完整的或部分的)或其他形式。如果衬底19较薄(例如，一诸如挠性电路材料的挠性薄膜)，则加强件28有助于原本会因电路管芯的重量而挠曲的其他挠性薄膜衬底维持一大体上平面的配置。然而，如上所述，挠性仅是衬底的一个实例。如果使用一更刚性的衬底(例如，印刷电路板材料)，则可不需要加强件。
如同以引用的方式并入本文中的第6,214,641B1及6,219,908B1号美国专利中所论述，已知优良电路管芯意指已经过测试及/或老化且因此据认为与其他等效封装式电路管芯具有相同的总体质量及可靠性的非封装电路管芯。可将所述已知优良电路管芯固定至一衬底上，以形成一在计算机、电信装置、车辆、手表、仪器及似乎无限制的各种各样的其它电子装置中使用的多芯片模块。在图1的组合件10中，每一个已知优良电路管芯12-15均包括一个或多个电电路管芯触点或电路管芯衬垫31。每一电路管芯衬垫31均可用作其已知优良电路管芯的电连接点(例如，用于接地、电力及信号连接)。取决于特定电路管芯的设计，所述电路管芯垫可采用任何适合的形式及数量。已知优良电路管芯12-15被固定至衬底19的底侧32(如在图2中所见)，以便可将电路管芯衬垫31设置于相应的开口23-26内，也就是说，可从衬底19的上表面经过开口接近电路管芯衬垫31。可通过任何标准及合适的手段(例如使用粘合剂33)将已知优良电路管芯12-15固定至衬底19。如果使用标准的接合技术，将导线18从迹线21接合至电路管芯衬垫31及/或从一个迹线末端36接合至另一迹线末端37以跨越一个开口24。在邻近于开口23-26处，可扩大每一迹线末端(即36及37)以方便导线接合，且优选在此类迹线末端处接合导线。然而，本发明涵盖可视需要或期望在沿一迹线的任何一点接合一个或多个导线18以达成一特定电配置。
图3显示一替代实施例，其中加强件材料39(及散热器)仅被施加至衬底19(在此实例中，所述衬底是一挠性电路)的底部电路管芯侧，且其中所述挠性电路延伸并包绕其自身或包绕其外部边缘34处的一小的插入衬底(未显示)，以为连接至一更高级电路提供一替代连接表面。
参照图4及5，图中显示根据一替代实施例的集成电路组合件40，其中有两层迹线21及41被安装至衬底19。迹线41通道被嵌入绝缘层42中，绝缘层42使迹线21与41电分离。如同在图1的实施例中，上层迹线21沿纵向延伸，而下层迹线41沿横向延伸或通常垂直于迹线21延伸。迹线41的外侧末端随同并在衬底19的一部分的顶部上向衬底19及加强件44的外侧延伸，以形成连接器43。通孔46延伸穿过衬底19以提供上部纵向迹线21与下部横向迹线41之间的连接。可在衬底19的任何部分中提供此类纵向及横向水平迹线与垂直通孔，以产生精致的多层电路配置。例如，连续的纵向迹线可敷设在衬底19中开口23-26上面及/或下面的一个层内，而垂直通孔则可敷设在开口之间从纵向迹线到表面区域的另一个层中，通过所述开口，导线可从通孔接合至电路管芯衬垫。横向迹线被描述为通常垂直于纵向迹线21敷设。然而，第二下部迹线21应以一与上部迹线21非成九十度的角度延伸且可相互不平行。所述第二迹线层(及可能的第三及第四迹线层等)必须完全与第一上部迹线层互不相干。
参照图6-8，图中显示根据另一替代实施例的集成电路组合件47，其中衬底48具有多个层。总线迹线49(图7及图6中的部分剖视图中所示的一个)被嵌入衬底48内且类似迹线21被开口50-53截断。大多数迹线49的末端均各自延伸至开口50-53中的一个内，以形成接合尖端55。在一末端56处，迹线49在衬底48的一部分上向外延伸以形成用于连接至一更高级电路的连接器57。如同集成电路组合件10，可将导线64从接合尖端55接合到安装在衬底48底侧上的已知优良电路管芯60-63的电路管芯衬垫58，或从一接合接头55接合到另一接合接头55。组合件47进一步分别配备有在衬底48顶部及沿其长度延伸的接地及电力平面迹线66及67。接地及电力迹线66及67可由通孔连接并连接至衬底48内(如图中在69处针对接地迹线66所显示)，每一迹线与一相应的横向迹线49相连接，以形成横向的嵌入接地及电力迹线(仅显示接地迹线70)。在衬底48的末端56处，接地及电力迹线向衬底48外侧延伸以形成接地及电力连接器72及73，以用于连接至一更高级的电路。
可在或靠近总线的终端处设置任选电阻器(以任何形式)以防止或减小信号反射。所述电阻器可通过一接合导线或其它互连元件连接至一迹线。所述电阻器可视情况接地。同样，可将导线、迹线、屏蔽、薄膜或其它元件定位在迹线之间或周围，以防止或减小所述组合件内迹线或其它导体之间或中间的电或其它信号干扰。
本发明涵盖多个其中接地及电力平面迹线66及67向下弯转至衬底48内(如在69处)且随后在末端56处直接向外弯转并脱离衬底48以形成接地及电力连接器72及73及无接地或电力迹线70或71的替代实施例。
本发明涵盖多个其中端接在边缘连接器71及72中的接地及电力迹线70及71仅提供接地及电力而不设置接地或电力平面迹线66及67的替代实施例。
本发明涵盖多个其中在具有或不具有嵌入式接地及/或电力70及71迹线的情况下用总线迹线(如图1中的迹线21)替代接地及电力平面迹线66及67的替代实施例。
本发明涵盖多个其中在衬底48的外表面上设置总线迹线(如图1及本文其它附图中的迹线21)且所述总线迹线可使用接合至其的导线进行连接以视需要提供电力、接地或信号的替代实施例。替代或除了本文所述的任一嵌入式迹线或表面平面之外，可提供此等表面安装式总线迹线。
参照图9，图中显示一替代实施例的集成电路组合件76，其中已知优良电路管芯77-80安装在衬底81的两侧上。
参照图10，图中显示一替代实施例的集成电路组合件82，其中如同图1及图2中的组合件10，总线迹线83表面安装在一衬底84上。已知优良电路管芯86-89表面安装在衬底84的相对侧上，其中至少一个已知优良电路管芯直接安装在经表面安装的迹线83的顶部上。为容纳安装于其上的已知优良电路管芯87及89，如图所示，某些迹线83延伸至对应的开口91及92内，以允许将导线93接合至所述迹线。或者，如关于图4及图5的集成电路组合件40所述，可使用多级迹线。举例而言，连续的水平迹线可敷设在所述衬底中的开口上面及/或下面的一个层内，而垂直迹线可敷设在另一个层内，其从水平迹线延伸并进入各开口之间的区域中，通过所述开口可将接合导线从垂直迹线接合至电路管芯衬垫。此迹线布置可设置在所述衬底的一侧或两侧上。
参照图11，图中显示一替代实施例的集成电路组合件95，其中多个边缘迹线96从外部开口向外延伸、沿所述衬底包绕至一中间点并从此处沿侧边缘向外延伸以形成侧边缘连接器97。
本发明涵盖多个其中将图1-11中所揭示的实施例的各个方面以未具体揭示的组合形式进行组合的实施例。举例而言(但不具限制性)，图11的实施例可包括安装在所述衬底的顶部及底部表面上的已知优良电路管芯及/或可包括两个或两个以上的不同迹线层。本发明涵盖多个其中在及/或围绕所述衬底施加各种形式的加强件、覆盖物及/或其它适合的保护材料(例如，美国专利第6,214,641号中所揭示的非导电性球形顶部66，此专利以引用的方式并入本文中)以加强并保护所述衬底、已知优良电路管芯(KGD)、迹线、布线等的实施例。本发明涵盖多个其中衬底是由任何适合支持已知优良电路管芯(KGD)、布线及相关的组件并承受所设想的处理及任何磨损的材料组成的实施例。此类材料包括(但不限于)：挠性材料、硅、陶瓷、环氧树脂、聚酰胺、聚四氟乙烯、含氟聚合物及其它有机或介电材料。
参照图12及13，图中显示一集成电路组合件105的实例性配置，其中图中显示迹线106经接线以用作一总线。也就是说，通过使用导线109将每一迹线末端(例如，107)连接至一电路管芯衬垫108且随后使用另一导线109将其连接至下一迹线末端(例如，110)来形成一总线。
参照图14，图中显示一替代实施例的集成电路组合件113，其中如同电路组合件105，迹线经布线以用作一总线。在每一对相邻的开口之间(例如，114与115)，通过一通孔118将衬底117顶部上的迹线116连接至薄膜117底部上的迹线119。如图所示，可以交替方式将已知优良电路管芯安装在薄膜117的顶部及底部上并通过导线121、上部迹线116、通孔118、下部迹线119及另一导线121将一个已知优良电路管芯123的电路管芯衬垫120连接至相邻已知优良电路管芯124的电路管芯衬垫120。可实质上沿一共用总线以此方式布线所有的已知优良电路管芯123-126。或者，可以任何期望的方式将具有互连通孔118的交替迹线配置(即，116与119)连接至所述已知优良电路管芯，无论其是一连续总线或是其它总线。本发明涵盖一其中一接地平面以类似于图7中接地迹线70的方式在衬底19的顶部与底部表面之间被嵌入衬底19的替代实施例。所述接地平面可用来控制通孔及迹线的阻抗。所述接地平面可被制作成任一期望的形状。例如，可将其制成如图6中的迹线49那样狭窄或制作成与衬底19的整个宽度那样宽或制作成其中间的任一宽度或形状。所述接地平面可包括数个其内可延伸穿过一个或多个通孔118的绝缘开口。一个或多个迹线可与所述接地平面相连接。
参照图15，图中显示一替代实施例的集成电路组合件132，其类似于图5中的电路组合件40，其区别之处在于：横向延伸迹线134嵌入衬底19内且延伸并视需要通过通孔136与纵向延伸的上部迹线层135相连接外。
本文所述实施例已包括导线(例如，图1中的导线18)作为互连器以将迹线连接至电路管芯衬垫或其它迹线。如本文中所使用，互连器包括适合在一个电电路管芯触点或迹线与另一电电路管芯触点或迹线之间提供电连接的任何装置、材料或元件。本发明涵盖其它互连器及应用所述互连器的方法，例如但不限于：以微影法铺设导电性聚合物、粘合剂或环氧树脂，及使用一掩蔽屏或一分配器。图16-17中显示进一步的替代实施例。在图16中所示的电路组合件139中，使用超声波接合法将一带状迹线140从一迹线141施加至另一迹线142。在图17中，可将带状迹线140从一迹线141向下施加至一电路管芯衬垫143并向后施加至相对的相邻迹线142。
在图18-20中，图中显示一替代电路组合件147，其中将带状迹线148沿衬底19的长度直接铺设在各个开口151及152上。随后，根据需要，使用包括导线接合在内的任一适合的方法及本文所讨论的其它方法将带状迹线148接合至下面的电路管芯衬垫153。本发明涵盖将一带状迹线148连接至一电路管芯衬垫153的其它方法，例如，施加一导电球154(图19)或随着施加带状迹线148(图20)或在施加带状迹线148(如图18所示)之后初始形成一凸块155，然后，在电路管芯衬垫位置处使带状迹线148变形进入导电凸块155(图20)。或者，可将凸块或球直接形成在电路管芯衬垫153上期望建立与一迹线的连接的地方(优选在将电路管芯粘附至衬底之前)。
图21图解说明图17的结构具有一沉积在迹线141及互连元件140上的一第一绝缘材料160。导电层162沉积在第一绝缘材料160上，而第二绝缘材料164沉积在所述导电层上。导电层162可接地或连接至一电压源以控制迹线141及互连元件140的阻抗。或者，导电层162可不接地或不连接至一电压源但可仅屏蔽迹线414、互连元件140及电路管芯123。当然，层160、162及164可包封所述组合件结构的一部分或甚至全部。在再一替代方案中，导电层162可为一附着至衬底117的金属壳体。在此情况下，可省去层164，而层160可为空气。当然，可将类似的层160、162、164施加至本文所述的任一实施例。
图22及23图解说明一其中通过一焊锡球218将一微处理器连接至迹线210的实施例。如图22及23所示，四个存储电路管芯204通过互连元件214及迹线210连接至微处理器202。当然，图22及23仅图解说明一其中装配不同类型的电路管芯形成一电子系统的系统的实施例。可装配及互连射频电路管芯、模拟电路管芯、逻辑电路管芯或任一其它类型的电路管芯来形成所述系统。
图24及25图解说明一其中电路管芯304被粘附至一衬底306表面的实施例。迹线310从一连接边缘320敷设至电路管芯304附近的空间。互连元件314将电路管芯304上的端子316连接至迹线310。此外，某些互连元件320将一电路管芯304上的端子316直接连接至另一电路管芯上的一端子316。
图26及27图解说明再一实施例，其中衬底406中开口408之间的迹线410被设置在衬底的底侧上(即，迹线404所粘附的一侧)。如图26及27中所示，互连元件414将电路管芯404上的端子416连接至穿过衬底406通至迹线410的通孔420。
尽管附图及上述说明中已详细图解说明并阐述了本发明，但此等图解说明及阐述应被视为仅具有说明性而不具有限制性，应了解，本文仅显示及阐述了优选实施例并且欲保护属于本发明精神范围内的所有改变及修改。冠词“一(a)”、“一(an)”、“所述(said)”、“该(the)”不限于一单数元件，而包括一个或多个此类元件。

Claims (35)

1、一种集成电路组合件，其包括：
一衬底；
一穿过所述衬底的第一开口；
一附着至所述衬底且具有定位于所述开口内的一第一电路管芯触点的第一电路管芯；
一附着至所述衬底的第一迹线；
一附着至所述衬底的第二迹线；及
一在所述第一开口上延伸且连接所述第一迹线与所述第二迹线的第一互连器，
其中所述第一互连器包括一导线，所述导线的一第一端接合至所述第一迹线且所述导线的一第二端接合至所述第二迹线。
2、根据权利要求1所述的组合件，其中所述导线也接合至所述第一电路管芯触点。
3、根据权利要求1所述的组合件，其中所述第一互连器包括：
一接合至所述第一迹线及所述第一电路管芯触点的第一导线；及
一接合至所述第二迹线及所述第一电路管芯触点的第二导线。
4、根据权利要求1所述的组合件，其中所述第一迹线嵌入所述衬底内且从所述衬底伸入所述第一开口中。
5、根据权利要求4所述的组合件，其中所述第二迹线嵌入所述衬底内且从所述衬底伸入所述第一开口中。
6、根据权利要求1所述的组合件，其中所述衬底包括一薄的挠性薄膜。
7、根据权利要求1所述的组合件，其中所述衬底进一步包括一第二开口，所述组合件进一步包括：
一附着至所述衬底且具有定位于所述第二开口内的一第二电路管芯触点的第二电路管芯；及
一将所述第二电路管芯触点连接至所述第二迹线的第二互连器。
8、根据权利要求7所述的组合件，其中所述第一电路管芯及所述第二电路管芯在所述衬底的相对侧上附着至所述衬底。
9、根据权利要求1所述的组合件，其进一步包括用于电屏蔽所述第一迹线、所述第二迹线及所述第一互连器的构件。
10、根据权利要求1所述的组合件，其进一步包括用于控制所述第一迹线、所述第二迹线及所述第一互连器的阻抗的构件。
11、根据权利要求1所述的组合件，其进一步包括靠近所述第一迹线及所述第二迹线中的一个迹线的一终端的电阻器构件。
12、根据权利要求1所述的组合件，其中所述第一电路管芯未封装。
13、一种集成电路组合件，其包括：
一衬底；
一在所述衬底内的第一开口；
一附着至所述衬底且具有定位于所述第一开口内的一第一电路管芯触点的第一电路管芯；
一嵌入所述衬底内并从所述衬底伸入所述第一开口中的迹线；及
一将所述第一电路管芯触点连接至所述迹线的第一互连器。
14、根据权利要求13所述的组合件，其中所述第一互连器是一接合至所述第一电路管芯触点及所述迹线的导线。
15、根据权利要求13所述的组合件，其中所述衬底包括一第二开口，且所述迹线也伸入所述第二开口中，所述组合件进一步包括：
一附着至所述衬底且具有定位于所述第二开口中的一第二电路管芯触点的第二电路管芯；及
一将所述第二电路管芯触点连接至所述迹线的第二互连器。
16、根据权利要求15所述的组合件，其中：
所述第一电路管芯包括多个所述第一电路管芯触点，每一第一电路管芯触点均定位于所述第一开口内；且
所述第二电路管芯包括多个所述第二电路管芯触点，每一第二电路管芯触点均定位于所述第二开口内；
所述组合件进一步包括：
多个嵌入所述衬底中并从所述衬底伸入所述第一开口内且伸入所述第二开口内的所述迹线；
多个所述第一互连器，每一第一互连器均将所述迹线中的一个迹线连接至所述第一电路管芯触点中的一个触点；及
多个所述第二互连器，每一第二互连器均将所述迹线中的一个迹线连接至所述第二电路管芯触点中的一个触点。
17、一种集成电路组合件，其包括：
一包含多个迹线的衬底；
多个附着至所述衬底的电路管芯；及
多个导电接合导线，所述导线中的某些导线的每一者都在所述导线的一第一端接合至所述迹线的一者，且在所述导线的一第二端接合至所述电路管芯的一者，
其中在所述电路管芯之间形成了电互连，所述电互连包括所述迹线及所述接合导线。
18、根据权利要求17所述的组合件，其中所述接合导线经专门设置以定制所述迹线与电路管芯中的互连。
19、根据权利要求17所述的组合件，其中所述迹线及所述接合导线形成一总线结构。
20、一种用于多个电路管芯的集成电路组合件，其包括：
一衬底；
一在所述衬底内的第一开口；
一在所述衬底内的第二开口；
一附着至所述衬底且具有定位于所述第一开口内的一第一电路管芯触点的第一电路管芯；
一附着至所述衬底且具有定位于所述第二开口内的一第二电路管芯触点的第二电路管芯；
一附着至所述衬底的第一迹线；
一连接所述第一迹线与所述第一电路管芯触点的第一互连器；及
一连接所述第一迹线与所述第二电路管芯触点的第二互连器，
其中所述第一互连器包括一导线，所述导线的一第一端结合至所述第一迹线且所述导线的一第二端接合至所述第二迹线，
其中所述第二互连器包括一第二导线，所述第二导线的一第一端接合至所述第一迹线且所述第二导线的一第二端接合至所述第二电路管芯触点。
21、根据权利要求20所述的组合件，其中：
所述第一电路管芯包括多个所述第一电路管芯触点，每一第一电路管芯触点均定位于所述第一开口内；及
所述第二电路管芯包括多个所述第二电路管芯触点，每一第二电路管芯触点均定位于所述第二开口内；
所述组合件进一步包括：
多个附着至所述衬底的所述第一迹线；
多个所述第一互连器，每一第一互连器将所述第一迹线中的一个迹线
连接至所述第一电路管芯触点中的一个触点；及
多个所述第二互连器，每一第二互连器将所述第一迹线中的一个迹线
连接至所述第二电路管芯触点中的一个触点。
22、根据权利要求21所述的组合件，其中所述多个第一迹线中的每一个迹线均平行。
23、根据权利要求21所述的组合件，其中所述多个第一迹线中的每一个迹线的长度均相等。
24、根据权利要求21所述的组合件，其中所述多个第一迹线中的每一个迹线均具有相同的阻抗。
25、根据权利要求20所述的组合件，其进一步包括：
一附着至所述衬底的第三电路管芯；及
用于将所述第三电路管芯电连接至所述第一电路管芯触点、所述第二电路管芯触点及所述第一迹线中的至少一个的构件。
26、根据权利要求25所述的组合件，其中所述第一电路管芯、所述第二电路管芯及所述第三电路管芯中的至少一个包括一集成电路，所述集成电路不同于所述第一电路管芯、所述第二电路管芯及所述第三电路管芯中的所述其它电路管芯的一集成电路。
27、根据权利要求25所述的组合件，其中所述第一电路管芯及所述第二电路管芯包括数字存储器电路，而所述第三电路管芯包括一微处理器电路。
28、根据权利要求20所述的组合件，其中所述第一电路管芯包括一不同于所述第二电路管芯的一集成电路的集成电路。
29、根据权利要求20所述的组合件，其中所述第一电路管芯包括一数字存储器电路，而所述第二电路管芯包括一微处理器电路。
30、根据权利要求20所述的组合件，其中所述第一迹线嵌入所述衬底内且从所述衬底伸入所述第一开口中。
31、根据权利要求20所述的组合件，其中所述第一电路管芯及所述第二电路管芯在所述衬底的相对侧上附着至所述衬底。
32、根据权利要求20所述的组合件，其中所述衬底包括一薄的挠性衬底薄膜。
33、根据权利要求20所述的组合件，其进一步包括用于电屏蔽所述第一迹线、所述第一互连器及所述第二互连器的构件。
34、根据权利要求20所述的组合件，其进一步包括用于控制所述第一迹线、所述第一互连器及所述第二互连器的阻抗的构件。
35、根据权利要求20所述的组合件，其中所述第一电路管芯及所述第二电路管芯均未封装。
CNB2003801092161A 2002-12-12 2003-12-12 集成电路组合件 Expired - Fee Related CN100530640C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/317,661 US7550842B2 (en) 2002-12-12 2002-12-12 Integrated circuit assembly
US10/317,661 2002-12-12

Publications (2)

Publication Number Publication Date
CN1742372A CN1742372A (zh) 2006-03-01
CN100530640C true CN100530640C (zh) 2009-08-19

Family

ID=32506187

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2003801092161A Expired - Fee Related CN100530640C (zh) 2002-12-12 2003-12-12 集成电路组合件

Country Status (8)

Country Link
US (1) US7550842B2 (zh)
EP (1) EP1573815A1 (zh)
JP (1) JP4452627B2 (zh)
KR (1) KR101062260B1 (zh)
CN (1) CN100530640C (zh)
AU (1) AU2003299608A1 (zh)
TW (1) TWI339435B (zh)
WO (1) WO2004055895A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107818799A (zh) * 2016-09-13 2018-03-20 希捷科技有限公司 具有背侧阻抗控制结构的柔性动态回路

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005524239A (ja) * 2002-04-29 2005-08-11 シリコン・パイプ・インコーポレーテッド ダイレクト・コネクト形信号システム
US7750446B2 (en) 2002-04-29 2010-07-06 Interconnect Portfolio Llc IC package structures having separate circuit interconnection structures and assemblies constructed thereof
US8324725B2 (en) * 2004-09-27 2012-12-04 Formfactor, Inc. Stacked die module
US7663216B2 (en) 2005-11-02 2010-02-16 Sandisk Corporation High density three dimensional semiconductor die package
US20070241441A1 (en) * 2006-04-17 2007-10-18 Stats Chippac Ltd. Multichip package system
US7569421B2 (en) * 2007-05-04 2009-08-04 Stats Chippac, Ltd. Through-hole via on saw streets
US7723157B2 (en) * 2007-12-28 2010-05-25 Walton Advanced Engineering, Inc. Method for cutting and molding in small windows to fabricate semiconductor packages
TWI370714B (en) * 2008-01-09 2012-08-11 Ind Tech Res Inst Circuit structure and menufacturing method thereof
US7643305B2 (en) * 2008-03-07 2010-01-05 Qualcomm Mems Technologies, Inc. System and method of preventing damage to metal traces of flexible printed circuits
JP2010287733A (ja) * 2009-06-11 2010-12-24 Elpida Memory Inc 半導体装置
KR20110082643A (ko) * 2010-01-12 2011-07-20 삼성전자주식회사 반도체 칩의 실장 기판 및 이를 갖는 반도체 패키지
JP2011155203A (ja) * 2010-01-28 2011-08-11 Elpida Memory Inc 半導体装置
US9136197B2 (en) 2010-09-16 2015-09-15 Tessera, Inc. Impedence controlled packages with metal sheet or 2-layer RDL
US8786083B2 (en) * 2010-09-16 2014-07-22 Tessera, Inc. Impedance controlled packages with metal sheet or 2-layer RDL
US9153530B2 (en) * 2011-06-16 2015-10-06 Broadcom Corporation Thermal enhanced high density flip chip package
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
US8513817B2 (en) 2011-07-12 2013-08-20 Invensas Corporation Memory module in a package
US8502390B2 (en) 2011-07-12 2013-08-06 Tessera, Inc. De-skewed multi-die packages
JP5947904B2 (ja) 2011-10-03 2016-07-06 インヴェンサス・コーポレイション 直交するウインドウを有するマルチダイ・ワイヤボンド・アセンブリのためのスタブ最小化
US8629545B2 (en) 2011-10-03 2014-01-14 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
US8436457B2 (en) * 2011-10-03 2013-05-07 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8441111B2 (en) * 2011-10-03 2013-05-14 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
JP5887414B2 (ja) 2011-10-03 2016-03-16 インヴェンサス・コーポレイション 平行な窓を有するマルチダイのワイヤボンドアセンブリのスタブ最小化
US8659142B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization for wirebond assemblies without windows
EP2766928A1 (en) 2011-10-03 2014-08-20 Invensas Corporation Stub minimization with terminal grids offset from center of package
US8513813B2 (en) 2011-10-03 2013-08-20 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
US8436477B2 (en) 2011-10-03 2013-05-07 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
TWI528500B (zh) * 2012-03-20 2016-04-01 鈺創科技股份有限公司 包裹式記憶體和用於製造具有一外部輸入輸出匯流排的包裹式記憶體 的製造方法
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US8848392B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support module and microelectronic assembly
US8787034B2 (en) 2012-08-27 2014-07-22 Invensas Corporation Co-support system and microelectronic assembly
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
US9019710B2 (en) 2012-10-11 2015-04-28 Apple Inc. Devices having flexible printed circuits with bent stiffeners
US9601557B2 (en) 2012-11-16 2017-03-21 Apple Inc. Flexible display
US20140191403A1 (en) * 2013-01-07 2014-07-10 Lsi Corporation Multi-die semiconductor package and method of manufacturing thereof
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
KR101416159B1 (ko) * 2013-09-06 2014-07-14 주식회사 기가레인 접촉 패드를 구비하는 인쇄회로기판
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US10153238B2 (en) * 2014-08-20 2018-12-11 Samsung Display Co., Ltd. Electrical channel including pattern voids
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
US9600112B2 (en) * 2014-10-10 2017-03-21 Apple Inc. Signal trace patterns for flexible substrates
US10154583B1 (en) 2015-03-27 2018-12-11 Flex Ltd Mechanical strain reduction on flexible and rigid-flexible circuits
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
US9992880B2 (en) 2015-11-12 2018-06-05 Multek Technologies Limited Rigid-bend printed circuit board fabrication
US9679613B1 (en) 2016-05-06 2017-06-13 Invensas Corporation TFD I/O partition for high-speed, high-density applications
KR20180075733A (ko) 2016-12-26 2018-07-05 엘지디스플레이 주식회사 플렉서블 표시장치
TWI652983B (zh) 2018-04-16 2019-03-01 緯創資通股份有限公司 電子裝置及電磁遮蔽裝置
KR102620865B1 (ko) * 2018-12-03 2024-01-04 에스케이하이닉스 주식회사 반도체 패키지
KR102538705B1 (ko) * 2018-12-04 2023-06-01 에스케이하이닉스 주식회사 반도체 패키지
US20230108475A1 (en) * 2021-10-04 2023-04-06 Formfactor, Inc. Thermal management techniques for high power integrated circuits operating in dry cryogenic environments

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5423497A (en) * 1965-12-03 1995-06-13 Shorts Missile Systems Limited Control systems for moving bodies
DE3911711A1 (de) * 1989-04-10 1990-10-11 Ibm Modul-aufbau mit integriertem halbleiterchip und chiptraeger
GB8918482D0 (en) 1989-08-14 1989-09-20 Inmos Ltd Packaging semiconductor chips
US5227338A (en) * 1990-04-30 1993-07-13 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US6219908B1 (en) * 1991-06-04 2001-04-24 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US5243497A (en) 1992-09-29 1993-09-07 Texas Instruments Chip on board assembly
JPH06151685A (ja) * 1992-11-04 1994-05-31 Mitsubishi Electric Corp Ｍｃｐ半導体装置
US5602421A (en) * 1995-01-31 1997-02-11 Hughes Aircraft Company Microwave monolithic integrated circuit package with improved RF ports
KR0177395B1 (ko) * 1995-04-27 1999-05-15 문정환 반도체소자를 칩 상태로 장착시켜서 된 전자회로 보드 및 그 제조방법
KR0144164B1 (ko) * 1995-05-12 1998-07-01 문정환 엘오씨 반도체 패키지 및 반도체 장치를 패키징하는 방법
US5818698A (en) * 1995-10-12 1998-10-06 Micron Technology, Inc. Method and apparatus for a chip-on-board semiconductor module
US6667560B2 (en) * 1996-05-29 2003-12-23 Texas Instruments Incorporated Board on chip ball grid array
US5723907A (en) * 1996-06-25 1998-03-03 Micron Technology, Inc. Loc simm
US5811879A (en) * 1996-06-26 1998-09-22 Micron Technology, Inc. Stacked leads-over-chip multi-chip module
US6017776A (en) * 1997-04-29 2000-01-25 Micron Technology, Inc. Method of attaching a leadframe to singulated semiconductor dice
US5899705A (en) * 1997-11-20 1999-05-04 Akram; Salman Stacked leads-over chip multi-chip module
US5998860A (en) * 1997-12-19 1999-12-07 Texas Instruments Incorporated Double sided single inline memory module
US6049129A (en) * 1997-12-19 2000-04-11 Texas Instruments Incorporated Chip size integrated circuit package
US6249052B1 (en) * 1998-06-01 2001-06-19 Paul T. Lin Substrate on chip (SOC) multiple-chip module (MCM) with chip-size-package (CSP) ready configuration
TW368707B (en) * 1998-10-27 1999-09-01 Tech Field Co Ltd Packaging method for semiconductor die and the product of the same
US6455354B1 (en) * 1998-12-30 2002-09-24 Micron Technology, Inc. Method of fabricating tape attachment chip-on-board assemblies
US6351028B1 (en) * 1999-02-08 2002-02-26 Micron Technology, Inc. Multiple die stack apparatus employing T-shaped interposer elements
US6856013B1 (en) * 1999-02-19 2005-02-15 Micron Technology, Inc. Integrated circuit packages, ball-grid array integrated circuit packages and methods of packaging an integrated circuit
JP2000315776A (ja) 1999-05-06 2000-11-14 Hitachi Ltd 半導体装置
US6387732B1 (en) * 1999-06-18 2002-05-14 Micron Technology, Inc. Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip and packages formed thereby
US6825550B2 (en) * 1999-09-02 2004-11-30 Micron Technology, Inc. Board-on-chip packages with conductive foil on the chip surface
US6534861B1 (en) * 1999-11-15 2003-03-18 Substrate Technologies Incorporated Ball grid substrate for lead-on-chip semiconductor package
KR20010064907A (ko) * 1999-12-20 2001-07-11 마이클 디. 오브라이언 와이어본딩 방법 및 이를 이용한 반도체패키지
US6404660B1 (en) * 1999-12-23 2002-06-11 Rambus, Inc. Semiconductor package with a controlled impedance bus and method of forming same
JP2001223324A (ja) * 2000-02-10 2001-08-17 Mitsubishi Electric Corp 半導体装置
JP2001274323A (ja) * 2000-03-24 2001-10-05 Hitachi Ltd 半導体装置とそれを搭載した半導体モジュール、および半導体装置の製造方法
US6522018B1 (en) * 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US6683377B1 (en) * 2000-05-30 2004-01-27 Amkor Technology, Inc. Multi-stacked memory package
KR100608608B1 (ko) * 2000-06-23 2006-08-09 삼성전자주식회사 혼합형 본딩패드 구조를 갖는 반도체 칩 패키지 및 그제조방법
JP2002074985A (ja) * 2000-08-29 2002-03-15 Mitsubishi Electric Corp メモリモジュールおよびその製造方法ならびにそれに使用するテストコネクタ
US20020043709A1 (en) * 2000-10-13 2002-04-18 Yeh Nai Hua Stackable integrated circuit
JP3652598B2 (ja) * 2000-11-22 2005-05-25 本田技研工業株式会社 内燃機関
US6680212B2 (en) * 2000-12-22 2004-01-20 Lucent Technologies Inc Method of testing and constructing monolithic multi-chip modules
US6680213B2 (en) * 2001-04-02 2004-01-20 Micron Technology, Inc. Method and system for fabricating contacts on semiconductor components
US6706624B1 (en) * 2001-10-31 2004-03-16 Lockheed Martin Corporation Method for making multichip module substrates by encapsulating electrical conductors
US6835592B2 (en) * 2002-05-24 2004-12-28 Micron Technology, Inc. Methods for molding a semiconductor die package with enhanced thermal conductivity
US6987031B2 (en) * 2002-08-27 2006-01-17 Micron Technology, Inc. Multiple chip semiconductor package and method of fabricating same
US7323772B2 (en) * 2002-08-28 2008-01-29 Micron Technology, Inc. Ball grid array structures and tape-based method of manufacturing same
US6879030B2 (en) * 2002-09-30 2005-04-12 Ultratera Corporation Strengthened window-type semiconductor package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107818799A (zh) * 2016-09-13 2018-03-20 希捷科技有限公司 具有背侧阻抗控制结构的柔性动态回路
CN107818799B (zh) * 2016-09-13 2021-03-12 希捷科技有限公司 具有背侧阻抗控制结构的柔性动态回路

Also Published As

Publication number Publication date
EP1573815A1 (en) 2005-09-14
KR101062260B1 (ko) 2011-09-06
WO2004055895A1 (en) 2004-07-01
TW200425462A (en) 2004-11-16
CN1742372A (zh) 2006-03-01
JP4452627B2 (ja) 2010-04-21
US7550842B2 (en) 2009-06-23
US20040113250A1 (en) 2004-06-17
JP2006510224A (ja) 2006-03-23
KR20050085561A (ko) 2005-08-29
TWI339435B (en) 2011-03-21
AU2003299608A1 (en) 2004-07-09

Similar Documents

Publication Publication Date Title
CN100530640C (zh) 集成电路组合件
US7372131B2 (en) Routing element for use in semiconductor device assemblies
US7652381B2 (en) Interconnect system without through-holes
US7190061B2 (en) stack package made of chip scale packages
US6344682B1 (en) Semiconductor device comprising a semiconductor element mounted on a substrate and covered by a wiring board
US8120164B2 (en) Semiconductor chip package, printed circuit board assembly including the same and manufacturing methods thereof
US20090045508A1 (en) Oblong peripheral solder ball pads on a printed circuit board for mounting a ball grid array package
US20080088030A1 (en) Attaching and interconnecting dies to a substrate
KR100628872B1 (ko) 전자소자 및 그 전자소자를 사용한 전자장치
KR970703617A (ko) 전도선을 가진 리드프레임 리드를 포함한 고밀도 집적회로 조립체(a high density integrated circuit assembly combining leadframe leads with conductive traces)
US6803666B2 (en) Semiconductor chip mounting substrate and semiconductor device using the same
US7521778B2 (en) Semiconductor device and method of manufacturing the same
US6989590B2 (en) Power semiconductor device with a control circuit board that includes filled through holes
US6753594B2 (en) Electronic component with a semiconductor chip and fabrication method
US7105923B2 (en) Device and method for including passive components in a chip scale package
JP3090115B2 (ja) 半導体装置およびその製造方法
JP3053013B2 (ja) 半導体集積回路装置
JPH0367345B2 (zh)
JPH08250620A (ja) 半導体装置
US20070290341A1 (en) Semiconductor package and method of mounting the same
JPH10223803A (ja) ボールグリッドアレイ
KR20060013067A (ko) 칩 리드프레임 모듈
CN1893047A (zh) 利用厚膜和印刷电路互连从集成电路分配信号的系统、方法和装置
JPH11121688A (ja) 複合型半導体装置
JPH047866A (ja) 混成集積回路装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090819

Termination date: 20111212