CN1113410C - 一种集成电路封装组件和组装集成电路封装的方法 - Google Patents
一种集成电路封装组件和组装集成电路封装的方法 Download PDFInfo
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Abstract
本发明是一种集成电路封装(10),其中包括与多个外安装管脚(14)及集成电路(12)耦连的多层印刷电路板(16)。多层电路板(16)有多个与集成电路(12)耦连并且不通过任何通路直通管脚(14)的内键合焊盘(46)。印刷电路板(16)有多层电压/接地层(20、22、24和28),以便给集成电路板(12)提供不同电压的电源。集成电路板(12)安装并电接地于还与印刷电路板(16)耦连的热片(52)上。热片(52)有双重功能,既可作接地面,又可作封装(10)的散热片。管脚(14)和封装(10)一般按常规PPGA封装结构构成。
Description
发明领域
本发明涉及一种集成电路封装以及组装集成电路封装的方法。
背景技术
集成电路(IC)一般置于能安装在印刷电路板上的管壳中。一种集成电路封装是栅阵列管脚塑料(PPGA)封装。典型的PPGA封装有能容纳集成电路的内腔,该内腔或者由帽盖或者由密封材料密封起来。内腔中有多个内键合焊盘,它们借助导线键合或TAB(载带自动键合)载带与IC耦连。内焊盘与从封装的外表面延伸出并与印刷电路板相连的管脚耦连。
内键合焊盘一般通过通路与管脚连通,这些通路把这些焊盘耦连到内导电层。形成通路要花费较多时间,且工艺成本高。因此,希望提供一种能不用通路构成的PPGA封装。
需要制造用于不同电源工作的各种集成电路。例如,用于台式计算机的集成电路可以在5V电源下工作,而用于便携式计算机的电路可在3.3V电源下工作。为了减少制造成本等,希望提供一种能封装用于不同电源工作的各种IC产品的单个PPGA器件。
发明内容
本发明是一种集成电路封装,其中包括多层印刷电路板,该电路板与多个外部安装管脚及集成电路耦连。多层电路板有多个内键合焊盘,这些焊盘与集成电路耦连,并且不用任何通路直接与管脚相连。印刷电路板有多个电压/接地层,为的是可以给集成电路板提供不同电压的电源。集成电路安装并电接地到也与印刷电路板耦连的热片上。该热片有双重功能,既可作为地,又可作封装的散热片。管脚和封装一般按常规PPGA封装的结构构成。
根据本发明的一个方面,提供了一种集成电路封装组件,包括:多层印刷电路板,它包括多层内导电层、多个边缘端部和多个卷绕在所述端部并与所述印刷电路板的内导电层相连接的多个内键合焊盘,所述内导电层直接通到多个导电孔内;多个与所述导电孔耦连的管脚;与所述内键合焊盘耦连的集成电路;及热片,它附着于所述多层印刷电路板上,并与所述集成电路和所述管脚电耦连。
优选地,在集成电路封装组件中,所述印刷电路板有多层导电层。
优选地,在集成电路封装组件中,所述印刷电路板有多层电源层。
优选地,在集成电路封装组件中,还包括支撑所述集成电路并与所述印刷电路板耦连的热片。
优选地,在集成电路封装组件中,所述热片与所述集成电路及所述管脚电耦连。
优选地,在集成电路封装组件中,所述多层印刷电路板有多层电源层。
根据本发明的另一个方面,提供了一种组装集成电路封装的方法,包括以下步骤:
a)把多个管脚附到多层印刷电路板的多个镀敷孔中,其中所述印刷电路板具有多个卷绕在所述印刷电路板的一个端部并与所述印刷电路板的内导电层相连接的多个内键合焊盘,所述内导电层直接通到多个导电孔内;
b)把热片安装到所述多层印刷电路板上;
c)把集成电路安装到所述热片上;
d)耦连所述集成电路与所述多层印刷电路板。
优选地在上述方法中,还包括密封所述集成电路的步骤。
优选地在上述方法中,用引线键合法进行耦连所述集成电路与所述多层印刷电路板的步骤。
优选地在上述方法中,所述热片与所述集成电路及所述多层印刷电路板电耦连。
附图说明
对于本领域的技普通术人员来说,在阅读了以下详细说明和各附图后,将会更清楚本发明的目的及优点,其中:
图1是本发明集成电路封装的透视图;
图2是图1所示封装的侧剖图;
图3是图1所示封装的顶面剖视图;
图4是图2所示封装的局部放大示图;
图5是图4所示封装的局部放大示图;
图6是展示盘绕到邻近导电面的键合焊盘的透视图。
具体实施方式
参见各附图,特别是各参考数字,图1-5展示了本发明的集成电路封装10。封装10中内置有集成电路12如微处理器。尽管这里说明和图示了集成电路12,但应该理解,该封装可以包括其它电器件。封装10有多个外安装管脚14。安装管脚14一般焊接于表面焊盘上或者外印刷电路板(未示出)的镀敷通孔中。管脚14最好是镀金的铁钴镍合金(Kovar),它们置于与常规栅阵列管脚塑料(PPGA)封装相当的结构中。这样本发明的封装10便可以插进常规外印刷电路板的孔中。在优选实施例中,封装10有296个管脚14。
封装10包括多层印刷电路板16。电路板16有数层导电层18-28,它们由介质层30-44隔开。导电层20-28有置于封装10的内腔48内的内键合焊盘46。按该优选实施例,多层印刷电路板由四块不同的常规印刷电路板构成,各电路板的硬介质基板(32、36、40和44)的一面或两面上有导电线/面。基板可以是加玻璃的环氧树脂或其它常规印刷电路板材料。印刷电路板一般借助如聚酰胺(30、34、38和42)等粘结剂粘接在一起。用常规印刷电路板技术构成封装10可以减少开发和制造多层封装10的成本。多层印刷电路板的导电层用于传送电源和数字信号,其中数字信号一般由单独的引线输送,导电面上提供电源。按该优选实施例,导电层18和26作为地(VSS),导电层20和22提供电源(VCC),层24和28传输数字信号。每一电源层能提供不同电压的电源。例如,导电层20可接5V电源,导电层22可接3.3V电源。集成电路12可根据电路12所需电源大小与电源层20和22或二者之一进行引线键合。
键合焊盘46置于封装10的分层边缘内。导电层18-28还具有多个进行了导电镀敷的通孔50。管脚14焊接于镀敷通孔50内,提供管脚14与键合焊盘46间的互连。键合焊盘46不用任何通路直通到镀敷的通孔。如图6所示,有些键合焊盘46盘绕介质材料的端部,并与邻近的导电层相连。这种盘绕就可实现不用任何通路键合焊盘与导电面间的互连。
热片52附着于印刷电路板16上。热片52最好由如铜之类的既导热又导电的材料构成。热片52可以镀镍和金,以提供引线键合面。热片52焊接于导电层18上。导电层18与某些管脚14相接,这样热片18便与管脚14电耦合。集成电路12安装于热片52上。集成电路12的接地焊盘借助键合线54焊接于热片52上。热片52和导电层18为封装提供接地面,并实现电路12与管脚14之间的电连接。所以热片52具有双重功能,既作接地面,又作散热片。
集成电路12还具有外表面焊盘(未示出),它们借助键合线54与相应的内键合焊盘46耦连。键合线54可以借助常规引线键合技术附着到电路12和键合焊盘46上。在把集成电路12键合到印刷电路板上后,用密封电路12的密封剂56填充内腔48。按另一实施例,可以用帽盖密封电路12。封装的外表面上可以施加焊料掩模58,用于绝缘导电层18和管脚14。
为了组装封装10,用粘结剂把各印刷电路板粘接在一起,形成多层印刷电路板16。也可用常规层叠技术把接合单独的印刷电路板在一起,在把电路板接合在一起之前,导电面和线要腐蚀成所要求的图形,从而形成导电层18-28。还可以在组装最后的多层电路板前形成镀敷孔。在各电路板的接合工艺中,可把热片52安装在印刷电路板的底上。
组装完多层板16后,把管脚14焊接到板16的镀敷孔50中。然后在电路板的外表面上施加焊料掩模58。把电路板/管脚组件作为分立单元装配,随后与集成电路一起使用。
集成电路12安装到热片52上,并将引线键合到印刷电路板16上。然后测试该封装,并用密封剂56填充,从而密封电路12。
尽管已说明并在各附图中展示了一些例示性实施例,但应该明白,这些实施例仅用于说明,并非对本发明范围的限制,本发明并不限于这里所展示和说明的这些特定结构和布局,本领域技术普通人员可作出各种改型。
Claims (10)
1.一种集成电路封装组件,包括:
多层印刷电路板,它包括多层内导电层、多个边缘端部和多个卷绕在所述端部并与所述印刷电路板的内导电层相连接的多个内键合焊盘,所述内导电层直接通到多个导电孔内;
多个与所述导电孔耦连的管脚;
与所述内键合焊盘耦连的集成电路;及
热片,它附着于所述多层印刷电路板上,并与所述集成电路和所述管脚电耦连。
2.根据权利要求1的集成电路封装组件,其特征在于,所述印刷电路板有多层导电层。
3.根据权利要求2的集成电路封装组件,其特征在于,所述印刷电路板有多层电源层。
4.根据权利要求1的集成电路封装组件,还包括支撑所述集成电路并与所述印刷电路板耦连的热片。
5.根据权利要求3的集成电路封装组件,其特征在于,所述热片与所述集成电路及所述管脚电耦连。
6.根据权利要求1的集成电路封装组件,其特征在于,所述多层印刷电路板有多层电源层。
7.一种组装集成电路封装的方法,包括以下步骤:
a)把多个管脚附到多层印刷电路板的多个镀敷孔中,其中所述印刷电路板具有多个卷绕在所述印刷电路板的一个端部并与所述印刷电路板的内导电层相连接的多个内键合焊盘,所述内导电层直接通到多个导电孔内;
b)把热片安装到所述多层印刷电路板上;
c)把集成电路安装到所述热片上;
d)耦连所述集成电路与所述多层印刷电路板。
8.根据权利要求7的方法,还包括密封所述集成电路的步骤。
9.根据权利要求8的方法,其特征在于,用引线键合法进行耦连所述集成电路与所述多层印刷电路板的步骤。
10.根据权利要求7的方法,其特征在于,所述热片与所述集成电路及所述多层印刷电路板电耦连。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/333,144 US5625166A (en) | 1994-11-01 | 1994-11-01 | Structure of a thermally and electrically enhanced plastic pin grid array (PPGA) package for high performance devices with wire bond interconnect |
US08/333,144 | 1994-11-01 |
Publications (2)
Publication Number | Publication Date |
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CN1171165A CN1171165A (zh) | 1998-01-21 |
CN1113410C true CN1113410C (zh) | 2003-07-02 |
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Application Number | Title | Priority Date | Filing Date |
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CN95196958A Expired - Fee Related CN1113410C (zh) | 1994-11-01 | 1995-11-01 | 一种集成电路封装组件和组装集成电路封装的方法 |
Country Status (9)
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US (1) | US5625166A (zh) |
JP (1) | JPH10512097A (zh) |
KR (1) | KR970707581A (zh) |
CN (1) | CN1113410C (zh) |
AU (1) | AU4019695A (zh) |
HK (1) | HK1008267A1 (zh) |
MX (1) | MX9702830A (zh) |
MY (1) | MY137608A (zh) |
WO (1) | WO1996013854A1 (zh) |
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WO2000005748A2 (en) * | 1998-07-22 | 2000-02-03 | Digirad Corporation | Blind pin placement on circuit boards |
US7020958B1 (en) * | 1998-09-15 | 2006-04-04 | Intel Corporation | Methods forming an integrated circuit package with a split cavity wall |
JP3160583B2 (ja) * | 1999-01-27 | 2001-04-25 | 日本特殊陶業株式会社 | 樹脂製基板 |
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WO2001047013A1 (en) * | 1999-12-21 | 2001-06-28 | Advanced Micro Devices, Inc. | Organic packages with solders for reliable flip chip connections |
US6229207B1 (en) | 2000-01-13 | 2001-05-08 | Advanced Micro Devices, Inc. | Organic pin grid array flip chip carrier package |
US6487083B1 (en) * | 2000-08-10 | 2002-11-26 | Nortel Networks Ltd. | Multilayer circuit board |
AU2003220023A1 (en) | 2002-03-05 | 2003-09-22 | Rika Denshi America, Inc. | Apparatus for interfacing electronic packages and test equipment |
US7177142B2 (en) * | 2004-09-29 | 2007-02-13 | Intel Corporation | Hybrid compression socket connector for integrated circuits |
WO2006104613A2 (en) | 2005-03-01 | 2006-10-05 | X2Y Attenuators, Llc | Conditioner with coplanar conductors |
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KR100834684B1 (ko) * | 2007-02-12 | 2008-06-02 | 삼성전자주식회사 | 전자 회로 패키지 |
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US5130889A (en) * | 1991-06-28 | 1992-07-14 | Digital Equipment Corporation | Integrated circuit protection by liquid encapsulation |
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-
1994
- 1994-11-01 US US08/333,144 patent/US5625166A/en not_active Expired - Lifetime
-
1995
- 1995-11-01 WO PCT/US1995/014169 patent/WO1996013854A1/en not_active Application Discontinuation
- 1995-11-01 AU AU40196/95A patent/AU4019695A/en not_active Abandoned
- 1995-11-01 KR KR1019970702747A patent/KR970707581A/ko not_active Application Discontinuation
- 1995-11-01 CN CN95196958A patent/CN1113410C/zh not_active Expired - Fee Related
- 1995-11-01 MX MX9702830A patent/MX9702830A/es unknown
- 1995-11-01 JP JP8514842A patent/JPH10512097A/ja not_active Ceased
- 1995-12-12 MY MYPI95003836A patent/MY137608A/en unknown
-
1998
- 1998-07-21 HK HK98109331A patent/HK1008267A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
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MY137608A (en) | 2009-02-27 |
CN1171165A (zh) | 1998-01-21 |
KR970707581A (ko) | 1997-12-01 |
JPH10512097A (ja) | 1998-11-17 |
MX9702830A (es) | 1997-07-31 |
US5625166A (en) | 1997-04-29 |
WO1996013854A1 (en) | 1996-05-09 |
HK1008267A1 (en) | 1999-05-07 |
AU4019695A (en) | 1996-05-23 |
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