MX9702830A - Paquete de matriz de reticula de agujas, de plastico, mejorado termica y electricamente (ppga). - Google Patents
Paquete de matriz de reticula de agujas, de plastico, mejorado termica y electricamente (ppga).Info
- Publication number
- MX9702830A MX9702830A MX9702830A MX9702830A MX9702830A MX 9702830 A MX9702830 A MX 9702830A MX 9702830 A MX9702830 A MX 9702830A MX 9702830 A MX9702830 A MX 9702830A MX 9702830 A MX9702830 A MX 9702830A
- Authority
- MX
- Mexico
- Prior art keywords
- circuit board
- integrated circuit
- package
- thermal
- ppga
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/20—Arrangements for cooling
- H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
- H10W76/42—Fillings
- H10W76/47—Solid or gel fillings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
La presente invencion se refiere a un paquete de circuito integrado que contiene un tablero de circuito impreso de multiples capas que se acopla a una pluralidad de agujas de montaje externas y un circuito integrado. El tablero de circuito de multiples capas tiene una pluralidad de cojines de union interiores que se acoplan al circuito integrado y se envían directamente a las agujas sin el uso de cualesquiera vías. El tablero de circuito impreso tiene multiples capas de voltaje/tierra, de manera tal que diferentes niveles de energía pueden suministrarse al tablero de circuito integrado. El circuito integrado se monta y pone a tierra eléctricamente a una barra térmica, que también se acopla al tablero de circuito impreso. La barra térmica proporciona la funcion dual de un plano de tierra y un colector térmico para el paquete. Las agujas y el paquete típicamente se configuran en un montaje de paquete PPGA convencional.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/333,144 US5625166A (en) | 1994-11-01 | 1994-11-01 | Structure of a thermally and electrically enhanced plastic pin grid array (PPGA) package for high performance devices with wire bond interconnect |
| PCT/US1995/014169 WO1996013854A1 (en) | 1994-11-01 | 1995-11-01 | Thermally and electrically enhanced plastic pin grid array (ppga) package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| MX9702830A true MX9702830A (es) | 1997-07-31 |
Family
ID=23301496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| MX9702830A MX9702830A (es) | 1994-11-01 | 1995-11-01 | Paquete de matriz de reticula de agujas, de plastico, mejorado termica y electricamente (ppga). |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US5625166A (es) |
| JP (1) | JPH10512097A (es) |
| KR (1) | KR970707581A (es) |
| CN (1) | CN1113410C (es) |
| AU (1) | AU4019695A (es) |
| MX (1) | MX9702830A (es) |
| MY (1) | MY137608A (es) |
| WO (1) | WO1996013854A1 (es) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6043559A (en) | 1996-09-09 | 2000-03-28 | Intel Corporation | Integrated circuit package which contains two in plane voltage busses and a wrap around conductive strip that connects a bond finger to one of the busses |
| US5804771A (en) | 1996-09-26 | 1998-09-08 | Intel Corporation | Organic substrate (PCB) slip plane "stress deflector" for flip chip deivces |
| US6054758A (en) * | 1996-12-18 | 2000-04-25 | Texas Instruments Incorporated | Differential pair geometry for integrated circuit chip packages |
| TW398165B (en) * | 1997-03-03 | 2000-07-11 | Hitachi Chemical Co Ltd | Circuit boards using heat resistant resin for adhesive layers |
| US7321485B2 (en) | 1997-04-08 | 2008-01-22 | X2Y Attenuators, Llc | Arrangement for energy conditioning |
| US9054094B2 (en) | 1997-04-08 | 2015-06-09 | X2Y Attenuators, Llc | Energy conditioning circuit arrangement for integrated circuit |
| US7336468B2 (en) | 1997-04-08 | 2008-02-26 | X2Y Attenuators, Llc | Arrangement for energy conditioning |
| WO2000005748A2 (en) * | 1998-07-22 | 2000-02-03 | Digirad Corporation | Blind pin placement on circuit boards |
| US7020958B1 (en) * | 1998-09-15 | 2006-04-04 | Intel Corporation | Methods forming an integrated circuit package with a split cavity wall |
| JP3160583B2 (ja) * | 1999-01-27 | 2001-04-25 | 日本特殊陶業株式会社 | 樹脂製基板 |
| JP3368870B2 (ja) * | 1999-06-25 | 2003-01-20 | 日本電気株式会社 | パッケージ基板及びこれを備えた半導体装置 |
| WO2001047013A1 (en) * | 1999-12-21 | 2001-06-28 | Advanced Micro Devices, Inc. | Organic packages with solders for reliable flip chip connections |
| US6229207B1 (en) | 2000-01-13 | 2001-05-08 | Advanced Micro Devices, Inc. | Organic pin grid array flip chip carrier package |
| US6487083B1 (en) * | 2000-08-10 | 2002-11-26 | Nortel Networks Ltd. | Multilayer circuit board |
| EP1488245B1 (en) * | 2002-03-05 | 2007-08-22 | Rika Denshi America, Inc. | Apparatus for interfacing electronic packages and test equipment |
| US7177142B2 (en) * | 2004-09-29 | 2007-02-13 | Intel Corporation | Hybrid compression socket connector for integrated circuits |
| GB2439861A (en) | 2005-03-01 | 2008-01-09 | X2Y Attenuators Llc | Internally overlapped conditioners |
| KR100737098B1 (ko) * | 2006-03-16 | 2007-07-06 | 엘지이노텍 주식회사 | 전자파 차폐장치 및 그 제조 공정 |
| US9713258B2 (en) * | 2006-04-27 | 2017-07-18 | International Business Machines Corporation | Integrated circuit chip packaging |
| KR100834684B1 (ko) * | 2007-02-12 | 2008-06-02 | 삼성전자주식회사 | 전자 회로 패키지 |
| US20090008139A1 (en) * | 2007-07-03 | 2009-01-08 | Sony Ericsson Mobile Communications Ab | Multilayer pwb and a method for producing the multilayer pwb |
| TW201327775A (zh) * | 2011-12-21 | 2013-07-01 | 財團法人工業技術研究院 | 半導體結構及其製造方法 |
| US9532465B2 (en) * | 2012-03-28 | 2016-12-27 | Ttm Technologies, Inc. | Method of fabricating a printed circuit board interconnect assembly |
| CN105304604A (zh) * | 2015-10-09 | 2016-02-03 | 株洲宏达天成微波有限公司 | 一种用于多焊盘芯片键合的多层键合方法 |
| US10804188B2 (en) | 2018-09-07 | 2020-10-13 | Intel Corporation | Electronic device including a lateral trace |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5130889A (en) * | 1991-06-28 | 1992-07-14 | Digital Equipment Corporation | Integrated circuit protection by liquid encapsulation |
| US5102829A (en) * | 1991-07-22 | 1992-04-07 | At&T Bell Laboratories | Plastic pin grid array package |
| US5357672A (en) * | 1993-08-13 | 1994-10-25 | Lsi Logic Corporation | Method and system for fabricating IC packages from laminated boards and heat spreader |
-
1994
- 1994-11-01 US US08/333,144 patent/US5625166A/en not_active Expired - Lifetime
-
1995
- 1995-11-01 WO PCT/US1995/014169 patent/WO1996013854A1/en not_active Ceased
- 1995-11-01 CN CN95196958A patent/CN1113410C/zh not_active Expired - Fee Related
- 1995-11-01 KR KR1019970702747A patent/KR970707581A/ko not_active Ceased
- 1995-11-01 MX MX9702830A patent/MX9702830A/es unknown
- 1995-11-01 JP JP8514842A patent/JPH10512097A/ja not_active Ceased
- 1995-11-01 AU AU40196/95A patent/AU4019695A/en not_active Abandoned
- 1995-12-12 MY MYPI95003836A patent/MY137608A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO1996013854A1 (en) | 1996-05-09 |
| JPH10512097A (ja) | 1998-11-17 |
| CN1171165A (zh) | 1998-01-21 |
| MY137608A (en) | 2009-02-27 |
| HK1008267A1 (en) | 1999-05-07 |
| US5625166A (en) | 1997-04-29 |
| AU4019695A (en) | 1996-05-23 |
| KR970707581A (ko) | 1997-12-01 |
| CN1113410C (zh) | 2003-07-02 |
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