US20050139980A1 - High density integrated circuit module - Google Patents

High density integrated circuit module Download PDF

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US20050139980A1
US20050139980A1 US11/040,564 US4056405A US2005139980A1 US 20050139980 A1 US20050139980 A1 US 20050139980A1 US 4056405 A US4056405 A US 4056405A US 2005139980 A1 US2005139980 A1 US 2005139980A1
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portion
bga package
package
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US11/040,564
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Carmen Burns
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Burns Carmen D.
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Priority to US07/990,334 priority Critical patent/US5484959A/en
Priority to US08/497,565 priority patent/US5631193A/en
Priority to US77469996A priority
Priority to US09/761,210 priority patent/US6919626B2/en
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25536047&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=US20050139980(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Burns Carmen D. filed Critical Burns Carmen D.
Priority to US11/040,564 priority patent/US20050139980A1/en
Publication of US20050139980A1 publication Critical patent/US20050139980A1/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49537Plurality of lead frames mounted in one device
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/107Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49121Beam lead frame or beam lead device
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49169Assembling electrical component directly to terminal or elongated conductor
    • Y10T29/49171Assembling electrical component directly to terminal or elongated conductor with encapsulating

Abstract

The present invention provides a method and apparatus for fabricating densely stacked ball-grid-array packages into a three-dimensional multi-package array. Integrated circuit packages are stacked on one another to form a module. Lead carriers provide an external point of electrical connection to buried package leads. Lead carriers are formed with apertures that partially surround each lead and electrically and thermally couple conductive elements or traces in the lead carrier to each package lead. Optionally thin layers of thermally conductive adhesive located between the lead carrier and adjacent packages facilitates the transfer of heat between packages and to the lead carrier. Lead carriers may be formed of custom flexible circuits having multiple layers of conductive material separated by a substrate to provide accurate impedance control and providing high density signal trace routing and ball-grid array connection to a printed wiring board.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a continuation-in-part of application Ser. No. 08/774,699, filed Dec. 26, 1996 and a Continuing Prosecution Application filed Feb. 11, 1998, pending, which is a continuation of 08/497,565, filed Jun. 30, 1995, now issued as U.S. Pat. No. 5,631,193, which is a continuation of application Ser. No. 07/990,334, filed Dec. 11, 1992, now issued as U.S. Pat. No. 5,484,959.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • This invention relates to a high density, integrated circuit module, which includes a plurality of vertically or horizontally stacked individual surface mount or ball-grid-array integrated circuit packages.
  • 2. Brief Description of the Related Technology
  • An example of a fabrication method and apparatus for high density lead-on-package modules by laminating one or more lead frames to standard integrated circuit packages is disclosed in U.S. Pat. No. 5,484,959, assigned to the common assignee of the present invention and incorporated herein by reference. Other methods for providing high density, stacked modules are disclosed in U.S. Pat. Nos. 5,279,029, 5,367,766, 5,455,740, 5,450,959 and 5,592,364, all of which are assigned to the common assignee of the present invention and incorporated herein by reference. The general methods and apparatus disclosed in the referenced patents can be applied to the fabrication of stacked configurations comprised of individual ball-grid-array or surface mount packages. However, the characteristic lead orientation, lead shape and lead content of ball-grid-array or surface mount packages impose a different set of parameters not adequately provided for by prior methods and assemblies.
  • SUMMARY OF THE INVENTION
  • The present invention provides a novel method and apparatus for manufacturing three-dimensional, high density, integrated circuit modules from standard ball-grid-array or other surface mount integrated circuit packages which provides improved space efficiency and heat dissipation. One way to increase space efficiency is to stack individual packages. Generally speaking, higher density generates more localized heat and thus increases the need for efficient heat dissipation. Improving the thermal transfer characteristics of the individual integrated circuit packages results in better heat dissipation for the module, and improves reliability and durability.
  • The present invention provides a novel method of fabricating a three-dimensional module formed of stacked and aligned surface mount or ball-grid-array packages. Ball-Grid-Array (BGA) integrated circuit packages typically have leads that extend from the bottom surface of a rectangular solid resin casing in a two-dimensional grid pattern. The external portion of each lead finished with a ball of solder. Package leads provide electrical and thermal coupling to one or more integrated circuit dies that are embedded within the protective casing. Typically, the protective casing completely surrounds the embedded die but, in some BGA packages, the protective casing does not cover the inactive top surface of the die. Near-chip scale packages provide 1.0 mm center-to-center lead spacing. Chip scale packaging such as MICRO_BGA™ have center-to-center lead spacing of 0.5 mm. Chip scale packaging offers excellent electrical characteristics including low capacitance and thermal design.
  • Connectivity to the leads of individual packages in a module is provided by thin substantially planar lead carriers located between adjacent packages. Lead carriers are adhered to adjacent packages with a thermally conductive but electrically insulating adhesive. A lead carrier is comprised of elongated electrically and thermally conductive elements formed in one or more thin planes of conductive material that are separated by high-dielectric material. Typically, each conductive element has at least one aperture, adapted to receive and electrically couple to an individual package ball and at least one interconnect lead that extends away from the module to provide external circuit connectivity to package leads. Preferably, the lead carriers are formed from custom flexible circuits commercially available from 3M™ or other manufacturers. These well known flexible circuits are typically comprised of one or more thin layers of conductive material that are die cut and drilled to form ground planes, signal traces, pads and apertures. The conductive layers are typically embedded in and between electrically-insulating, high-dielectric material such as polyamide, polyester or teflon which results in circuits that are flexible, have dense trace, and provide accurate impedance control.
  • The present invention utilizes standard manufactured packages to form the multi-package module. Such packages typically have ball irregularities or inconsistencies, particularly ball length and solder coating variations. These variations make automated assembly problematic since the tolerances necessary to accommodate variation in ball length and excess solder, for example, do not permit the packages to be assembled within the more stringent requirements for automated assembly of the module. According to one aspect of the present invention, the leads of the ball-grid-array packages are scythed prior to assembly or as an automated step during the assembly. Scything is a method where a hot razor knife skims off a layer from the distal end of all the leads of a ball-grid-array package, reducing random excess lead length and providing a uniform, closely tolerant lead length. The step of scything allows multiple packages to be added to the module prior to a final heating step where the solder for all the packages is flowed. This method also has the advantage of increasing the minimal tolerances for positioning of ball-grid-array package on the lead carrier. An alternative method that may also be used to compensate for excess solder from the leads is to provide channels formed in the walls or edges of each aperture of the lead carrier that receives the ball so the excess solder, when heated, flows into the channels A channel is a void area in a conductive element which merges into the void area of an aperture. An edge of the channel is in close proximity to the package leads and the void area extends away from the leads. Channels take advantage of the surface tension of molten solder which will pull molten solder away from leads to fill the channel.
  • Another object of the present invention is to provide an assembly which effectively dissipates heat generated during normal operation. Efficient thermal management increases the operational life of the module, and improves reliability by eliminating the effects of elevated temperature on the electrical characteristics of the integrated circuit and packaging. When packages are not stacked, heat from the embedded integrated circuits, generated through normal operation, is primarily dissipated by convection from the package's external surfaces to the surrounding air. When modules are formed by stacking packages, the buried packages have reduced surface area exposed to the air. The use of thermally conductive adhesive facilitates the transmission of heat between adjacent packages and is an effective method of taking advantage of the exposed surfaces for removing heat from buried packages.
  • In the module of the present invention, the package leads are thermally coupled to the lead carrier and provide a path for heat from the embedded integrated circuits. Thermally conductive adhesive also facilitates transfer of heat from packages to the lead carrier.
  • In applications where it is desirable to reduce the package and module height, or where package or module warping is a concern, each package may be constructed using any of the various techniques described in U.S. Pat. Nos. 5,369,056, 5,369,058 and 5,644,161, each of which is assigned to the common assignee of the present invention and incorporated herein by reference. These patents describe methods for constructing thin, durable packages and modules with enhanced heat dissipation characteristics and minimal warpage.
  • A common application of a stacked configuration is memory modules. Most of the leads of each package are electrically connected to corresponding leads of adjacent packages. A method is required to select the individual memory package being read, written or refreshed. One method is to provide a custom manufactured lead carrier for each package. A more cost-effective method is to use a common lead carrier design with extra package interconnect leads which is then modified by clipping off or no-connecting selected interconnect leads to make each lead carrier in a stacked configuration unique. Methods for connecting a unique bit of a data word per package and for uniquely addressing each package in a stacked configuration are described in U.S. Pat. Nos. 5,279,029 and 5,371,866, both which are assigned to the common assignee of the present invention and incorporated herein by reference. While the apparatus and methods of the present invention are described herein with reference to standard, single-size packages, it will be appreciated by those of ordinary skill in the art, that those methods and apparatus are equally applicable to multiple-die packages.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view of two adjacent packages of a module of the present invention;
  • FIG. 2 is a top planar view of a typical lead carrier of the present invention;
  • FIG. 3 a illustrates the preferred embodiment for an aperture for connection with a package lead of the present invention;
  • FIG. 3 b illustrates an alternative embodiment of an aperture for connection with a package lead of the present invention;
  • FIG. 4 illustrates a horizontally stacked module of the present invention;
  • FIG. 5 illustrates a vertically stacked module of the present invention;
  • FIG. 6 illustrates an alternative embodiment of a horizontally stacked module of the present invention; and
  • FIG. 7 illustrates an alternative embodiment of horizontally stacked module of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Other and further objects, features and advantages will be apparent from the following description of the preferred embodiments of the invention, given for the purpose of disclosure and taken in conjunction with the accompanying drawings.
  • The letter of a reference character containing numerics followed by a letter, either identifies the relative placement of the numeric reference within a stacked module or it identifies a specific embodiment.
  • Referring now to FIG. 1, a typical ball-grid-array package 50 is comprised of an integrated circuit 51 surrounded by an essentially rectangular solid resin casing 55. Package leads 52 extend from the bottom surface 54 of the casing in a two-dimensional grid pattern providing electrical and thermal coupling to one or more integrated circuit die 51 that are embedded within the protective casing. The external portion of each package lead 52 includes a coating of solder having a semi-spherical shape. Typically, the protective casing 55 completely surrounds the embedded die but, in some ball-grid-array packages 50, the protective casing 55 does not cover the inactive top surface 53 of the die. Near-chip scale packages 50 provide 1.0 mm center-to-center spacing between leads 52. Chip scale packaging such as MICRO_BGA™ have center-to-center lead spacing of 0.5 mm. Chip scale packaging offers excellent electrical characteristics including low capacitance and thermal design.
  • FIGS. 4 through 7 show various specific embodiments of stacked module M of the present invention. The letter M designates the module M formed of a plurality of ball-grid-array packages 50. Typically, the packages 50 are aligned as shown in FIGS. 4, 5 and 7 where the bottom surfaces 54 of each package 50 are facing the same direction. Alternately, the packages 50 may be aligned where one or more of the packages 50 are inverted in relation to the other packages 50 as shown in FIG. 6. In this embodiment, the top package 50 d is inverted with respect to the bottom package 50 e; the top surface 53 of the top package 50 d is in substantially full contact with the adhesive 70 on the top surface 53 of the lower package 50 e.
  • A typical application of one aspect of the present invention is shown in FIG. 1 which illustrates a partial cross-section of any two adjacent packages 50 that comprise a module M. The internals of package 50 b are not shown for simplicity. FIG. 1 shows two packages 50 a and 50 b mounted on opposite sides of a lead carrier 60 comprised of a single thin copper plane. Interconnect leads 64 extend away from the module M to provide external circuit connectivity to package leads 52 of the top package 50 a. External connectivity may be provided in different configurations as described in detail below with reference to FIGS. 4-7. A typical layout of a single plane lead carrier 60 is shown in FIG. 2. The lead carrier 60 is made to be flexible for increased reliability and ease of assembly. A lead carrier 60 can be comprised of elongated conductive elements 65 formed from a thermally and electrically conductive thin planer material such as beryllium copper alloy C3 having a thickness of about 3 mils. Each conductive element 65 is defined to include a trace, interconnect pad, via and any other conductive feature of the lead carrier that are electrically coupled. Other preferred alloys for the lead-carrier-conductive elements 62 are full hard or hard copper alloys (110 or 197) or olin copper alloy 1094. Preferably, the lead carrier 60 is formed from custom flexible circuits from 3M™ and other manufacturers. These well known flexible circuits are typically comprised of one or more thin (1.4 mils thick) layers of conductive material that are die cut and drilled to form apertures 66, ground planes and conductive elements 65 which include traces, mounting pads and leads. The conductive layers typically are flanked by a thin (typically 1 to 11 mill thick) layer of electrically-insulating, high-dielectric materials such at polyamide, polyester or teflon which results in circuit composites that are flexible. The material and thickness of individual layers that comprise the lead carriers 60 as well as spacing between conductive elements 65 and the width of conductive elements 65 can be precisely controlled to provide a accurate and consistent impedance control in select conductive elements 65. Lead carriers 60 formed from custom flexible-circuits can have vias for connecting traces 65 located on different planes and conductive pads (or leads), with solder coating having footprints that are compatible with standards for ball-grid array packages 50 for electrical and mechanical coupling to a printed wiring board 80.
  • Typically, each conductive element 65 in a lead carrier 60 has at least one aperture 66, adapted to receive an individual package lead 52 and at least one interconnect portion 64 that extends away from the module to provide an external point of electrical connection to package leads 52. Interconnect portions 64 preferably have a spring-like resiliency for increased reliability. Apertures 66 have about the same diameter as a package lead 52 allowing each package lead 52 to extend through the aperture 66 and for the lead carrier 60 to have substantial contact with the bottom surface 54 of a package 50. The application of heat (about 175 degrees centigrade) that is sufficient to cause the solder comprising the package leads 52 to flow will cause the solder to adhere to a thin area of a conductive element 65 on the surface of the lead carrier 60 facing away from the package 50 that surrounds each aperture 66 to form flange 55 that provides excellent electrical and mechanical coupling between package leads 52 and the lead carrier 60. FIG. 3 a illustrates the preferred semi-circle shape 66 a for the aperture 66 where the conductive element 65 partially surrounds the package ball 52. The semicircle shape 66 a, as opposed to a full-circle shape, enables an increased space for routing the conductive elements 65 of the lead carrier 60.
  • The present invention utilizes standard manufactured packages 50 to form the multi-package module M. Such packages 50 typically have package lead 52 irregularities or inconsistencies, particularly, lead length and solder coating variations. These variations make automated assembly problematic since the tolerances necessary to accommodate variation in lead 52 length, for example, do not permit the packages 50 to be assembled within the more stringent requirements for automated assembly of the module M. The package leads 52 typically have excess solder that can cause electrical shorts between package leads 52. According to one aspect of the present invention, the leads 52 of the ball-grid-array packages 50 are scythed prior to assembly or as an automated step during the assembly after the lead carrier 60 is attached. Scything is the preferred method of reducing the length by which package leads 52 extend from the package 50. Scything is a method where a hot razor knife skims off the distal portion of all package leads 52.
  • Referring again to FIG. 1, lead carriers 60 are adhered to adjacent packages 50 with a thermally conductive but electrical-insulating adhesive 70. The adhesive 70 may be epoxy, such as Rogers Corp. R/flex 8970 which is B-staged phenolic butyryl epoxy, that may be laminated at a temperature of 130 degrees centigrade and cured at a temperature of about 175 degrees centigrade. The preferred method is to use a 2 mil thick sandwich of polyamide film 70, such as Kapton™ which includes a 0.5 mil thick layer of adhesive on both sides (a three-layer system). A thermally conductive filled adhesive 70 may be used to enhance the transfer of heat between adjacent packages 50, and between the packages 50 and carrier 60.
  • Referring now to FIG. 4, a horizontally oriented embodiment of the present invention is illustrated. Typically, a module M is preassembled and then attached to a PWB 80 or other circuit carrying substrate. Alternately, the preassembled module M may be inserted into an integrated circuit socket.
  • In FIG. 4, a plurality of integrated circuit packages 50, each with an attached lead carrier 65, are stacked in a horizontally-oriented module M. In this configuration, each lead carrier 65 has an external interconnect portion 64 which extends from both sides of the module M to provide interconnection to an electrically and thermally conductive external interconnect structure 40. Structure 40 provides mechanical rigidity to the module M and is adhered to the upper surface 41 of the uppermost package 50. Structure 40 also includes circuit board interconnection portions 43 which may be formed for industry-standard socketability with an electrical socket carried in circuit board substrate 80.
  • A vertically-oriented configuration of module M is illustrated in FIG. 5. In this embodiment, lead carriers 60 are formed with external interconnect portions 64 all extending to one side which requires the conductive elements 65 to be more densely spaced. In this embodiment, external interconnect portions 64 are spaced in row and column configuration for socketing or soldering to circuit connections on circuit board substrate 80.
  • Another embodiment of module M is illustrated with reference to FIG. 6. In this embodiment, module M is formed in a two-high stack comprised of packages 50 e and 50 d. In this embodiment, package 50 e has its package leads 52 mounted directly to corresponding array of external circuit connect pads carried in substrate 80. Upper package 50 d is inverted with respect to package 50 e and mounted to package 50 d with thermally conductive adhesive layer 70. Surface 54 of package 50 d includes package leads 52. A lead carrier 60, formed as described above, is adhered to surface 54 of package 50 d with thermally conductive adhesive 70. External circuit interconnect portions 64 provide electrical connectivity for upper package 50 d to circuit connection pads carried in substrate 80.
  • Referring now to FIG. 7, module M is shown in an alternative three-high configuration comprised of individual packages 50 a, 50 b and 50 c. A lead carrier 60 is adhered to the package lead surface 54 of each package. For clarity, package leads 52 are not shown as to packages 50 a and 50 b. Lead carriers 60 for packages 50 a and 50 b include external circuit connect portions 64 b which are formed to nest together to provide mechanical rigidity and electrical and thermal conductivity for the module M. Lower package 50 c has lead carrier 60 c adhered to its lower surface 54 in the manner described above with thermally conductivity, electrically insulating adhesive. In this embodiment, circuit connection portions 64 a of lead carrier 60 c are selectively interconnected to connection portions 64 b. Package leads 52 of lower package 50 c are connected to external circuit connections carried in substrate 80 in a standard ball-grid-array pattern.
  • According to one specific method of the present invention, a method for manufacture a module M involves the following steps: (1) mounting an adhesive 70 a to the bottom surface 56 of a package 50; (2) aligning and mounting a lead carrier 60 to the adhesive 70 wherein apertures 66 receive the package leads 52; (3) scything of the distal end of all package leads 52; (4) applying heat (about 175 degrees centigrade) to cure adhesive 70 and flow the package lead 52 solder coating; (5) mounting a second thin layer of adhesive 70 b to the lead carrier 60; and (6) mounting another package 50 to the adhesive 70 b, wherein the top surface 56 of the package 50 has substantial contact with the adhesive. Steps 1 though 6 are repeated for each package 50 added to the module, except steps 5 and 6 are not repeated for the last package 50. For reliability and remanufacturability, it may be desirable to test each package 50 as it is added to the module M.
  • The preferred method replaces the steps of applying adhesive 70 a and 70 b with the preliminary step of applying double-sided adhesive tape 70 to both upper and lower surfaces of each lead carrier 60 prior to assembly. The step of applying heat to cause solder 53 to flow and to cure adhesive 66 after each step of mounting a package 50 is eliminated if the leads 52 of the package 50 are reduced in height prior to assembly and a thin area of the second layer of adhesive 70 b around each aperture 66 is left void to allow the package leads 52 to form a flange when heat is applied. The module M may be assembled using a suitably formed manufacturing jig provided to hold individual packages 50 in alignment as they are stacked together with interspaced lead carriers 60 and adhesive carrying tape 70. In this embodiment, the entire module M may be preassembled and a single heating event applied to flow the solder and cure the adhesive 70 as pressure is exerted on the module M to compress the layers.
  • Referring now to FIG. 3 b, an alternative embodiment which compensates for excess solder steps utilizes channels 66 c formed in each aperture 66 b. FIG. 3 b illustrates one shape of an aperture 66 b with multiple channels 66 c. A channel 66 c is a void area in a conductive element 65 which merges into the void area of an aperture 66. When a package lead 52 is inserted into the aperture 66 b, an edge of each channel 66 c is in close proximity to the package leads 52. The void area of the channel 66 c extends away from the ball 52. When heat is applied such that the solder coating the package leads 52 becomes molten, excess solder is pulled by the inherent surface tension of molten solder to fill the voided area.
  • Communication between individual integrated circuits embedded within packages 50 and signals external to the modules are provided by various methods for implementing an external structure. Methods and apparatus of such structures are described in U.S. Pat. Nos. 5,279,029 and 5,367,766. Alternatively, the external structure 40 may be formed integral to the leads 64 extending from the lead carrier 61 as shown in FIGS. 6 and 7. In the embodiment shown in FIG. 7, the leads 64 b are formed such to electrically and thermally connect directly to selected adjacent leads 64 b. Leads 64 may be formed with a substrate mounting portion 65 that may have a standard “gull-wing,” “J-lead” shape.
  • The foregoing disclosure and description of the invention are illustrative and explanatory of the preferred embodiments. Changes in the size, shape, materials and individual components used, elements, connections and construction may be made without departing from the spirit of the invention.

Claims (11)

1-41. (canceled)
42. A high density circuit module comprising:
first and second BGA packages, each having a body exhibiting a bottom surface, a top surface, a plurality of BGA contacts arranged in a grid along the bottom surface and first and second opposing lateral sides;
a flexible circuit having a first side with a first BGA-connecting portion including a plurality of electrical contacts arranged in a grid, and a second side, the first BGA-connecting portion of the first side of the flexible circuit being disposed below the body of the first BGA package and connected through the plurality of electrical contacts to the plurality of BGA contacts of the first BGA, the flexible circuit having a second portion having a second portion set of contacts for connecting to a circuit board and a third portion having a third portion set of contacts for connecting to the circuit board, the second portion being disposed partially beside the first lateral side of the second BGA package and the third portion being disposed partially beside the second lateral side of the second BGA package to dispose the second portion set of contacts and the third portion set of contacts below the level of a plane defined by the bottom surface of the body of the second BGA package.
43. The high density circuit module of claim 42 in which the flexible circuit comprises two or more planes of conductive material separated by high dielectric material.
44. The high density circuit module of claim 42 in which the plurality of electrical contacts are each formed having an aperture adapted to receive one of the BGA contacts.
45. The high density circuit module of claim 42 in which the flexible circuit is adhesively connected to the top surface of the second selected BGA package.
46. A high density circuit module comprising:
a first BGA package having a body with a bottom surface, a top surface, a plurality of BGA contacts arranged in a grid along the bottom surface, and first and second opposing lateral sides that define a vertical extent of body;
a first flexible circuit having a first portion disposed above the top surface of the first BGA package, the first portion having a grid of electrical contacts, a second portion disposed beside the first lateral side of the first BGA package, a third portion disposed beside the second lateral side of the first BGA package, a fourth portion disposed adjacent to the second portion and below the vertical extent of the body of the first BGA package, the fourth portion having a first set of contacts for connecting to a circuit board, a fifth portion disposed adjacent to the third portion and below the vertical extent of the body of the first BGA package, the fifth portion having a second set of contacts for connecting to the circuit board;
a second BGA package having a body with a bottom surface, a top surface, a plurality of BGA contacts arranged in a grid along the bottom surface, and first and second opposing lateral sides that define a vertical extent of body, the second BGA package being mounted to the grid of electrical contacts, the second BGA package being above the first BGA package.
47. The high density circuit module of claim 46 in which the first flexible circuit comprises two or more planes of conductive material separated by high dielectric material.
48. The high density circuit module of claim 46 further comprising:
a second flexible circuit having a first portion disposed above the top surface of the second BGA package, the first portion having a grid of electrical contacts, a second portion disposed beside the first lateral side of the second BGA package, a third portion disposed beside the second lateral side of the second BGA package, a fourth portion disposed adjacent to the second portion and below the vertical extent of the body of the second BGA package, the fourth portion having a first set of contacts for connecting to the first flexible circuit, a fifth portion disposed adjacent to the third portion and below the vertical extent of the body of the second BGA package, the fifth portion having a second set of contacts for connecting to the first flexible circuit;
a third BGA package having a body with a bottom surface, a top surface, a plurality of BGA contacts arranged in a grid along the bottom surface, and first and second opposing lateral sides that define a vertical extent of body, the third BGA package being mounted to the grid of electrical contacts of the second flexible circuit, the third BGA package being above the second BGA package.
49. The high density circuit module of claim 46 in which the grid of electrical contacts are each formed having an aperature adapted to receive one of the BGA contacts.
50. The high density circuit module of claim 46 in which the flexible circuit is adhesively connected to the top surface of the second selected BGA package.
51. The high density circuit module of claim 46 in which the flexible circuit is adhesively connected to the top surface of the second selected BGA package.
US11/040,564 1992-12-11 2005-01-21 High density integrated circuit module Abandoned US20050139980A1 (en)

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US07/990,334 US5484959A (en) 1992-12-11 1992-12-11 High density lead-on-package fabrication method and apparatus
US08/497,565 US5631193A (en) 1992-12-11 1995-06-30 High density lead-on-package fabrication method
US77469996A true 1996-12-26 1996-12-26
US09/761,210 US6919626B2 (en) 1992-12-11 2001-01-16 High density integrated circuit module
US11/040,564 US20050139980A1 (en) 1992-12-11 2005-01-21 High density integrated circuit module

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US11/040,564 Abandoned US20050139980A1 (en) 1992-12-11 2005-01-21 High density integrated circuit module

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US5631193A (en) 1997-05-20

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