CN100517621C - 具有包覆层的互连结构及其制造方法 - Google Patents
具有包覆层的互连结构及其制造方法 Download PDFInfo
- Publication number
- CN100517621C CN100517621C CN200580046544.0A CN200580046544A CN100517621C CN 100517621 C CN100517621 C CN 100517621C CN 200580046544 A CN200580046544 A CN 200580046544A CN 100517621 C CN100517621 C CN 100517621C
- Authority
- CN
- China
- Prior art keywords
- coating layer
- dielectric material
- interconnection structure
- interconnection
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/038—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
- H10W20/039—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures also covering sidewalls of the conductive structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
- H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/42—Vias, e.g. via plugs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/425—Barrier, adhesion or liner layers
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/034,890 | 2005-01-14 | ||
| US11/034,890 US7105445B2 (en) | 2005-01-14 | 2005-01-14 | Interconnect structures with encasing cap and methods of making thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101099235A CN101099235A (zh) | 2008-01-02 |
| CN100517621C true CN100517621C (zh) | 2009-07-22 |
Family
ID=36684497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200580046544.0A Expired - Fee Related CN100517621C (zh) | 2005-01-14 | 2005-12-02 | 具有包覆层的互连结构及其制造方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (3) | US7105445B2 (https=) |
| EP (1) | EP1836726A4 (https=) |
| JP (1) | JP2008527739A (https=) |
| CN (1) | CN100517621C (https=) |
| TW (1) | TW200634980A (https=) |
| WO (1) | WO2006088534A1 (https=) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7105445B2 (en) * | 2005-01-14 | 2006-09-12 | International Business Machines Corporation | Interconnect structures with encasing cap and methods of making thereof |
| US7317253B2 (en) * | 2005-04-25 | 2008-01-08 | Sony Corporation | Cobalt tungsten phosphate used to fill voids arising in a copper metallization process |
| US7737560B2 (en) * | 2006-05-18 | 2010-06-15 | Infineon Technologies Austria Ag | Metallization layer for a power semiconductor device |
| US7582558B2 (en) * | 2006-07-14 | 2009-09-01 | Intel Corporation | Reducing corrosion in copper damascene processes |
| US20090111263A1 (en) * | 2007-10-26 | 2009-04-30 | Kuan-Neng Chen | Method of Forming Programmable Via Devices |
| US7998864B2 (en) * | 2008-01-29 | 2011-08-16 | International Business Machines Corporation | Noble metal cap for interconnect structures |
| US8105937B2 (en) * | 2008-08-13 | 2012-01-31 | International Business Machines Corporation | Conformal adhesion promoter liner for metal interconnects |
| US7803704B2 (en) * | 2008-08-22 | 2010-09-28 | Chartered Semiconductor Manufacturing, Ltd. | Reliable interconnects |
| CN102203935A (zh) * | 2008-10-27 | 2011-09-28 | Nxp股份有限公司 | 生物兼容电极 |
| US20110045171A1 (en) * | 2009-08-19 | 2011-02-24 | International Business Machines Corporation | Multi-Step Method to Selectively Deposit Ruthenium Layers of Arbitrary Thickness on Copper |
| US8809183B2 (en) | 2010-09-21 | 2014-08-19 | International Business Machines Corporation | Interconnect structure with a planar interface between a selective conductive cap and a dielectric cap layer |
| US8492897B2 (en) | 2011-09-14 | 2013-07-23 | International Business Machines Corporation | Microstructure modification in copper interconnect structures |
| US9837356B1 (en) | 2016-06-07 | 2017-12-05 | International Business Machines Corporation | Interconnect structures with enhanced electromigration resistance |
| US10672653B2 (en) * | 2017-12-18 | 2020-06-02 | International Business Machines Corporation | Metallic interconnect structures with wrap around capping layers |
| US12341100B2 (en) * | 2021-10-11 | 2025-06-24 | International Business Machines Corporation | Copper interconnects with self-aligned hourglass-shaped metal cap |
| CN118338662A (zh) * | 2023-01-03 | 2024-07-12 | 长鑫存储技术有限公司 | 半导体结构及其制作方法 |
| US12581925B2 (en) | 2023-02-10 | 2026-03-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Selective metal cap in an interconnect structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5686760A (en) * | 1994-11-16 | 1997-11-11 | Nec Corporation | Eutectic Cu-alloy wiring structure in a semiconductor device |
| CN1346147A (zh) * | 2000-10-03 | 2002-04-24 | 索尼化学株式会社 | 带突起的线路板及其制造方法 |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2257504B (en) * | 1991-06-25 | 1995-10-25 | Nec Semiconductors | Method of measuring relative positioning accuracy of a pattern to be formed on a semiconductor wafer |
| US5300813A (en) * | 1992-02-26 | 1994-04-05 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
| WO1996002070A2 (en) * | 1994-07-12 | 1996-01-25 | National Semiconductor Corporation | Integrated circuit comprising a trench isolation structure and an oxygen barrier layer and method for forming the integrated circuit |
| US6294799B1 (en) * | 1995-11-27 | 2001-09-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating same |
| US5695810A (en) * | 1996-11-20 | 1997-12-09 | Cornell Research Foundation, Inc. | Use of cobalt tungsten phosphide as a barrier material for copper metallization |
| US6215129B1 (en) * | 1997-12-01 | 2001-04-10 | Vsli Technology, Inc. | Via alignment, etch completion, and critical dimension measurement method and structure |
| US6103625A (en) * | 1997-12-31 | 2000-08-15 | Intel Corporation | Use of a polish stop layer in the formation of metal structures |
| US6157081A (en) * | 1999-03-10 | 2000-12-05 | Advanced Micro Devices, Inc. | High-reliability damascene interconnect formation for semiconductor fabrication |
| JP2000323479A (ja) * | 1999-05-14 | 2000-11-24 | Sony Corp | 半導体装置およびその製造方法 |
| JP3626058B2 (ja) * | 2000-01-25 | 2005-03-02 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US6391669B1 (en) * | 2000-06-21 | 2002-05-21 | International Business Machines Corporation | Embedded structures to provide electrical testing for via to via and interface layer alignment as well as for conductive interface electrical integrity in multilayer devices |
| TW463307B (en) * | 2000-06-29 | 2001-11-11 | Mosel Vitelic Inc | Manufacturing method of dual damascene structure |
| US6461963B1 (en) * | 2000-08-30 | 2002-10-08 | Micron Technology, Inc. | Utilization of disappearing silicon hard mask for fabrication of semiconductor structures |
| JP4169950B2 (ja) * | 2001-05-18 | 2008-10-22 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP2003179058A (ja) * | 2001-12-12 | 2003-06-27 | Sony Corp | 半導体装置の製造方法 |
| US6605874B2 (en) * | 2001-12-19 | 2003-08-12 | Intel Corporation | Method of making semiconductor device using an interconnect |
| US20030116439A1 (en) * | 2001-12-21 | 2003-06-26 | International Business Machines Corporation | Method for forming encapsulated metal interconnect structures in semiconductor integrated circuit devices |
| JP2003243389A (ja) * | 2002-02-15 | 2003-08-29 | Sony Corp | 半導体装置及びその製造方法 |
| JP4103497B2 (ja) * | 2002-04-18 | 2008-06-18 | ソニー株式会社 | 記憶装置とその製造方法および使用方法、半導体装置とその製造方法 |
| JP3935049B2 (ja) * | 2002-11-05 | 2007-06-20 | 株式会社東芝 | 磁気記憶装置及びその製造方法 |
| US6764919B2 (en) * | 2002-12-20 | 2004-07-20 | Motorola, Inc. | Method for providing a dummy feature and structure thereof |
| FR2857719B1 (fr) * | 2003-07-17 | 2006-02-03 | Snecma Moteurs | Dispositif de vanne a longue course de regulation |
| US6838355B1 (en) * | 2003-08-04 | 2005-01-04 | International Business Machines Corporation | Damascene interconnect structures including etchback for low-k dielectric materials |
| JP4207749B2 (ja) * | 2003-10-28 | 2009-01-14 | 沖電気工業株式会社 | 半導体装置の配線構造及びその製造方法 |
| US7105445B2 (en) * | 2005-01-14 | 2006-09-12 | International Business Machines Corporation | Interconnect structures with encasing cap and methods of making thereof |
-
2005
- 2005-01-14 US US11/034,890 patent/US7105445B2/en not_active Expired - Fee Related
- 2005-12-02 EP EP05852629A patent/EP1836726A4/en not_active Withdrawn
- 2005-12-02 JP JP2007551251A patent/JP2008527739A/ja active Pending
- 2005-12-02 WO PCT/US2005/043465 patent/WO2006088534A1/en not_active Ceased
- 2005-12-02 CN CN200580046544.0A patent/CN100517621C/zh not_active Expired - Fee Related
-
2006
- 2006-01-04 TW TW095100294A patent/TW200634980A/zh unknown
- 2006-08-14 US US11/503,259 patent/US7488677B2/en not_active Expired - Fee Related
-
2008
- 2008-08-27 US US12/199,407 patent/US7902061B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5686760A (en) * | 1994-11-16 | 1997-11-11 | Nec Corporation | Eutectic Cu-alloy wiring structure in a semiconductor device |
| CN1346147A (zh) * | 2000-10-03 | 2002-04-24 | 索尼化学株式会社 | 带突起的线路板及其制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20060160349A1 (en) | 2006-07-20 |
| US7902061B2 (en) | 2011-03-08 |
| US20080318415A1 (en) | 2008-12-25 |
| CN101099235A (zh) | 2008-01-02 |
| US20070054489A1 (en) | 2007-03-08 |
| US7488677B2 (en) | 2009-02-10 |
| TW200634980A (en) | 2006-10-01 |
| EP1836726A4 (en) | 2010-07-28 |
| US7105445B2 (en) | 2006-09-12 |
| WO2006088534A1 (en) | 2006-08-24 |
| EP1836726A1 (en) | 2007-09-26 |
| JP2008527739A (ja) | 2008-07-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20171101 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171101 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. |
|
| TR01 | Transfer of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090722 Termination date: 20191202 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |