CN100490171C - 应用栅极介电层的晶体管 - Google Patents
应用栅极介电层的晶体管 Download PDFInfo
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- CN100490171C CN100490171C CNB200510136869XA CN200510136869A CN100490171C CN 100490171 C CN100490171 C CN 100490171C CN B200510136869X A CNB200510136869X A CN B200510136869XA CN 200510136869 A CN200510136869 A CN 200510136869A CN 100490171 C CN100490171 C CN 100490171C
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract
本发明提供一种栅极介电层以及应用该栅极介电层的晶体管与半导体装置,以及具有一氮化的栅极介电层的MOSFET与其制造方法。该制造方法包括提供一基板,开沉积一具有非高介电常数的介电材料于该基板上。该具有非高介电常数的介电材料包括两层。该介电材料的第一层邻近该基板,主要为不含氮的。该介电材料的第二层约含有1015atoms/cm3到1022atoms/cm3的氮。该MOSFET更包括一具有高介电常数的介电材料,形成于该具有非高介电常数的介电材料之上。该具有高介电常数的介电材料包括HfSiON、ZrSiON或氮化的Al2O3。在本发明的实施例中更揭露了核心区与周边区的不对称制造技术。
Description
技术领域
本发明为半导体装置与其制造方法,特别是一种具有改良的输入/输出的晶体管装置与其制造方法。其中该晶体管装置具有一复合式栅极介电质,包括一含氮且具有高介电常数的介电质,以及一下方介电层,具有一含氮区用以接触该具有高介电常数的介电层,以及一不含氮区用以接触该基板。
背景技术
栅极介电质的效能和稳定度一直都是已知CMOS工艺所关心的部分,尤其是在次微米工艺(如90nm、65nm或更低的工艺)中半导体装置的几何收缩情形,以及半导体装置可靠度标准上的加强。已知有两种方法用以增加在小几何尺寸时半导体装置的效能。其中一种方法是用以减少二氧化硅栅极°电质的厚度,而这会导致较高的栅极漏电流。另一种方法是利用所谓的高介电常数介电质(介电质具有大于3.9的介电常数即是,3.9为氧化硅的介电常数),可得到比已知的氧化硅层较薄的等效氧化物厚度(equivalent oxide thickness,EOT)。因为在高介电常数介电质与下层半导体材料(通常为硅、锗、硅锗化合物或其他类似材料)之间不希望的反应影响载子的漂移率,因此尽管已经利用一高介电常数介电质,但仍会再利用一薄的硅氧化物层作为栅极介电层的一部分。
硅氧化物的栅极介电质的常见的几个影响装置效能的现象包括电荷陷阱(charge traps),如氧化层内部或外部的缺陷,以及导因于硅氧介面的硅悬空键(dangling bonds)的干扰现象。此外,电荷陷阱的位置也常形成在一含氮的介电质与一不含氮的介电质之间,如一硅氧化物与一具有高介电常数的复合栅极介电质。
以目前来说,利用氮化处理(以热处理或等离子处理方式实现)在硅氧化物栅极介电质掺入氮,用以消除电荷陷阱可能产生的位置。一个氮化的氧化层(或是任何含氮的介电层)可能在下层基板有其他的不良影响,例如基板内的氮扩散,以及在一源/漏极或其延伸部内氮结合掺杂物扩散或掺杂物不活化的情形。
特别地,负偏置温度不稳定性(ne gative bias temperatureinstability,NBTI)可能会因为相对于基板(特别是相对于通道区)的含氮材料的存在而有不利的影响。当一氮化的栅极电极的有益的影响(如减少电荷陷阱)可能比一些晶体管应用上不利的结果更为重要,这些不利的影响在其他应用上,如输入/输出装置上更为明显。这是因为输入/输出晶体管通常在较高的电压运作,如5V、3.3V、2.5V、1.8V或其他相对的较高电压,而核心逻辑以及存储器装置则是以较低的相对电压运作,如1.5V、1.2V或是1V。
因此,如何提供一个装置以及其制造方法,用以提供一氮化的介电层以及一高介电常数介电层的优点是必要的,而这也可以同时增加装置与电路中周边(输入/输出)以及核心装置的效能,而不是去降低或消极的影响可靠度。
发明内容
本发明用以提供一种使用高介电常数的栅极介电层材料的半导体装置的制造方法与结构,用以解决或克服已知的问题以及达到较佳的效能。本发明还提供数个较佳实施例,提供一多层的介电层堆迭结构与方法,其中在栅极介电层内的氮分布区域克服了制造与可靠度的问题。
本发明提供一较佳实施例,包括适用于一晶体管的栅极介电层与其制造方法。该介电层包括一含氮的且具高介电常数的介电层以及一位于下方的不具高介电常数的介电层。该下方的介电层包括一含氮的第一区,用以接触具有高介电常数的介电层以及一大体上不含氮的第二区,用以接触一下方的基板。在一较佳实施例中,具有高介电常数的介电层包括氮化的铪基(Hf-based)高介电材料,如HfO2、HfSiO、HfON或是HfSiON,氮化的锆基(Zr-based)高介电材料,如ZrO2、ZrSiO、ZrON或是ZrSiON,氮化的铝基(Al-based)高介电材料,如Al2O3、AlSiO、AlON或是AlSiON以及其他介电常数大于8的介电材料。非高介电常数的介电层包括了氧和氮氧化物。
本发明提供一种栅极介电层,适用于一晶体管,该栅极介电层包括:一含氮且具有高介电常数的第一介电层;以及一第二介电层,位于该第一介电层的下方,该第二介电层具有含氮的一表面处理区与不含氮的一第二区,其中该表面处理区用以连接该第一介电层,该第二区用以连接一基板。
本发明所述的栅极介电层,该第一介电层具有一大于8的介电常数。
本发明所述的栅极介电层,该第一介电层的厚度约在5埃到50埃之间,该第二介电层的厚度约在15埃到80埃之间。
本发明所述的栅极介电层,该第二介电层具有一小于8的介电常数。
本发明所述的栅极介电层,该第二介电层中的该第一区的厚度大于1nm且该第二区的厚度大于0.5nm。
本发明所述的栅极介电层,该第一介电层包含下列硅(Si)、氧(O)、氮(N)、Hf、Ta、Al、La、Ge、Ti、Co、HfSiON、Ta2O5、TiO2、Al2O3、ZrO2、HfO2、Y2O3、La2O3、铝酸盐、硅酸盐、PbTiO3、BaTiO3、SrTiO3或PbZrO3。
本发明所述的栅极介电层,该基板包括硅(Si)、Ge、SiC、SiGe、SiGeC、SOI、SiGeOI、GeOI或GaAs。
在另一较佳实施例中,提供一半导体装置,如一集成电路,具有核心与周边区域形成于一基板上。在核心与周边区域的工艺步骤上是不对称的。数个制造结构与方法应用在一区域,但在其他区域便不适用,反之亦然。利用这样的不对称的方法应用在装置的工艺上,在本发明中说明的实施例皆是针对核心区域与周边区域订做的工艺。在一包括非对称工艺的一实施例中,在周边区的通道区的氮含量低于在核心区的通道区。在另一实施例中,在周边区域的非高介电常数介电层的厚度大于在核心区域的非高介电常数介电层的厚度。
本发明提供一种半导体装置,具有一核心区以及一输入输出区形成于一基板上,该半导体装置包括:一第一介电层形成于该基板之上,该第一介电层在该输入输出区上具有一第一厚度,在该核心区上具有一第二厚度,其中该第一厚度大于该第二厚度;以及一第二介电层,形成于该第一介电层之上,且覆盖该核心区与该输入输出区,其中该第一介电层覆盖在该输入输出区的区域被部分氮化,且该第一介电层中覆盖在该核心区的区域被完全氮化。
本发明所述的半导体装置,该第一介电层具有一小于8的介电常数且该第二介电层具有一大于8的介电常数。
本发明所述的半导体装置,该第一厚度至少大于该第二厚度约0.1nm。
本发明所述的半导体装置,该第一介电层中覆盖在该核心区的区域的厚度小于1.5nm。
本发明所述的半导体装置,具有高介电常数的该第二介电层包含硅(Si)、氧(O)、氮(N)、Hf、Ta、Al、La、Ge、Ti、Co、HfSiON、Ta2O5、TiO2、Al2O3、ZrO2、HfO2、Y2O3、La2O3、铝酸盐、硅酸盐、PbTiO3、BaTiO3、SrTiO3或PbZrO3。
在另一实施例中,该半导体装置为一晶体管。晶体管包括一基板以及一栅极结构形成于该基板上。在其他类似相关的实施例中,该栅极结构包括一第一介电层形成于该基板之上,该第一介电层具有含氮的一表面处理区与不含氮的一第二区,其中该表面处理区用以连接该第二介电层,该第二区用以连接一基板。一含氮且具有高介电常数的介电层,形成于该第一介电层之上。一栅极电极形成于该第二介电层之上。数个实施例中更包括一源极区域以及一漏极区域,相临于栅极结构且在相对的方向,且在两者之间形成一通道区,该通道区的长度约小于100nm。在较佳实施例中,第一介电层的介电层数小于8,而具有高介电常数的介电层的介电常数大于8。在较佳实施例中,含氮区域的厚度约大于1nm,而大体上不含氮的区域的厚度约大于0.5nm。
本发明提供一种晶体管,该晶体管包括:一基板;一栅极结构,包括:一第一介电层,形成于该基板之上,该第一介电层具有一大体上不含氮的一第一区,紧邻于该基板,以及含氮的一第二区,紧邻于该第一区;一第二介电层,形成于该第一介电层之上,该第二介电层为含氮且具有高介电常数;以及一栅极电极,位于一第三介电层之上;以及一源极区与一漏极区,紧邻于该栅极结构且分别位于该栅极结构的两侧,且在该源极区与该漏极区之间形成一通道区,该通道区的长度小于100nm。
本发明所述的晶体管,该第一介电层具有一小于8的介电常数,且该第二介电层具有一大于8的介电常数。
本发明所述的晶体管,含氮的该第二区的厚度约大于1nm且该第一区的厚度约大于0.5nm。
本发明所述的晶体管,具有高介电常数的该第二介电层包含硅(Si)、氧(O)、氮(N)、Hf、Ta、Al、La、Ge、Ti、Co、HfSiON、Ta2O5、TiO2、Al2O3、ZrO2、HfO2、Y2O3、La2O3、铝酸盐、硅酸盐、TiO2、PbTiO3、BaTiO3、SrTiO3或PbZrO3。
附图说明
图1a与图1b为应用本发明的复合栅极介电层的周边输入/输出装置的实施例的示意图。
图2为根据图1a与图1b的结构的一半导体基板2的剖面示意图。
图3为用以表示符合图1a和图1b的剖面示意图的一MOSFET装置100的工艺结果的一剖面示意图。
具体实施方式
在下文中会以本发明的较佳实施例为例说明本发明的运作与制造,但非用以限制本发明,且本发明的应用上非仅限于下文中的实施例,本领域技术人员当可据以应用于相关领域。
请参考图1a。图1a为根据本发明的概念,以一微电子工艺制造的半导体基板的结构示意图。半导体基板2较佳为一晶圆,可能包含锗(Ge)、硅锗(SiGe)、应变硅(strained silicon)、应变锗(strained germanium)、GaAs、硅在绝缘体上(silicon oninsulator)、硅锗在绝缘体上(SiGeOI)、锗在绝缘体上(GeOI)、一种多个硅/硅化锗层的堆迭结构以及上述材料的结合。基板2被应用在微电子制造中,微电子制造中包含了集成电路制造、电荷耦合装置微电子制造、辐射发射微电子制造以及光电微电子制造。
图1a与图1b为一周边输入/输出装置的实施例的详细说明,特别是在应用本发明的复合栅极介电层的周边输入/输出装置。
一第一中间工艺步骤,如图1a所示,描述了一高介电常数介电层6以及一下方介电层8的形成。下方介电层8形成在基板2的上方表面。下层介电层较佳为一非具有高介电常数的介电层。本领域技术人员会得知在形成该下方介电层8之前,在基板2的表面上可能会存在一薄的原生氧化层(native oxide layer)。在另一个例子中,该原生氧化层可能由一湿蚀刻(氢氟酸浸泡)或一干蚀刻(氢氟酸气体或含氢气体退火)方式来移去。较佳实施例中,该下方介电层8是基板2在一充满氧的环境中的一热成长氧化物。
如图1a所示,一高介电常数介电层6形成在下方介电层8之上。该高介电常数介电层6的沉积可能是由一已知方式达成,如遥式化学气相气体沉积(remote plasma CVD,RPCVD)、等离子辅助化学气相沉积(plasma enhanced CVD)、原子层沉积(atomiclayer deposition,ALD)、有机金属化学气相外延法(metalorganic chemical vapor deposition,MOCVD)、分子束外延法(molecular beam epitaxy,MBE)、物理气相沉积(physicalvapor deposition,PVD)、溅镀或是其他已知方法。
高介电常数介电质是指具有介电常数大于硅氧化物介电值(约为3.9)的介电质。较佳实施例中,高介电常数介电质的介电常数要大于8。高介电常数介电质可能为Ta2O5、TiO2、Al2O3、ZrO2、HfO2、Y2O3、La2O3以其上述材料的铝酸盐或硅酸盐。高介电常数介电材料可能包含一个单一金属氧化物层或是含有两个或数个金属氧化物的数个层。其他可能具有高介电常数的介电质包括氮化硅、硅氧化铬、氧化镧以及其他已知的高介电常数材料。高介电常数介电层6可能包含了下列材料或其化合物或数个材料的堆迭层:HfO2、HfSiOx、HfON、HfSiON、HfAlOx、ZrO2、ZrON、ZrSiON、Al2O3、TiO2、Ta2O5、La2O3、BST、PbTiO3、BaTiO3、SrTiO3、PbZrO3、PST、PZN、PZT、PMN、金属氧化物、金属硅酸盐以及金属氮化物。高介电常数介电层6可能更包含了下列材料:Si、Ge、F、C、B、O、Al、Ti、Ta、La、Ce、Bi、W、Hf或Zr原子。
在较佳实施例中,高介电常数介电层6可能包含一非晶硅(amorphous)、一结晶状或多结晶状材料。高介电常数介电层6的厚度约为1埃到100埃之间,较佳为小于50埃,以维持低栅极漏电流以及较薄的等效氧化物厚度。
在较佳实施例中,高介电常数介电层6被沉积覆盖在下方介电层8,如图1b所示,且一氮处理或氮化处理使得高介电常数介电层6以及下方介电层8的一上部区域掺杂氮(如图1b中点状部分)。下方介电层8的上方区域为一氮化介电层10,且下方介电层8的下方区域为一大体上不含氮介电层12。氮化介电层10较佳为氮化(nitrided或nitrogenozed)介电层,如图1b所示。在一实施例中,氮化过程可通过将介电层暴露在含氮等离子中。在较佳实施例中,N2等离子、NOx等离子或NHx等离子都可用来氮化处理高介电常数介电层6与下方介电层8。在另一实施例中,高介电常数介电层6与下方介电层8通过热氮化过程达到氮化的目的。热氮化的较佳实施例工艺为使用NH3或NOx氮化。
在较佳实施例中,下方介电层8的优点为提供高介电常数周边或输入/输出装置较高的游离度以及稳定度。下方介电层8的氮化介电层10的远离通道的设计可以维持较佳的通道游离度、NBTI稳定度以及在源/漏极与通道区中可控制的掺杂量变曲线。更进一步来说,利用位于基板2与氮化介电层10之间的不含氮介电层12可以避免或大体上预防基板2的氮结合的不良影响。
较佳实施例中,下方介电层8被氮化的深度大于1nm。换言之,氮化介电层10(或称做一子层)的组成厚度大于1nm,不含氮介电层12的组成厚度大于0.5nm。较佳实施例中,氮化介电层10的厚度为总厚度的百分之十到百分之九十。并非一个限制定义而是一个举例说明,含氮的意思是指在含氮区或含氮子层中的氮原子的浓度1015atoms/cm3到1022atoms/cm3。
刚沉积上去时,高介电常数介电层一般具有较高的捕捉电荷密度。这些电荷陷阱可能通过注入大于5个原子百分率的氮,较佳为1到15个原子百分率之间。钝化可能造成在一些实施例中,捕捉电荷密度小于1012cm2,因此具有较低的漏电流以及EOT。实施例中更包括产生氮的方法,通过覆盖氮化硅产生的扩散、气体扩散、远遥式等离子氮化以及退耦等离子氮化。
在一实施例中,包括一方法,用以将氮注入高介电常数介电层6并以约500℃到900℃的温度加热约0.5分钟到500分钟,较佳为在氨气、氧化亚氮以及氮氧化合物中。
另一实施例包括在约200℃到1000℃的温度下对高介电常数介电层6进行远遥式等离子氮化约0.5到60分钟,较佳为在氨气、氮、氧化亚氮以及氮氧化合物中。远遥式等离子氮化的一较佳实施例为在550℃下,1分钟的氮化时间。
在另一用以对捕捉高介电常数介电层6内电荷钝化的方法包括在10℃到400℃的温度下,使用退耦式等离子氮化0.1分钟到60分钟。退耦式等离子氮化的一较佳实施例为在25℃下,30秒钟的氮化时间。
在一实施例中,一HfwSixOyNz(HfSiON)的高介电常数介电层6被沉积的厚度约为5埃到50埃,且具有小于2.0nm的等效氧化物厚度。
另一较广泛应用的实施例叙述了目前在网络激增与快速成长的年代里已知的应用,如高效能的宽频装置与电路。提供高效能晶体管与嵌入是高密度存储器的嵌入式系统(system on chip,SOC)解决方案在实现高效能宽频装置上是非常需要的,可以用以划分频宽以及达到需要的高速与运作频率。
一嵌入式系统可能包含了存储单元(如DRAM、SRAM、flash、EEPROM、EPROM)、逻辑电路、模拟以及输入/输出装置。逻辑电路与一些输入/输出装置通常需要高效能的晶体管以达到更快的信号传输。PMOS逻辑装置与一些输入/输出装置需要高驱动电流,则可能被会在源极与漏极部分以取向附生长成应变材料(epitaxially grown strained material)制造,如SiGe。同样地,在SOC中一些NMOS晶体管需较高的电子游离率。较高的电子游离率可能由一伸展的薄膜,如Si3N4,获得,该薄膜可能被以一内部的伸展压力的方式沉积。
然而,对其他装置来说,速度的效能并不是这么重要的。一些逻辑电路装置、存储单元装置以及输入/输出装置或模拟装置,这些不需要高驱动电流的装置可能就不会以应变材料或应变方法制造。这些装置不会因为制造的复杂度、花费以及产能减少而有所影响,而这些因素都是会影响使用先进科技的高驱动电流装置。
按照这些需求,下文所述的实施例包括不对称的与嵌入式系统制造的最佳化。举例来说,嵌入式系统包括一周边区域(第一区域)以及一核心区域(第二区)形成在基板上。在核心区域与周边区域的工艺步骤可能为不对称。数个制造结构与方法应用在一区域,但在其他区域便不适用,反之亦然。利用这样的不对称的方法应用在装置的工艺上,在本发明中说明的实施例皆是针对核心区域与周边区域订做的工艺。
较佳实施例中,周边区域包括一输入/输出区域以及一模拟区域以及一上述区域的结合区域。较佳实施例中,核心区域包括一逻辑区域以及一存储器区域以及一上述区域的结合区域。在其他实施例中,当其他装置可能包含了非核心区域时,模拟装置或输入/输出装置可能被包含在核心区域中。
在较佳实施例中,一非高介电常数介电层被沉积在周边区域与核心区域两者。如同实施例所说的,介电层包括两个层。根据非对称嵌入式系统要求,在核心与周边区域内的第一与第二非高介电常数介电层是个别最佳化。在周边区域中,栅极介电层厚度可能会大于核心区域的介电层厚度。在周边区域中,靠近介电层/基板介面的氮浓度会比核心区域的氮浓度低。在另一实施例中,介电层只有在输入/输出装置中包含两层,在核心装置中只有一氮化介电层10。
如图2所示,一较佳实施例包括不对称制造方法与结构。图2为根据图1a与图1b的结构的一半导体基板2的剖面示意图。基板2包括一核心区与一周边区。一下方介电层8被沉积在基板2的周边区上。如前文所述,下方介电层8为部分氮化,使得产生一氮化介电层10形成于一不含氮介电层12之上。一下方介电层8’被沉积在基板2的核心区之上,其中下方介电层8’大体上如同氮化介电层10一样氮化,而形成氮化介电层10’。如图2所示,在更进一步的较佳非对称工艺的实施例中,在周边区的氮化介电层10厚度可能比在核心区的氮化介电层10’厚度来得厚。因此,在周边区的氮化介电层10的厚度较佳为10埃到50埃,在核心区的氮化介电层10’的厚度约为10埃或是小于30埃。在本发明一较佳实施例中,周边区的氮化介电层的厚度10约大于核心区的氮化介电层10’约0.1nm。在更近一步的较佳工艺中,下方介电层8或8’下方的通道区(或基板表面)在周边区的部分具有比在核心区较低的氮浓度,这是因为在氮化工艺中较少的氮渗透。
在氮化介电层10与10’中的氮分布可能是均质或非均质的,例如渐次扩散。已知的方法则是用以建立一适合的渐次扩散,介电层的氮分布曲线。一旦这种已知技术被应用在ALD上,则已经为美国公开号No.2003/0032281所揭露,而且本发明也以此为参考。
回到图2,氮化介电层10可能包括一渐次的介电层的氮分布曲线。实施例可能包含一分布曲线,其中在不含氮介电层12的氮大体上是0%。与非对称工艺的实施例一致,在核心区域与周边区域中,氮可能被独立分布或是渐次分布。或是说,氮化介电层10可能为均质,且不含氮介电层12可能是渐次分布,但是在介电层/基板介面的氮分布程度较佳为0。
继续图2的说明,一高介电常数介电层6被沉积覆盖在氮化介电层10与10’。一栅极电极4被沉积在高介电常数介电层6之上。
发明人根据提出的实施例,制造测试的MOSFET,具有氮化的Hf硅酸盐(HfSiON或HfON)的高介电常数栅极介电层。在可靠度的估算下,如NBTI、PBTI、HCI或TDDB,测试的MOSFET在室温与高温下,在反向模式与累积模式下被施加压力。输入/输出与核心装置在以已知估算方法估算下都具有超过10年的生存周期。
最后,本领域技术人员所知的工艺被采用,以完成符合图1a和1b所示的微电子装置结构。图3为一剖面示意图,用以表示符合图1a和1b的剖面示意图的一MOSFET装置100的工艺结果。
MOSFET装置100可能包括一晶体管,形成在基板2之上或内部,基板2可能为一大量的硅晶圆,但本领域技术人员当可知道基板2可能为一半导体层,形成在一支撑的基底的一掩埋氧化层之上,支撑的基底已知为绝缘层上覆硅结构。基板2可能更包括Ge、SiGeC、GeOI、SiGeOI、GaAs、如Si/SiGe的堆迭的层状结构以及上述材料的复合物。
MOSFET装置100包括一栅极结构,包括一栅极电极4覆盖在一高介电常数介电层6之上,高介电常数介电层6覆盖在一下方介电层8之上,栅极结构较佳为由氧化硅形成。栅极电极4的材料较佳为一多晶硅、硅化物或金属栅极电极材料。栅极电极4可能被以一已知的CVD、PVD或其他适合的工艺所沉积,沉积厚度小于2000埃。下方介电层8具有一氮化介电层10,用以接触高介电常数介电层6,以及一第二非氮化或大体上不含氮介电层12,用以接触基板2。
如图3所示,侧壁间隙壁14与16分别在栅极结构的两侧。侧壁间隙壁14与16被沉积与组成在对应的侧壁,且在栅极电极4、高介电常数介电层6与下方介电层8的一边。侧壁间隙壁14与16使用一非高介电常数介电质沉积而成,以提供栅极电极4的侧壁的一保护间隙壁。大多数的侧壁间隙壁14与16为复合的间隙壁,例如ON(氧化硅/氧化氮-氮化硅)、NO、ONO、ONON或NONO间隙壁。侧壁间隙壁14与16的底层(图上未显示,较佳为小于8nm)较佳为一含氮层(如氮化硅),以避免一次氧化层形成在栅极电极4与高介电常数介电层6之间的介面,且可能以低温或高温的沉积方法沉积,如LPCVD、RTCVD、PECVD与RPCVD。侧壁间隙壁14与16可能含有氮化硅、氧化硅或氮氧硅化合物。
根据掺杂在源极区18、漏极区20以及基板2的掺杂物可以决定晶体管的型态为P型MOS晶体管或N型MOS晶体管。在一互补式MOS晶体管集成电路中,晶体管可能被形成在阱扩散区(welldiffusions)(图上未显示)内,阱扩散区可能是在浅沟隔离层(shallow trench isolation,STI)36与40或LOCOS隔离层(图上未绘出)形成前被形成,阱扩散区也会因为浅沟隔离层36与40而被隔离。
本发明的较佳实施例并没有去限制使用额外的材料与方法来增加效能。举例来说,应变通道材料,如SiGe,已为本领域技术人员所知用以增加载子游离度,特别是在PMOS晶体管制造上。应变通道材料被通过如外延生长(epitaxial growth)方式沉积。应变通道材料的厚度较佳为小于200埃,较佳实施例为约100埃。该应变材料可能是下列的半导体材料、混合物或多层材料都可以被使用,包括:Si、应变Si、SOI、SiC、SiGe、SiGeC、SiGeOI、Ge、GeOI、应变Ge以及上述材料的化合物。如图3所示,在栅极结构,间隙壁14与16、源极区18、漏极区20的形成之后,一接触蚀刻停止层22被形成且覆盖在MOSFET装置100之上。在一实施例中,该氧化物或氮氧化物接触蚀刻停止层(contact etch stoplayer,CESL)22可能是由CVD方式形成。在另一实施例中,接触蚀刻停止层22为本领域技术人员所知的氮化硅,可能被以内部的压缩力(对PMOS而言)或内部的张力(对NMOS而言)的方式沉积,用以将压缩材料形成于下方的基板之上,以增加游离率(电子或空穴的游离率)。
更进一步根据已知技艺的工艺技术来说,一硅化物可能通过沉积在一金属,如镍、钛或钴,然后接受处理以形成一自动对准(self-aligned)硅化物或一硅化金属于栅极电极38、源极区、漏极区以及其他区域的顶端,以提供一较低电阻并改善装置效能。
接着下列硅化金属步骤(如果有被使用的话),层间绝缘层24被形成在基板2之上,通过沉积步骤以沉积氧化物、氮化物或其他已知的绝缘材料,如此一来,一典型的硅氧化合物就被形成了。接触区域被配置且蚀刻在该绝缘材料,以暴露该源极区、漏极区以及栅极电极38,由蚀刻产生的通道26则注满了导通材料以提供电性连接由位于层间绝缘层24之上的金属层到栅极电极、源极区以及漏极区。铝或铜的金属层可能被形成在层间绝缘层24之上,利用已知技术,如铝金属化工艺或一双金属铜嵌入金属化工艺(dual damascene copper metallization process)以提供一个或多个接线层,用以接触通道26以及产生对栅极电极、源极区与漏极区的电性连接。接着再利用已知的清洗、钝化、晶片切割(diesaw)、晶片分离(singluation)、封装(packaging)、组装(assembly)以及测试步骤来完成形成在基板2上的集成电路装置。
虽然本发明已通过较佳实施例说明如上,但该较佳实施例并非用以限定本发明。本领域的技术人员,在不脱离本发明的精神和范围内,应有能力对该较佳实施例做出各种更改和补充,因此本发明的保护范围以权利要求书的范围为准。
附图中符号的简单说明如下:
2:基板
4:栅极电极
6:高介电常数介电层
8:下方介电层
8’:下方介电层
10:氮化介电层
10’:氮化介电层
12:不含氮介电层
14:侧壁间隙壁
100:MOSFET装置
16:侧壁间隙壁
18:源极区
20:漏极区
22:接触蚀刻停止层
24:层间绝缘层
26:通道
36、40:浅通道隔离区
38:栅极电极
Claims (5)
1.一种晶体管,其特征在于,该晶体管包括:
一基板;
一栅极结构,包括:
一第一介电层,形成于该基板之上,该第一介电层具有含氮的一表面处理区与不含氮的一第二区,其中该表面处理区用以连接第二介电层,该第二区用以连接一基板;
一第二介电层,形成于该第一介电层之上,该第二介电层为含氮且具有高介电常数;以及
一栅极电极,位于一第三介电层之上;以及
一源极区与一漏极区,紧邻于该栅极结构且分别位于该栅极结构的两侧,且在该源极区与该漏极区之间形成一通道区,该通道区的长度小于1000埃。
2.根据权利要求1所述的晶体管,其特征在于,该第一介电层具有一小于8的介电常数,且该第二介电层具有一大于8的介电常数。
3.根据权利要求1所述的晶体管,其特征在于,含氮的该第二区的厚度大于1nm且该第一区的厚度大于0.5nm。
4.根据权利要求1所述的晶体管,其特征在于,具有高介电常数的该第二介电层包含硅、氧、氮、Hf、Ta、Al、La、Ge、Ti或Co。
5.根据权利要求1所述的晶体管,其特征在于,具有高介电常数的该第二介电层包含HfSiON、Ta2O5、TiO2、Al2O3、ZrO2、HfO2、Y2O3、La2O3、铝酸盐、硅酸盐、PbTiO3、BaTiO3、SrTiO3或PbZrO3。
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