CN100481491C - 薄膜晶体管及其制造方法 - Google Patents
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Abstract
一种通过在第一掺杂物注入步骤中使用栅极(10)作为掩膜制造的具有覆盖其沟道的栅极(10)的多晶硅GOLDD薄膜晶体管。然后毗邻栅极(10)形成包括在蚀刻处理中被圆角(17)限定的金属层(19)部分的间隔(13、14)。然后间隔和栅极被用作用于掺杂源区和漏区的掩膜，从而提供一种能够自对准制造技术。
Description
本发明涉及一种薄膜晶体管(TFT)，例如其可被用在有源液晶显示器(AMLCD)或其他平面显示器中。
在本领域中众所周知，薄膜晶体管(TFT)被用于AMLCD和其他平面显示器中，以控制显示器的各个像素的状态。例如如第US-A-5130829号美国专利所述，利用多晶硅半导体膜，它们可被制造在譬如玻璃或塑料材料的廉价绝缘基底上。
普通的TFT由一个如二氧化硅的绝缘层、具有一个形成在二氧化硅层上并延伸在多掺杂源区和漏区间的多晶硅沟道组成。非晶硅层经退火处理可形成多晶硅层，如S.D.Brotherton和D.J.McCulloch等于97年10月15日在J.Appl.Phys.82(8)上说明的这可使用受激准分子激光器实现。该沟道被栅极区依次覆盖的绝缘层覆盖。可以通过在多晶硅层中离子注入产生多掺杂源区和漏区，使用栅极作为掩膜以获得自对准结构。
这种普通结构具有的问题是在高漏偏压，例如>10V处可发生热载流子不稳定性，这使通常使用在这样电压中的TFT，尤其用在AMLCD中的TFT丧失功能。同样，由于多晶硅沟道和多掺杂漏区的缺陷，在晶体管关闭状态中可发生漏电流。该缺陷也可在晶体管导通状态中降低沟道迁移率。
已提出的一些观点，使用包含一个在不掺杂多晶硅沟道和多掺杂漏区的轻掺杂漏极(LDD)区以释放漏极场。US-A-5786241披露了一种具有在栅极下的不掺杂多晶硅沟道和多掺杂漏区间的LDD区的多晶硅沟道TFT。相应的轻掺杂区也被形成在多掺杂源区和不掺杂沟道间。LDD区在关闭状态中降低峰值场和降低峰值电流。使用栅极作为掩膜经离子注入轻掺杂制造LDD区。然后在栅极的对面形成不掺杂绝缘二氧化硅的间隔区，并使用栅极和间隔区作为掩膜经离子注入多掺杂多晶硅层，这样在在多掺杂源区和漏区与栅极下的不掺杂沟道之间的间隔区下形成LDD区。
这些LDD区的缺点是它们有害地影响了导通状态中的沟道电流。
又提出了安置TFT的栅极，以使它覆盖LDD区以提供栅极覆盖LDD或GOLDD区。栅极应用场至LDD区作为覆盖配置的结果，这有利于降低晶体管的导通状态中的电阻。参考S.S.Brotherton和J.R.Ayres等发表于ElectrochemicalSoc.Proc.Vol.98-22(1998).pp25-43的“The Technology and Application ofLaser Crystallised Poly-Si TFTs”。该论述了GOLDD TFTs的参数并提出通过执行首先在TFT的沟道中形成LDD区、然后覆盖栅极以形成GOLDD配置的GOLDD区的制造方法。
本发明尝试提出一种具有能通过自对准(SA)技术制造GOLDD区的TFT。
依据本发明，提供一种TFT，其包括一个在源区和漏区间延伸的多晶硅沟道、一个覆盖该沟道的栅极、和其中的厚度限定直立栅极侧壁、LDD区和覆盖LDD区的间隔，其中间隔包括既能覆盖LDD区又能沿直立栅极侧壁延伸的导电区。
优选地，导电区包括一个比栅极的厚度薄且具有覆盖LDD区的第一部分和沿栅极的直立侧壁延伸的第二部分的层。
本发明也包含一种制造具有一个覆盖沟道并具有直立栅极侧壁的栅极的多晶硅沟道TFT的方法，该方法包括：
(a)提供一个通过一个绝缘层从多晶硅层中分离的栅极；
(b)使用栅极作为掩膜，将掺杂物注入多晶硅层；
(c)在步骤(b)后形成一个毗邻栅极包括覆盖多晶硅层并沿栅极侧壁延伸的导电区的间隔；和
(d)使用栅极和间隔作为掩膜，将掺杂物注入多晶硅层以形成源区或漏区，以使间隔覆盖在多晶硅层中位于源区或漏区和沟道之间的LDD区。
通过在沟道和栅极上方沉积导电材料层可以形成间隔，并选择蚀刻导电材料的沉积层以形成具有覆盖沟道的第一部分和沿栅极的侧壁延伸的第二部分的间隔。沉积层可具有一个小于栅极厚度的厚度。其可以是一个导电材料的非顺形层。在优选具体实施例中，其包含通过溅射沉积的金属层。
导电层的选择蚀刻可以通过形成覆盖其第一部分的圆角实现，并且选择蚀刻该层不被圆角保护。
可以是顺形Si包含层的另一层例如通过PECVD可沉积在所述导电层上，并且选择蚀刻以形成圆角。
为了更充分理解本发明，现参考附图说明现有技术和本发明的具体实施例，其中：
图1A和1B分别是包括有TFT的公知有源板和公知AMLCD的示意性图解；
图2是依据本发明具体实施例的TFT的示意性截面图；和
图3A-3G是为了制造图2所示TFT执行的处理步骤的示意性剖面图。
参考图1A，一个AMLCD板的有源板30包括一个可以透射光的平面支座1，以实质上本领域公知的方式在其上提供一个LCD像素P的有源转换矩阵。像素Px，y被布置以矩形x、y阵列排列，并被x和y驱动电路D1、D2操作。众所周知，如图1B中示意所示，通过在有源板30和无源板34间夹入一层液晶材料32可以形成AMLCD板。
使用例子考虑像素P0，0，其包含一个通过一个其栅极连接到驱动线x0和其源极连接到驱动线y0的TFT0，0在不同的光透射性间转换的液晶显示单元L0，0，TFT的漏极连接到显示单元L0，0，并通过应用合适的电压至线x0和y0上，晶体管TFT0，0就能在导通和关闭间转换，从而控制LCD单元L0，0的操作。可以理解显示器的各个像素P具有同样的结构，并x和y驱动电路D1、D2以实质上公知的方式操作、一排排地扫描像素。
图2说明了依据本发明的TFT，其可以被用于如图1A和1B显示配置的有源板或AMLCD中。TFT是以截面显示、被形成在玻璃或塑料基底1上、并包括氮化硅层2、通过PECVD形成、被二氧化硅层3覆盖，也可以本领域公知的方式通过PECVD沉积。
TFT具有一个被形成在多晶硅层4中的沟道11，其开始作为非晶硅沉积、然后退火为多晶硅形式，其被多掺杂n+以形成具有金属电阻连接7、8的源区和漏区5、6。自身被可由如AI或Ti的金属或合金形成的导电栅极区10覆盖的二氧化硅层9覆盖多晶硅层4，其中合金如AI(1％Ti)。
多晶硅层4包含一个与n-掺杂的LDD区12a、12b一起位于栅极9的下面的不掺杂沟道区11，LDD区12a、12b在多掺杂n+区5、6和不掺杂区11之间。
间隔区13、14覆盖LDD区12a、12b。间隔区13、14由在沿LDD区12a、12b之上的两个氧化层9延伸并也沿栅极10的直立侧壁15、16延伸的层中沉积导电材料制造，在这个例子中是金属。这样，如图2所示，间隔区包含沿栅极10的上面伸展侧壁15、16延伸的第一部分13a、14a和沿绝缘氧化层9的表面延伸的第二部分13b、14b，以覆盖LDD区12a、12b。譬如n+Si或二氧化硅的材料的圆角17覆盖间隔区13b、14b。二氧化硅的绝缘层18覆盖整个器件。
现参考图3更详细说明制造图2的器件的方法。参考图3A，准备玻璃基底1，其使用通常的PECVD技术沉积一层100nm厚的氮化硅层2。此后，生长300-400nm厚的二氧化硅层。
然后，使用PECVD沉积40nm厚的非晶硅层4。譬如使用受激准分子激光器使非晶硅层4退火，以使层4被转变成多晶硅。此后，生长40-150nm厚的二氧化硅层5。进一步细节参考S.D.Brotherton和D.J.McCulloch等于97年10月15日在J.Appl.Phys.82(8)上的说明。
此后，通过溅射沉积沉积0.5-1μm厚的金属层。然后，使用通常的光刻和蚀刻技术制版合成金属层，以限定如图3A所示的栅极区10。
参考图3B，为了形成LDD区12a、12b，栅极区10被作为掩膜以允许相对低浓度的掺杂物沉积在层4中。在栅极10提供的掩膜下的层4的区在该处理中保持不掺杂。掺杂物可包括P离子，以获得一个3E12-3E13个原子/cm-2的掺杂浓度。
参考图3C，通过譬如溅射的标准非顺形技术在器件的上表面沉积50-150nm厚的例如Cr的薄金属层19。层19的厚度基本上小于栅极区10的厚度，以使溅射处理不必过加热基底1，从而损害基底1。
参考图3D，通过溅射或PECVD沉积一般为0.5μm-1.0μm厚的例如n+Si的顺形层20，然后进行非均匀性或平面刻蚀，如反应离子刻蚀(RIE)以提供电绝缘圆角17。
此后，蚀刻金属层19以剔除不被圆角17覆盖的金属区。结果构造显示在图3F中。用于薄Cr层19的合适的湿蚀刻剂是一种六硝酸柿酸铵(ammoniumhexa-nitrato-cerate)(IV)和硝酸的水溶液混合物。然而，其它使用湿或干蚀刻剂可以更适合蚀刻、用于层19的金属和合金，这对本领域技术人员而言是显而易见的。蚀刻处理形成被安置在栅极10对面的具有沿栅极10的直立侧沿15、16延伸的区13a、14a和沿氧化层9的表面延伸的区13b、14b的导电间隔区13、14。
在多掺杂源区和漏区5、6的注入时，间隔区13、14与圆角17一起被用作掩膜。最终，P离子以箭头X方向被导入基底以逐渐被注入层4，从而形成源区和漏区5、6。预先轻掺杂的区域12a、12b被间隔区13、14与圆角17屏蔽。这样，获得了GOLDD结构。导体区13、14与栅极区10电连接，以延伸栅极的侧边；区域13、14形成栅极的部分并覆盖LDD区12a、12b。
此后，如图3G所示，通过PECVD沉积例如300nm厚的二氧化硅钝化层18。随后，通过普通的的制版和沉积技术沉积金属源极和漏极7、8(显示在图2中)，以允许外部电连接多掺杂源区和漏区5、6。
使用普通的TFT，在漏极偏压>10V处发生热载流子不稳定性；而依据本发明的TFT，能最高稳定至20V。
这里说明的制造技术的优点是使用在现代TFT生产中容易获得的标准沉积技术，即溅射沉积和CVD。溅射沉积可被用于形成间隔区13、14的金属层19，和PECVD沉积可被用于形成圆角17的Si基底层20。因此，使用对已用于TFT制造的处理技术的简单改良，就可制造说明的TFT，而不必引入更多复杂沉积技术。
通过理解本发明，其它变化和改良对于本领域技术人员是显而易见的。这些变化和改良可包含等效物和在包括TFT和其它半导体器件及其中的元件部分的设计、制造和使用中已经公知的以及可被替代使用的其它特征或除在这里已经描述之外的特征。尽管在这个申请中对特征的部分组合阐明权利要求，应当理解本发明的披露的范围也包含在这里明确或含蓄披露的任何新特征或新特征组合或从其中的任何概括，无论其是否涉及与在任何权利要求中目前要求的相同的发明，以及无论其是否解决与本发明一样的任一或全部的同样的技术问题。因此，在实现本申请或任何进一步来源于此的申请时，该申请给出了可由这些特征和/或这些特征组合阐明的新权利要求的提示。
Claims (18)
1、一种薄膜晶体管，其包括在源区和漏区间延伸的多晶硅沟道，覆盖该沟道的栅极，和其中的厚度限定直立栅极侧壁，轻掺杂漏极区和覆盖轻掺杂漏极区的间隔，其中间隔包括导电区，该导电区包括一个比所述栅极的厚度薄且具有覆盖所述轻掺杂漏极区的第二部分和沿所述直立栅极侧壁延伸的第一部分的层。
2、依据权利要求1所述的薄膜晶体管，其中所述导电区包括一个导电材料层。
3、依据权利要求2所述的薄膜晶体管，其中所述导电材料层是一个通过溅射沉积的金属层。
4、依据权利要求2所述的薄膜晶体管，其中所述导电材料层包括一个掺杂半导体材料。
5、依据权利要求1至4中任一个所述的薄膜晶体管，包含一个在导电区的第一部分上方的圆角。
6、一种用于有源矩阵显示器的有源板，包含依据任何前述权利要求的薄膜晶体管。
7、一种有源矩阵液晶显示器，包括一个依据权利要求6的有源板、一个无源板、一个夹在有源板和无源板之间的液晶材料层。
8、一种制造具有覆盖其沟道并具有直立栅极侧壁的栅极的多晶硅沟道薄膜晶体管的方法，该方法包括步骤：
提供一个使用一个绝缘层从多晶硅层中分离出的栅极；
使用栅极作为掩膜，将掺杂物注入多晶硅层；
在注入多晶硅层后形成一个毗邻栅极包括覆盖多晶硅层并沿栅极侧壁延伸的厚度比所述栅极薄的导电区的间隔；和
使用栅极和间隔作为掩膜，将掺杂物注入多晶硅层以形成源区或漏区，以使间隔覆盖在多晶硅层中位于源区或漏区和沟道之间的轻掺杂漏极区。
9、依据权利要求8的方法，其中形成间隔的步骤包括：包含在多晶硅层和栅极上方沉积导电材料层，以及选择蚀刻沉积的导电材料层以形成具有覆盖多晶硅层的第一部分和沿栅极的侧壁延伸的第二部分的间隔。
10、依据权利要求9的方法，包含沉积其厚度小于栅极厚度的导电材料层。
11、依据权利要求9或10的方法，在所述栅极上沉积一非顺形层，该非顺形层中包含一导电材料。
12、依据权利要求9或10的方法，包含通过溅射沉积层。
13、依据权利要求9或10的方法，包含沉积所述层作为金属层。
14、依据权利要求9或10的方法，其中通过在其的第一部分上方形成一个圆角实现导电层的选择蚀刻，并且圆角不保护选择蚀刻层。
15、依据权利要求12的方法，包含在所述导电层上沉积另一层，并选择蚀刻该另一层以形成圆角。
16、依据权利要求15的方法，包含沉积另一层作为顺形层。
17、依据权利要求15的方法，包含沉积另一层作为Si包含层。
18、依据权利要求14的方法，包含通过化学汽相沉积法沉积另一层。
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| GBGB0225205.4A GB0225205D0 (en) | 2002-10-30 | 2002-10-30 | Thin film transistors and methods of manufacture thereof |
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| EP (1) | EP1559142A1 (zh) |
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| CN (1) | CN100481491C (zh) |
| AU (1) | AU2003267765A1 (zh) |
| GB (1) | GB0225205D0 (zh) |
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| CN101506863B (zh) * | 2006-11-30 | 2011-01-05 | 夏普株式会社 | 显示装置及显示装置的驱动方法 |
| US8878177B2 (en) * | 2011-11-11 | 2014-11-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| JP6063117B2 (ja) * | 2011-11-11 | 2017-01-18 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| US8796683B2 (en) * | 2011-12-23 | 2014-08-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| CN107516471B (zh) * | 2013-03-18 | 2019-10-25 | 松下电器产业株式会社 | 发光面板 |
| KR102180554B1 (ko) * | 2013-12-04 | 2020-11-19 | 삼성디스플레이 주식회사 | 박막 트랜지스터 및 이의 제조 방법 |
| CN105789326B (zh) | 2016-05-13 | 2019-07-12 | 京东方科技集团股份有限公司 | 薄膜晶体管、阵列基板、显示面板以及显示装置及其制造方法 |
| US11257956B2 (en) | 2018-03-30 | 2022-02-22 | Intel Corporation | Thin film transistor with selectively doped oxide thin film |
| US11362215B2 (en) | 2018-03-30 | 2022-06-14 | Intel Corporation | Top-gate doped thin film transistor |
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| US5217913A (en) * | 1988-08-31 | 1993-06-08 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing an MIS device having lightly doped drain structure and conductive sidewall spacers |
| GB2245741A (en) * | 1990-06-27 | 1992-01-08 | Philips Electronic Associated | Active matrix liquid crystal devices |
| JP3325992B2 (ja) * | 1994-01-08 | 2002-09-17 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
| US5498555A (en) * | 1994-11-07 | 1996-03-12 | United Microelectronics Corporation | Method of making LDD with polysilicon and dielectric spacers |
| JP3762002B2 (ja) * | 1996-11-29 | 2006-03-29 | 株式会社東芝 | 薄膜トランジスタ、及び液晶表示装置 |
| US5953596A (en) * | 1996-12-19 | 1999-09-14 | Micron Technology, Inc. | Methods of forming thin film transistors |
| US6420758B1 (en) * | 1998-11-17 | 2002-07-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having an impurity region overlapping a gate electrode |
| US6501098B2 (en) * | 1998-11-25 | 2002-12-31 | Semiconductor Energy Laboratory Co, Ltd. | Semiconductor device |
| GB2354882B (en) * | 1999-03-10 | 2004-06-02 | Matsushita Electric Ind Co Ltd | Thin film transistor panel and their manufacturing method |
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- 2003-10-14 EP EP03748460A patent/EP1559142A1/en not_active Withdrawn
- 2003-10-14 KR KR1020057007499A patent/KR20050071643A/ko not_active Application Discontinuation
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| CN1708856A (zh) | 2005-12-14 |
| US20060071352A1 (en) | 2006-04-06 |
| JP2006505121A (ja) | 2006-02-09 |
| EP1559142A1 (en) | 2005-08-03 |
| TW200417040A (en) | 2004-09-01 |
| KR20050071643A (ko) | 2005-07-07 |
| WO2004040653A1 (en) | 2004-05-13 |
| GB0225205D0 (en) | 2002-12-11 |
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